rts5227.c 8.6 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * Roger Tseng <rogerable@realtek.com>
  21. */
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/mfd/rtsx_pci.h>
  25. #include "rtsx_pcr.h"
  26. static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  27. {
  28. u8 driving_3v3[4][3] = {
  29. {0x13, 0x13, 0x13},
  30. {0x96, 0x96, 0x96},
  31. {0x7F, 0x7F, 0x7F},
  32. {0x96, 0x96, 0x96},
  33. };
  34. u8 driving_1v8[4][3] = {
  35. {0x99, 0x99, 0x99},
  36. {0xAA, 0xAA, 0xAA},
  37. {0xFE, 0xFE, 0xFE},
  38. {0xB3, 0xB3, 0xB3},
  39. };
  40. u8 (*driving)[3], drive_sel;
  41. if (voltage == OUTPUT_3V3) {
  42. driving = driving_3v3;
  43. drive_sel = pcr->sd30_drive_sel_3v3;
  44. } else {
  45. driving = driving_1v8;
  46. drive_sel = pcr->sd30_drive_sel_1v8;
  47. }
  48. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  49. 0xFF, driving[drive_sel][0]);
  50. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  51. 0xFF, driving[drive_sel][1]);
  52. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  53. 0xFF, driving[drive_sel][2]);
  54. }
  55. static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  56. {
  57. u32 reg;
  58. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
  59. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  60. if (!rtsx_vendor_setting_valid(reg))
  61. return;
  62. pcr->aspm_en = rtsx_reg_to_aspm(reg);
  63. pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  64. pcr->card_drive_sel &= 0x3F;
  65. pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  66. rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
  67. dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  68. pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  69. if (rtsx_reg_check_reverse_socket(reg))
  70. pcr->flags |= PCR_REVERSE_SOCKET;
  71. }
  72. static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
  73. {
  74. /* Set relink_time to 0 */
  75. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
  76. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
  77. rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
  78. if (pm_state == HOST_ENTER_S3)
  79. rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
  80. rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
  81. }
  82. static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
  83. {
  84. u16 cap;
  85. rtsx_pci_init_cmd(pcr);
  86. /* Configure GPIO as output */
  87. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  88. /* Reset ASPM state to default value */
  89. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
  90. /* Switch LDO3318 source from DV33 to card_3v3 */
  91. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  92. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  93. /* LED shine disabled, set initial shine cycle period */
  94. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  95. /* Configure LTR */
  96. pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
  97. if (cap & PCI_EXP_DEVCTL2_LTR_EN)
  98. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
  99. /* Configure OBFF */
  100. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
  101. /* Configure driving */
  102. rts5227_fill_driving(pcr, OUTPUT_3V3);
  103. /* Configure force_clock_req */
  104. if (pcr->flags & PCR_REVERSE_SOCKET)
  105. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  106. AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
  107. else
  108. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  109. AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
  110. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
  111. return rtsx_pci_send_cmd(pcr, 100);
  112. }
  113. static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
  114. {
  115. /* Optimize RX sensitivity */
  116. return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
  117. }
  118. static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
  119. {
  120. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  121. }
  122. static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
  123. {
  124. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  125. }
  126. static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
  127. {
  128. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  129. }
  130. static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
  131. {
  132. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  133. }
  134. static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
  135. {
  136. int err;
  137. rtsx_pci_init_cmd(pcr);
  138. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  139. SD_POWER_MASK, SD_PARTIAL_POWER_ON);
  140. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  141. LDO3318_PWR_MASK, 0x02);
  142. err = rtsx_pci_send_cmd(pcr, 100);
  143. if (err < 0)
  144. return err;
  145. /* To avoid too large in-rush current */
  146. udelay(150);
  147. rtsx_pci_init_cmd(pcr);
  148. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  149. SD_POWER_MASK, SD_POWER_ON);
  150. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  151. LDO3318_PWR_MASK, 0x06);
  152. err = rtsx_pci_send_cmd(pcr, 100);
  153. if (err < 0)
  154. return err;
  155. return 0;
  156. }
  157. static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
  158. {
  159. rtsx_pci_init_cmd(pcr);
  160. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  161. SD_POWER_MASK | PMOS_STRG_MASK,
  162. SD_POWER_OFF | PMOS_STRG_400mA);
  163. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  164. LDO3318_PWR_MASK, 0X00);
  165. return rtsx_pci_send_cmd(pcr, 100);
  166. }
  167. static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  168. {
  169. int err;
  170. if (voltage == OUTPUT_3V3) {
  171. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
  172. if (err < 0)
  173. return err;
  174. } else if (voltage == OUTPUT_1V8) {
  175. err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
  176. if (err < 0)
  177. return err;
  178. err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
  179. if (err < 0)
  180. return err;
  181. } else {
  182. return -EINVAL;
  183. }
  184. /* set pad drive */
  185. rtsx_pci_init_cmd(pcr);
  186. rts5227_fill_driving(pcr, voltage);
  187. return rtsx_pci_send_cmd(pcr, 100);
  188. }
  189. static const struct pcr_ops rts5227_pcr_ops = {
  190. .fetch_vendor_settings = rts5227_fetch_vendor_settings,
  191. .extra_init_hw = rts5227_extra_init_hw,
  192. .optimize_phy = rts5227_optimize_phy,
  193. .turn_on_led = rts5227_turn_on_led,
  194. .turn_off_led = rts5227_turn_off_led,
  195. .enable_auto_blink = rts5227_enable_auto_blink,
  196. .disable_auto_blink = rts5227_disable_auto_blink,
  197. .card_power_on = rts5227_card_power_on,
  198. .card_power_off = rts5227_card_power_off,
  199. .switch_output_voltage = rts5227_switch_output_voltage,
  200. .cd_deglitch = NULL,
  201. .conv_clk_and_div_n = NULL,
  202. .force_power_down = rts5227_force_power_down,
  203. };
  204. /* SD Pull Control Enable:
  205. * SD_DAT[3:0] ==> pull up
  206. * SD_CD ==> pull up
  207. * SD_WP ==> pull up
  208. * SD_CMD ==> pull up
  209. * SD_CLK ==> pull down
  210. */
  211. static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
  212. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  213. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  214. 0,
  215. };
  216. /* SD Pull Control Disable:
  217. * SD_DAT[3:0] ==> pull down
  218. * SD_CD ==> pull up
  219. * SD_WP ==> pull down
  220. * SD_CMD ==> pull down
  221. * SD_CLK ==> pull down
  222. */
  223. static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
  224. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  225. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  226. 0,
  227. };
  228. /* MS Pull Control Enable:
  229. * MS CD ==> pull up
  230. * others ==> pull down
  231. */
  232. static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
  233. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  234. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  235. 0,
  236. };
  237. /* MS Pull Control Disable:
  238. * MS CD ==> pull up
  239. * others ==> pull down
  240. */
  241. static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
  242. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  243. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  244. 0,
  245. };
  246. void rts5227_init_params(struct rtsx_pcr *pcr)
  247. {
  248. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  249. pcr->num_slots = 2;
  250. pcr->ops = &rts5227_pcr_ops;
  251. pcr->flags = 0;
  252. pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
  253. pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
  254. pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
  255. pcr->aspm_en = ASPM_L1_EN;
  256. pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
  257. pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
  258. pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
  259. pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
  260. pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
  261. pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
  262. }