palmas.c 15 KB

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  1. /*
  2. * TI Palmas MFD Driver
  3. *
  4. * Copyright 2011-2012 Texas Instruments Inc.
  5. *
  6. * Author: Graeme Gregory <gg@slimlogic.co.uk>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #include <linux/module.h>
  15. #include <linux/moduleparam.h>
  16. #include <linux/init.h>
  17. #include <linux/slab.h>
  18. #include <linux/i2c.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/regmap.h>
  22. #include <linux/err.h>
  23. #include <linux/mfd/core.h>
  24. #include <linux/mfd/palmas.h>
  25. #include <linux/of_device.h>
  26. #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
  27. PALMAS_EXT_CONTROL_ENABLE2 | \
  28. PALMAS_EXT_CONTROL_NSLEEP)
  29. struct palmas_sleep_requestor_info {
  30. int id;
  31. int reg_offset;
  32. int bit_pos;
  33. };
  34. #define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
  35. [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
  36. .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
  37. .reg_offset = _offset, \
  38. .bit_pos = _pos, \
  39. }
  40. static struct palmas_sleep_requestor_info sleep_req_info[] = {
  41. EXTERNAL_REQUESTOR(REGEN1, 0, 0),
  42. EXTERNAL_REQUESTOR(REGEN2, 0, 1),
  43. EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
  44. EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
  45. EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
  46. EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
  47. EXTERNAL_REQUESTOR(REGEN3, 0, 6),
  48. EXTERNAL_REQUESTOR(SMPS12, 1, 0),
  49. EXTERNAL_REQUESTOR(SMPS3, 1, 1),
  50. EXTERNAL_REQUESTOR(SMPS45, 1, 2),
  51. EXTERNAL_REQUESTOR(SMPS6, 1, 3),
  52. EXTERNAL_REQUESTOR(SMPS7, 1, 4),
  53. EXTERNAL_REQUESTOR(SMPS8, 1, 5),
  54. EXTERNAL_REQUESTOR(SMPS9, 1, 6),
  55. EXTERNAL_REQUESTOR(SMPS10, 1, 7),
  56. EXTERNAL_REQUESTOR(LDO1, 2, 0),
  57. EXTERNAL_REQUESTOR(LDO2, 2, 1),
  58. EXTERNAL_REQUESTOR(LDO3, 2, 2),
  59. EXTERNAL_REQUESTOR(LDO4, 2, 3),
  60. EXTERNAL_REQUESTOR(LDO5, 2, 4),
  61. EXTERNAL_REQUESTOR(LDO6, 2, 5),
  62. EXTERNAL_REQUESTOR(LDO7, 2, 6),
  63. EXTERNAL_REQUESTOR(LDO8, 2, 7),
  64. EXTERNAL_REQUESTOR(LDO9, 3, 0),
  65. EXTERNAL_REQUESTOR(LDOLN, 3, 1),
  66. EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
  67. };
  68. static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
  69. {
  70. .reg_bits = 8,
  71. .val_bits = 8,
  72. .max_register = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
  73. PALMAS_PRIMARY_SECONDARY_PAD3),
  74. },
  75. {
  76. .reg_bits = 8,
  77. .val_bits = 8,
  78. .max_register = PALMAS_BASE_TO_REG(PALMAS_GPADC_BASE,
  79. PALMAS_GPADC_SMPS_VSEL_MONITORING),
  80. },
  81. {
  82. .reg_bits = 8,
  83. .val_bits = 8,
  84. .max_register = PALMAS_BASE_TO_REG(PALMAS_TRIM_GPADC_BASE,
  85. PALMAS_GPADC_TRIM16),
  86. },
  87. };
  88. static const struct regmap_irq palmas_irqs[] = {
  89. /* INT1 IRQs */
  90. [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
  91. .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
  92. },
  93. [PALMAS_PWRON_IRQ] = {
  94. .mask = PALMAS_INT1_STATUS_PWRON,
  95. },
  96. [PALMAS_LONG_PRESS_KEY_IRQ] = {
  97. .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
  98. },
  99. [PALMAS_RPWRON_IRQ] = {
  100. .mask = PALMAS_INT1_STATUS_RPWRON,
  101. },
  102. [PALMAS_PWRDOWN_IRQ] = {
  103. .mask = PALMAS_INT1_STATUS_PWRDOWN,
  104. },
  105. [PALMAS_HOTDIE_IRQ] = {
  106. .mask = PALMAS_INT1_STATUS_HOTDIE,
  107. },
  108. [PALMAS_VSYS_MON_IRQ] = {
  109. .mask = PALMAS_INT1_STATUS_VSYS_MON,
  110. },
  111. [PALMAS_VBAT_MON_IRQ] = {
  112. .mask = PALMAS_INT1_STATUS_VBAT_MON,
  113. },
  114. /* INT2 IRQs*/
  115. [PALMAS_RTC_ALARM_IRQ] = {
  116. .mask = PALMAS_INT2_STATUS_RTC_ALARM,
  117. .reg_offset = 1,
  118. },
  119. [PALMAS_RTC_TIMER_IRQ] = {
  120. .mask = PALMAS_INT2_STATUS_RTC_TIMER,
  121. .reg_offset = 1,
  122. },
  123. [PALMAS_WDT_IRQ] = {
  124. .mask = PALMAS_INT2_STATUS_WDT,
  125. .reg_offset = 1,
  126. },
  127. [PALMAS_BATREMOVAL_IRQ] = {
  128. .mask = PALMAS_INT2_STATUS_BATREMOVAL,
  129. .reg_offset = 1,
  130. },
  131. [PALMAS_RESET_IN_IRQ] = {
  132. .mask = PALMAS_INT2_STATUS_RESET_IN,
  133. .reg_offset = 1,
  134. },
  135. [PALMAS_FBI_BB_IRQ] = {
  136. .mask = PALMAS_INT2_STATUS_FBI_BB,
  137. .reg_offset = 1,
  138. },
  139. [PALMAS_SHORT_IRQ] = {
  140. .mask = PALMAS_INT2_STATUS_SHORT,
  141. .reg_offset = 1,
  142. },
  143. [PALMAS_VAC_ACOK_IRQ] = {
  144. .mask = PALMAS_INT2_STATUS_VAC_ACOK,
  145. .reg_offset = 1,
  146. },
  147. /* INT3 IRQs */
  148. [PALMAS_GPADC_AUTO_0_IRQ] = {
  149. .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
  150. .reg_offset = 2,
  151. },
  152. [PALMAS_GPADC_AUTO_1_IRQ] = {
  153. .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
  154. .reg_offset = 2,
  155. },
  156. [PALMAS_GPADC_EOC_SW_IRQ] = {
  157. .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
  158. .reg_offset = 2,
  159. },
  160. [PALMAS_GPADC_EOC_RT_IRQ] = {
  161. .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
  162. .reg_offset = 2,
  163. },
  164. [PALMAS_ID_OTG_IRQ] = {
  165. .mask = PALMAS_INT3_STATUS_ID_OTG,
  166. .reg_offset = 2,
  167. },
  168. [PALMAS_ID_IRQ] = {
  169. .mask = PALMAS_INT3_STATUS_ID,
  170. .reg_offset = 2,
  171. },
  172. [PALMAS_VBUS_OTG_IRQ] = {
  173. .mask = PALMAS_INT3_STATUS_VBUS_OTG,
  174. .reg_offset = 2,
  175. },
  176. [PALMAS_VBUS_IRQ] = {
  177. .mask = PALMAS_INT3_STATUS_VBUS,
  178. .reg_offset = 2,
  179. },
  180. /* INT4 IRQs */
  181. [PALMAS_GPIO_0_IRQ] = {
  182. .mask = PALMAS_INT4_STATUS_GPIO_0,
  183. .reg_offset = 3,
  184. },
  185. [PALMAS_GPIO_1_IRQ] = {
  186. .mask = PALMAS_INT4_STATUS_GPIO_1,
  187. .reg_offset = 3,
  188. },
  189. [PALMAS_GPIO_2_IRQ] = {
  190. .mask = PALMAS_INT4_STATUS_GPIO_2,
  191. .reg_offset = 3,
  192. },
  193. [PALMAS_GPIO_3_IRQ] = {
  194. .mask = PALMAS_INT4_STATUS_GPIO_3,
  195. .reg_offset = 3,
  196. },
  197. [PALMAS_GPIO_4_IRQ] = {
  198. .mask = PALMAS_INT4_STATUS_GPIO_4,
  199. .reg_offset = 3,
  200. },
  201. [PALMAS_GPIO_5_IRQ] = {
  202. .mask = PALMAS_INT4_STATUS_GPIO_5,
  203. .reg_offset = 3,
  204. },
  205. [PALMAS_GPIO_6_IRQ] = {
  206. .mask = PALMAS_INT4_STATUS_GPIO_6,
  207. .reg_offset = 3,
  208. },
  209. [PALMAS_GPIO_7_IRQ] = {
  210. .mask = PALMAS_INT4_STATUS_GPIO_7,
  211. .reg_offset = 3,
  212. },
  213. };
  214. static struct regmap_irq_chip palmas_irq_chip = {
  215. .name = "palmas",
  216. .irqs = palmas_irqs,
  217. .num_irqs = ARRAY_SIZE(palmas_irqs),
  218. .num_regs = 4,
  219. .irq_reg_stride = 5,
  220. .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
  221. PALMAS_INT1_STATUS),
  222. .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
  223. PALMAS_INT1_MASK),
  224. };
  225. int palmas_ext_control_req_config(struct palmas *palmas,
  226. enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
  227. {
  228. int preq_mask_bit = 0;
  229. int reg_add = 0;
  230. int bit_pos;
  231. int ret;
  232. if (!(ext_ctrl & PALMAS_EXT_REQ))
  233. return 0;
  234. if (id >= PALMAS_EXTERNAL_REQSTR_ID_MAX)
  235. return 0;
  236. if (ext_ctrl & PALMAS_EXT_CONTROL_NSLEEP) {
  237. reg_add = PALMAS_NSLEEP_RES_ASSIGN;
  238. preq_mask_bit = 0;
  239. } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE1) {
  240. reg_add = PALMAS_ENABLE1_RES_ASSIGN;
  241. preq_mask_bit = 1;
  242. } else if (ext_ctrl & PALMAS_EXT_CONTROL_ENABLE2) {
  243. reg_add = PALMAS_ENABLE2_RES_ASSIGN;
  244. preq_mask_bit = 2;
  245. }
  246. bit_pos = sleep_req_info[id].bit_pos;
  247. reg_add += sleep_req_info[id].reg_offset;
  248. if (enable)
  249. ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
  250. reg_add, BIT(bit_pos), BIT(bit_pos));
  251. else
  252. ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
  253. reg_add, BIT(bit_pos), 0);
  254. if (ret < 0) {
  255. dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
  256. reg_add, ret);
  257. return ret;
  258. }
  259. /* Unmask the PREQ */
  260. ret = palmas_update_bits(palmas, PALMAS_PMU_CONTROL_BASE,
  261. PALMAS_POWER_CTRL, BIT(preq_mask_bit), 0);
  262. if (ret < 0) {
  263. dev_err(palmas->dev, "POWER_CTRL register update failed %d\n",
  264. ret);
  265. return ret;
  266. }
  267. return ret;
  268. }
  269. EXPORT_SYMBOL_GPL(palmas_ext_control_req_config);
  270. static int palmas_set_pdata_irq_flag(struct i2c_client *i2c,
  271. struct palmas_platform_data *pdata)
  272. {
  273. struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
  274. if (!irq_data) {
  275. dev_err(&i2c->dev, "Invalid IRQ: %d\n", i2c->irq);
  276. return -EINVAL;
  277. }
  278. pdata->irq_flags = irqd_get_trigger_type(irq_data);
  279. dev_info(&i2c->dev, "Irq flag is 0x%08x\n", pdata->irq_flags);
  280. return 0;
  281. }
  282. static void palmas_dt_to_pdata(struct i2c_client *i2c,
  283. struct palmas_platform_data *pdata)
  284. {
  285. struct device_node *node = i2c->dev.of_node;
  286. int ret;
  287. u32 prop;
  288. ret = of_property_read_u32(node, "ti,mux-pad1", &prop);
  289. if (!ret) {
  290. pdata->mux_from_pdata = 1;
  291. pdata->pad1 = prop;
  292. }
  293. ret = of_property_read_u32(node, "ti,mux-pad2", &prop);
  294. if (!ret) {
  295. pdata->mux_from_pdata = 1;
  296. pdata->pad2 = prop;
  297. }
  298. /* The default for this register is all masked */
  299. ret = of_property_read_u32(node, "ti,power-ctrl", &prop);
  300. if (!ret)
  301. pdata->power_ctrl = prop;
  302. else
  303. pdata->power_ctrl = PALMAS_POWER_CTRL_NSLEEP_MASK |
  304. PALMAS_POWER_CTRL_ENABLE1_MASK |
  305. PALMAS_POWER_CTRL_ENABLE2_MASK;
  306. if (i2c->irq)
  307. palmas_set_pdata_irq_flag(i2c, pdata);
  308. pdata->pm_off = of_property_read_bool(node,
  309. "ti,system-power-controller");
  310. }
  311. static struct palmas *palmas_dev;
  312. static void palmas_power_off(void)
  313. {
  314. unsigned int addr;
  315. int ret, slave;
  316. if (!palmas_dev)
  317. return;
  318. slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
  319. addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_DEV_CTRL);
  320. ret = regmap_update_bits(
  321. palmas_dev->regmap[slave],
  322. addr,
  323. PALMAS_DEV_CTRL_DEV_ON,
  324. 0);
  325. if (ret)
  326. pr_err("%s: Unable to write to DEV_CTRL_DEV_ON: %d\n",
  327. __func__, ret);
  328. }
  329. static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
  330. static unsigned int tps659038_features;
  331. static const struct of_device_id of_palmas_match_tbl[] = {
  332. {
  333. .compatible = "ti,palmas",
  334. .data = &palmas_features,
  335. },
  336. {
  337. .compatible = "ti,tps659038",
  338. .data = &tps659038_features,
  339. },
  340. { },
  341. };
  342. static int palmas_i2c_probe(struct i2c_client *i2c,
  343. const struct i2c_device_id *id)
  344. {
  345. struct palmas *palmas;
  346. struct palmas_platform_data *pdata;
  347. struct device_node *node = i2c->dev.of_node;
  348. int ret = 0, i;
  349. unsigned int reg, addr, *features;
  350. int slave;
  351. const struct of_device_id *match;
  352. pdata = dev_get_platdata(&i2c->dev);
  353. if (node && !pdata) {
  354. pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
  355. if (!pdata)
  356. return -ENOMEM;
  357. palmas_dt_to_pdata(i2c, pdata);
  358. }
  359. if (!pdata)
  360. return -EINVAL;
  361. palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL);
  362. if (palmas == NULL)
  363. return -ENOMEM;
  364. i2c_set_clientdata(i2c, palmas);
  365. palmas->dev = &i2c->dev;
  366. palmas->irq = i2c->irq;
  367. match = of_match_device(of_match_ptr(of_palmas_match_tbl), &i2c->dev);
  368. if (!match)
  369. return -ENODATA;
  370. features = (unsigned int *)match->data;
  371. palmas->features = *features;
  372. for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
  373. if (i == 0)
  374. palmas->i2c_clients[i] = i2c;
  375. else {
  376. palmas->i2c_clients[i] =
  377. i2c_new_dummy(i2c->adapter,
  378. i2c->addr + i);
  379. if (!palmas->i2c_clients[i]) {
  380. dev_err(palmas->dev,
  381. "can't attach client %d\n", i);
  382. ret = -ENOMEM;
  383. goto err;
  384. }
  385. palmas->i2c_clients[i]->dev.of_node = of_node_get(node);
  386. }
  387. palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
  388. &palmas_regmap_config[i]);
  389. if (IS_ERR(palmas->regmap[i])) {
  390. ret = PTR_ERR(palmas->regmap[i]);
  391. dev_err(palmas->dev,
  392. "Failed to allocate regmap %d, err: %d\n",
  393. i, ret);
  394. goto err;
  395. }
  396. }
  397. if (!palmas->irq) {
  398. dev_warn(palmas->dev, "IRQ missing: skipping irq request\n");
  399. goto no_irq;
  400. }
  401. /* Change interrupt line output polarity */
  402. if (pdata->irq_flags & IRQ_TYPE_LEVEL_HIGH)
  403. reg = PALMAS_POLARITY_CTRL_INT_POLARITY;
  404. else
  405. reg = 0;
  406. ret = palmas_update_bits(palmas, PALMAS_PU_PD_OD_BASE,
  407. PALMAS_POLARITY_CTRL, PALMAS_POLARITY_CTRL_INT_POLARITY,
  408. reg);
  409. if (ret < 0) {
  410. dev_err(palmas->dev, "POLARITY_CTRL updat failed: %d\n", ret);
  411. goto err;
  412. }
  413. /* Change IRQ into clear on read mode for efficiency */
  414. slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
  415. addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
  416. reg = PALMAS_INT_CTRL_INT_CLEAR;
  417. regmap_write(palmas->regmap[slave], addr, reg);
  418. ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
  419. IRQF_ONESHOT | pdata->irq_flags, 0, &palmas_irq_chip,
  420. &palmas->irq_data);
  421. if (ret < 0)
  422. goto err;
  423. no_irq:
  424. slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
  425. addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
  426. PALMAS_PRIMARY_SECONDARY_PAD1);
  427. if (pdata->mux_from_pdata) {
  428. reg = pdata->pad1;
  429. ret = regmap_write(palmas->regmap[slave], addr, reg);
  430. if (ret)
  431. goto err_irq;
  432. } else {
  433. ret = regmap_read(palmas->regmap[slave], addr, &reg);
  434. if (ret)
  435. goto err_irq;
  436. }
  437. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0))
  438. palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED;
  439. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK))
  440. palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED;
  441. else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
  442. (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
  443. palmas->led_muxed |= PALMAS_LED1_MUXED;
  444. else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) ==
  445. (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT))
  446. palmas->pwm_muxed |= PALMAS_PWM1_MUXED;
  447. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK))
  448. palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED;
  449. else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
  450. (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
  451. palmas->led_muxed |= PALMAS_LED2_MUXED;
  452. else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) ==
  453. (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT))
  454. palmas->pwm_muxed |= PALMAS_PWM2_MUXED;
  455. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3))
  456. palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED;
  457. addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
  458. PALMAS_PRIMARY_SECONDARY_PAD2);
  459. if (pdata->mux_from_pdata) {
  460. reg = pdata->pad2;
  461. ret = regmap_write(palmas->regmap[slave], addr, reg);
  462. if (ret)
  463. goto err_irq;
  464. } else {
  465. ret = regmap_read(palmas->regmap[slave], addr, &reg);
  466. if (ret)
  467. goto err_irq;
  468. }
  469. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4))
  470. palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED;
  471. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK))
  472. palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED;
  473. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6))
  474. palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED;
  475. if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK))
  476. palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED;
  477. dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n",
  478. palmas->gpio_muxed, palmas->pwm_muxed,
  479. palmas->led_muxed);
  480. reg = pdata->power_ctrl;
  481. slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE);
  482. addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL);
  483. ret = regmap_write(palmas->regmap[slave], addr, reg);
  484. if (ret)
  485. goto err_irq;
  486. /*
  487. * If we are probing with DT do this the DT way and return here
  488. * otherwise continue and add devices using mfd helpers.
  489. */
  490. if (node) {
  491. ret = of_platform_populate(node, NULL, NULL, &i2c->dev);
  492. if (ret < 0) {
  493. goto err_irq;
  494. } else if (pdata->pm_off && !pm_power_off) {
  495. palmas_dev = palmas;
  496. pm_power_off = palmas_power_off;
  497. return ret;
  498. }
  499. }
  500. return ret;
  501. err_irq:
  502. regmap_del_irq_chip(palmas->irq, palmas->irq_data);
  503. err:
  504. return ret;
  505. }
  506. static int palmas_i2c_remove(struct i2c_client *i2c)
  507. {
  508. struct palmas *palmas = i2c_get_clientdata(i2c);
  509. mfd_remove_devices(palmas->dev);
  510. regmap_del_irq_chip(palmas->irq, palmas->irq_data);
  511. return 0;
  512. }
  513. static const struct i2c_device_id palmas_i2c_id[] = {
  514. { "palmas", },
  515. { "twl6035", },
  516. { "twl6037", },
  517. { "tps65913", },
  518. { /* end */ }
  519. };
  520. MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
  521. static struct i2c_driver palmas_i2c_driver = {
  522. .driver = {
  523. .name = "palmas",
  524. .of_match_table = of_palmas_match_tbl,
  525. .owner = THIS_MODULE,
  526. },
  527. .probe = palmas_i2c_probe,
  528. .remove = palmas_i2c_remove,
  529. .id_table = palmas_i2c_id,
  530. };
  531. static int __init palmas_i2c_init(void)
  532. {
  533. return i2c_add_driver(&palmas_i2c_driver);
  534. }
  535. /* init early so consumer devices can complete system boot */
  536. subsys_initcall(palmas_i2c_init);
  537. static void __exit palmas_i2c_exit(void)
  538. {
  539. i2c_del_driver(&palmas_i2c_driver);
  540. }
  541. module_exit(palmas_i2c_exit);
  542. MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
  543. MODULE_DESCRIPTION("Palmas chip family multi-function driver");
  544. MODULE_LICENSE("GPL");