arizona-core.c 25 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/regulator/machine.h>
  25. #include <linux/slab.h>
  26. #include <linux/mfd/arizona/core.h>
  27. #include <linux/mfd/arizona/registers.h>
  28. #include "arizona.h"
  29. static const char *wm5102_core_supplies[] = {
  30. "AVDD",
  31. "DBVDD1",
  32. };
  33. int arizona_clk32k_enable(struct arizona *arizona)
  34. {
  35. int ret = 0;
  36. mutex_lock(&arizona->clk_lock);
  37. arizona->clk32k_ref++;
  38. if (arizona->clk32k_ref == 1) {
  39. switch (arizona->pdata.clk32k_src) {
  40. case ARIZONA_32KZ_MCLK1:
  41. ret = pm_runtime_get_sync(arizona->dev);
  42. if (ret != 0)
  43. goto out;
  44. break;
  45. }
  46. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  47. ARIZONA_CLK_32K_ENA,
  48. ARIZONA_CLK_32K_ENA);
  49. }
  50. out:
  51. if (ret != 0)
  52. arizona->clk32k_ref--;
  53. mutex_unlock(&arizona->clk_lock);
  54. return ret;
  55. }
  56. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  57. int arizona_clk32k_disable(struct arizona *arizona)
  58. {
  59. int ret = 0;
  60. mutex_lock(&arizona->clk_lock);
  61. BUG_ON(arizona->clk32k_ref <= 0);
  62. arizona->clk32k_ref--;
  63. if (arizona->clk32k_ref == 0) {
  64. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  65. ARIZONA_CLK_32K_ENA, 0);
  66. switch (arizona->pdata.clk32k_src) {
  67. case ARIZONA_32KZ_MCLK1:
  68. pm_runtime_put_sync(arizona->dev);
  69. break;
  70. }
  71. }
  72. mutex_unlock(&arizona->clk_lock);
  73. return ret;
  74. }
  75. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  76. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  77. {
  78. struct arizona *arizona = data;
  79. dev_err(arizona->dev, "CLKGEN error\n");
  80. return IRQ_HANDLED;
  81. }
  82. static irqreturn_t arizona_underclocked(int irq, void *data)
  83. {
  84. struct arizona *arizona = data;
  85. unsigned int val;
  86. int ret;
  87. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  88. &val);
  89. if (ret != 0) {
  90. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  91. ret);
  92. return IRQ_NONE;
  93. }
  94. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF3 underclocked\n");
  96. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "AIF2 underclocked\n");
  98. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "AIF1 underclocked\n");
  100. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "ISRC2 underclocked\n");
  102. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ISRC1 underclocked\n");
  104. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "FX underclocked\n");
  106. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "ASRC underclocked\n");
  108. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "DAC underclocked\n");
  110. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  111. dev_err(arizona->dev, "ADC underclocked\n");
  112. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  113. dev_err(arizona->dev, "Mixer dropped sample\n");
  114. return IRQ_HANDLED;
  115. }
  116. static irqreturn_t arizona_overclocked(int irq, void *data)
  117. {
  118. struct arizona *arizona = data;
  119. unsigned int val[2];
  120. int ret;
  121. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  122. &val[0], 2);
  123. if (ret != 0) {
  124. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  125. ret);
  126. return IRQ_NONE;
  127. }
  128. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  129. dev_err(arizona->dev, "PWM overclocked\n");
  130. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "FX core overclocked\n");
  132. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "DAC SYS overclocked\n");
  134. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "DAC WARP overclocked\n");
  136. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "ADC overclocked\n");
  138. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "Mixer overclocked\n");
  140. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "AIF3 overclocked\n");
  142. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "AIF2 overclocked\n");
  144. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "AIF1 overclocked\n");
  146. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "Pad control overclocked\n");
  148. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  150. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "Slimbus async overclocked\n");
  152. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  154. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "ASRC async system overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  158. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  160. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  162. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "DSP1 overclocked\n");
  164. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  165. dev_err(arizona->dev, "ISRC2 overclocked\n");
  166. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  167. dev_err(arizona->dev, "ISRC1 overclocked\n");
  168. return IRQ_HANDLED;
  169. }
  170. static int arizona_poll_reg(struct arizona *arizona,
  171. int timeout, unsigned int reg,
  172. unsigned int mask, unsigned int target)
  173. {
  174. unsigned int val = 0;
  175. int ret, i;
  176. for (i = 0; i < timeout; i++) {
  177. ret = regmap_read(arizona->regmap, reg, &val);
  178. if (ret != 0) {
  179. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  180. reg, ret);
  181. continue;
  182. }
  183. if ((val & mask) == target)
  184. return 0;
  185. msleep(1);
  186. }
  187. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  188. return -ETIMEDOUT;
  189. }
  190. static int arizona_wait_for_boot(struct arizona *arizona)
  191. {
  192. int ret;
  193. /*
  194. * We can't use an interrupt as we need to runtime resume to do so,
  195. * we won't race with the interrupt handler as it'll be blocked on
  196. * runtime resume.
  197. */
  198. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  199. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  200. if (!ret)
  201. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  202. ARIZONA_BOOT_DONE_STS);
  203. pm_runtime_mark_last_busy(arizona->dev);
  204. return ret;
  205. }
  206. static int arizona_apply_hardware_patch(struct arizona* arizona)
  207. {
  208. unsigned int fll, sysclk;
  209. int ret, err;
  210. regcache_cache_bypass(arizona->regmap, true);
  211. /* Cache existing FLL and SYSCLK settings */
  212. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll);
  213. if (ret != 0) {
  214. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  215. ret);
  216. return ret;
  217. }
  218. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk);
  219. if (ret != 0) {
  220. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  221. ret);
  222. return ret;
  223. }
  224. /* Start up SYSCLK using the FLL in free running mode */
  225. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  226. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  227. if (ret != 0) {
  228. dev_err(arizona->dev,
  229. "Failed to start FLL in freerunning mode: %d\n",
  230. ret);
  231. return ret;
  232. }
  233. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  234. ARIZONA_FLL1_CLOCK_OK_STS,
  235. ARIZONA_FLL1_CLOCK_OK_STS);
  236. if (ret != 0) {
  237. ret = -ETIMEDOUT;
  238. goto err_fll;
  239. }
  240. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  241. if (ret != 0) {
  242. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  243. goto err_fll;
  244. }
  245. /* Start the write sequencer and wait for it to finish */
  246. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  247. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  248. if (ret != 0) {
  249. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  250. ret);
  251. goto err_sysclk;
  252. }
  253. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  254. ARIZONA_WSEQ_BUSY, 0);
  255. if (ret != 0) {
  256. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  257. ARIZONA_WSEQ_ABORT);
  258. ret = -ETIMEDOUT;
  259. }
  260. err_sysclk:
  261. err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk);
  262. if (err != 0) {
  263. dev_err(arizona->dev,
  264. "Failed to re-apply old SYSCLK settings: %d\n",
  265. err);
  266. }
  267. err_fll:
  268. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll);
  269. if (err != 0) {
  270. dev_err(arizona->dev,
  271. "Failed to re-apply old FLL settings: %d\n",
  272. err);
  273. }
  274. regcache_cache_bypass(arizona->regmap, false);
  275. if (ret != 0)
  276. return ret;
  277. else
  278. return err;
  279. }
  280. #ifdef CONFIG_PM_RUNTIME
  281. static int arizona_runtime_resume(struct device *dev)
  282. {
  283. struct arizona *arizona = dev_get_drvdata(dev);
  284. int ret;
  285. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  286. ret = regulator_enable(arizona->dcvdd);
  287. if (ret != 0) {
  288. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  289. return ret;
  290. }
  291. regcache_cache_only(arizona->regmap, false);
  292. switch (arizona->type) {
  293. case WM5102:
  294. if (arizona->external_dcvdd) {
  295. ret = regmap_update_bits(arizona->regmap,
  296. ARIZONA_ISOLATION_CONTROL,
  297. ARIZONA_ISOLATE_DCVDD1, 0);
  298. if (ret != 0) {
  299. dev_err(arizona->dev,
  300. "Failed to connect DCVDD: %d\n", ret);
  301. goto err;
  302. }
  303. }
  304. ret = wm5102_patch(arizona);
  305. if (ret != 0) {
  306. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  307. ret);
  308. goto err;
  309. }
  310. ret = arizona_apply_hardware_patch(arizona);
  311. if (ret != 0) {
  312. dev_err(arizona->dev,
  313. "Failed to apply hardware patch: %d\n",
  314. ret);
  315. goto err;
  316. }
  317. break;
  318. default:
  319. ret = arizona_wait_for_boot(arizona);
  320. if (ret != 0) {
  321. goto err;
  322. }
  323. if (arizona->external_dcvdd) {
  324. ret = regmap_update_bits(arizona->regmap,
  325. ARIZONA_ISOLATION_CONTROL,
  326. ARIZONA_ISOLATE_DCVDD1, 0);
  327. if (ret != 0) {
  328. dev_err(arizona->dev,
  329. "Failed to connect DCVDD: %d\n", ret);
  330. goto err;
  331. }
  332. }
  333. break;
  334. }
  335. switch (arizona->type) {
  336. case WM5102:
  337. ret = wm5102_patch(arizona);
  338. if (ret != 0) {
  339. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  340. ret);
  341. goto err;
  342. }
  343. default:
  344. break;
  345. }
  346. ret = regcache_sync(arizona->regmap);
  347. if (ret != 0) {
  348. dev_err(arizona->dev, "Failed to restore register cache\n");
  349. goto err;
  350. }
  351. return 0;
  352. err:
  353. regcache_cache_only(arizona->regmap, true);
  354. regulator_disable(arizona->dcvdd);
  355. return ret;
  356. }
  357. static int arizona_runtime_suspend(struct device *dev)
  358. {
  359. struct arizona *arizona = dev_get_drvdata(dev);
  360. int ret;
  361. dev_dbg(arizona->dev, "Entering AoD mode\n");
  362. if (arizona->external_dcvdd) {
  363. ret = regmap_update_bits(arizona->regmap,
  364. ARIZONA_ISOLATION_CONTROL,
  365. ARIZONA_ISOLATE_DCVDD1,
  366. ARIZONA_ISOLATE_DCVDD1);
  367. if (ret != 0) {
  368. dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n",
  369. ret);
  370. return ret;
  371. }
  372. }
  373. regcache_cache_only(arizona->regmap, true);
  374. regcache_mark_dirty(arizona->regmap);
  375. regulator_disable(arizona->dcvdd);
  376. return 0;
  377. }
  378. #endif
  379. #ifdef CONFIG_PM_SLEEP
  380. static int arizona_suspend(struct device *dev)
  381. {
  382. struct arizona *arizona = dev_get_drvdata(dev);
  383. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  384. disable_irq(arizona->irq);
  385. return 0;
  386. }
  387. static int arizona_suspend_late(struct device *dev)
  388. {
  389. struct arizona *arizona = dev_get_drvdata(dev);
  390. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  391. enable_irq(arizona->irq);
  392. return 0;
  393. }
  394. static int arizona_resume_noirq(struct device *dev)
  395. {
  396. struct arizona *arizona = dev_get_drvdata(dev);
  397. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  398. disable_irq(arizona->irq);
  399. return 0;
  400. }
  401. static int arizona_resume(struct device *dev)
  402. {
  403. struct arizona *arizona = dev_get_drvdata(dev);
  404. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  405. enable_irq(arizona->irq);
  406. return 0;
  407. }
  408. #endif
  409. const struct dev_pm_ops arizona_pm_ops = {
  410. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  411. arizona_runtime_resume,
  412. NULL)
  413. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  414. #ifdef CONFIG_PM_SLEEP
  415. .suspend_late = arizona_suspend_late,
  416. .resume_noirq = arizona_resume_noirq,
  417. #endif
  418. };
  419. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  420. #ifdef CONFIG_OF
  421. int arizona_of_get_type(struct device *dev)
  422. {
  423. const struct of_device_id *id = of_match_device(arizona_of_match, dev);
  424. if (id)
  425. return (int)id->data;
  426. else
  427. return 0;
  428. }
  429. EXPORT_SYMBOL_GPL(arizona_of_get_type);
  430. static int arizona_of_get_core_pdata(struct arizona *arizona)
  431. {
  432. int ret, i;
  433. arizona->pdata.reset = of_get_named_gpio(arizona->dev->of_node,
  434. "wlf,reset", 0);
  435. if (arizona->pdata.reset < 0)
  436. arizona->pdata.reset = 0;
  437. arizona->pdata.ldoena = of_get_named_gpio(arizona->dev->of_node,
  438. "wlf,ldoena", 0);
  439. if (arizona->pdata.ldoena < 0)
  440. arizona->pdata.ldoena = 0;
  441. ret = of_property_read_u32_array(arizona->dev->of_node,
  442. "wlf,gpio-defaults",
  443. arizona->pdata.gpio_defaults,
  444. ARRAY_SIZE(arizona->pdata.gpio_defaults));
  445. if (ret >= 0) {
  446. /*
  447. * All values are literal except out of range values
  448. * which are chip default, translate into platform
  449. * data which uses 0 as chip default and out of range
  450. * as zero.
  451. */
  452. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  453. if (arizona->pdata.gpio_defaults[i] > 0xffff)
  454. arizona->pdata.gpio_defaults[i] = 0;
  455. if (arizona->pdata.gpio_defaults[i] == 0)
  456. arizona->pdata.gpio_defaults[i] = 0x10000;
  457. }
  458. } else {
  459. dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
  460. ret);
  461. }
  462. return 0;
  463. }
  464. const struct of_device_id arizona_of_match[] = {
  465. { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
  466. { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
  467. { .compatible = "wlf,wm8997", .data = (void *)WM8997 },
  468. {},
  469. };
  470. EXPORT_SYMBOL_GPL(arizona_of_match);
  471. #else
  472. static inline int arizona_of_get_core_pdata(struct arizona *arizona)
  473. {
  474. return 0;
  475. }
  476. #endif
  477. static struct mfd_cell early_devs[] = {
  478. { .name = "arizona-ldo1" },
  479. };
  480. static struct mfd_cell wm5102_devs[] = {
  481. { .name = "arizona-micsupp" },
  482. { .name = "arizona-extcon" },
  483. { .name = "arizona-gpio" },
  484. { .name = "arizona-haptics" },
  485. { .name = "arizona-pwm" },
  486. { .name = "wm5102-codec" },
  487. };
  488. static struct mfd_cell wm5110_devs[] = {
  489. { .name = "arizona-micsupp" },
  490. { .name = "arizona-extcon" },
  491. { .name = "arizona-gpio" },
  492. { .name = "arizona-haptics" },
  493. { .name = "arizona-pwm" },
  494. { .name = "wm5110-codec" },
  495. };
  496. static struct mfd_cell wm8997_devs[] = {
  497. { .name = "arizona-micsupp" },
  498. { .name = "arizona-extcon" },
  499. { .name = "arizona-gpio" },
  500. { .name = "arizona-haptics" },
  501. { .name = "arizona-pwm" },
  502. { .name = "wm8997-codec" },
  503. };
  504. int arizona_dev_init(struct arizona *arizona)
  505. {
  506. struct device *dev = arizona->dev;
  507. const char *type_name;
  508. unsigned int reg, val;
  509. int (*apply_patch)(struct arizona *) = NULL;
  510. int ret, i;
  511. dev_set_drvdata(arizona->dev, arizona);
  512. mutex_init(&arizona->clk_lock);
  513. arizona_of_get_core_pdata(arizona);
  514. if (dev_get_platdata(arizona->dev))
  515. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  516. sizeof(arizona->pdata));
  517. regcache_cache_only(arizona->regmap, true);
  518. switch (arizona->type) {
  519. case WM5102:
  520. case WM5110:
  521. case WM8997:
  522. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  523. arizona->core_supplies[i].supply
  524. = wm5102_core_supplies[i];
  525. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  526. break;
  527. default:
  528. dev_err(arizona->dev, "Unknown device type %d\n",
  529. arizona->type);
  530. return -EINVAL;
  531. }
  532. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  533. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  534. if (ret != 0) {
  535. dev_err(dev, "Failed to add early children: %d\n", ret);
  536. return ret;
  537. }
  538. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  539. arizona->core_supplies);
  540. if (ret != 0) {
  541. dev_err(dev, "Failed to request core supplies: %d\n",
  542. ret);
  543. goto err_early;
  544. }
  545. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  546. if (IS_ERR(arizona->dcvdd)) {
  547. ret = PTR_ERR(arizona->dcvdd);
  548. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  549. goto err_early;
  550. }
  551. if (arizona->pdata.reset) {
  552. /* Start out with /RESET low to put the chip into reset */
  553. ret = gpio_request_one(arizona->pdata.reset,
  554. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  555. "arizona /RESET");
  556. if (ret != 0) {
  557. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  558. goto err_early;
  559. }
  560. }
  561. ret = regulator_bulk_enable(arizona->num_core_supplies,
  562. arizona->core_supplies);
  563. if (ret != 0) {
  564. dev_err(dev, "Failed to enable core supplies: %d\n",
  565. ret);
  566. goto err_early;
  567. }
  568. ret = regulator_enable(arizona->dcvdd);
  569. if (ret != 0) {
  570. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  571. goto err_enable;
  572. }
  573. if (arizona->pdata.reset) {
  574. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  575. msleep(1);
  576. }
  577. regcache_cache_only(arizona->regmap, false);
  578. /* Verify that this is a chip we know about */
  579. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  580. if (ret != 0) {
  581. dev_err(dev, "Failed to read ID register: %d\n", ret);
  582. goto err_reset;
  583. }
  584. switch (reg) {
  585. case 0x5102:
  586. case 0x5110:
  587. case 0x8997:
  588. break;
  589. default:
  590. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  591. goto err_reset;
  592. }
  593. /* If we have a /RESET GPIO we'll already be reset */
  594. if (!arizona->pdata.reset) {
  595. regcache_mark_dirty(arizona->regmap);
  596. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  597. if (ret != 0) {
  598. dev_err(dev, "Failed to reset device: %d\n", ret);
  599. goto err_reset;
  600. }
  601. msleep(1);
  602. ret = regcache_sync(arizona->regmap);
  603. if (ret != 0) {
  604. dev_err(dev, "Failed to sync device: %d\n", ret);
  605. goto err_reset;
  606. }
  607. }
  608. /* Ensure device startup is complete */
  609. switch (arizona->type) {
  610. case WM5102:
  611. ret = regmap_read(arizona->regmap, 0x19, &val);
  612. if (ret != 0)
  613. dev_err(dev,
  614. "Failed to check write sequencer state: %d\n",
  615. ret);
  616. else if (val & 0x01)
  617. break;
  618. /* Fall through */
  619. default:
  620. ret = arizona_wait_for_boot(arizona);
  621. if (ret != 0) {
  622. dev_err(arizona->dev,
  623. "Device failed initial boot: %d\n", ret);
  624. goto err_reset;
  625. }
  626. break;
  627. }
  628. /* Read the device ID information & do device specific stuff */
  629. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  630. if (ret != 0) {
  631. dev_err(dev, "Failed to read ID register: %d\n", ret);
  632. goto err_reset;
  633. }
  634. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  635. &arizona->rev);
  636. if (ret != 0) {
  637. dev_err(dev, "Failed to read revision register: %d\n", ret);
  638. goto err_reset;
  639. }
  640. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  641. switch (reg) {
  642. #ifdef CONFIG_MFD_WM5102
  643. case 0x5102:
  644. type_name = "WM5102";
  645. if (arizona->type != WM5102) {
  646. dev_err(arizona->dev, "WM5102 registered as %d\n",
  647. arizona->type);
  648. arizona->type = WM5102;
  649. }
  650. apply_patch = wm5102_patch;
  651. arizona->rev &= 0x7;
  652. break;
  653. #endif
  654. #ifdef CONFIG_MFD_WM5110
  655. case 0x5110:
  656. type_name = "WM5110";
  657. if (arizona->type != WM5110) {
  658. dev_err(arizona->dev, "WM5110 registered as %d\n",
  659. arizona->type);
  660. arizona->type = WM5110;
  661. }
  662. apply_patch = wm5110_patch;
  663. break;
  664. #endif
  665. #ifdef CONFIG_MFD_WM8997
  666. case 0x8997:
  667. type_name = "WM8997";
  668. if (arizona->type != WM8997) {
  669. dev_err(arizona->dev, "WM8997 registered as %d\n",
  670. arizona->type);
  671. arizona->type = WM8997;
  672. }
  673. apply_patch = wm8997_patch;
  674. break;
  675. #endif
  676. default:
  677. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  678. goto err_reset;
  679. }
  680. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  681. if (apply_patch) {
  682. ret = apply_patch(arizona);
  683. if (ret != 0) {
  684. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  685. ret);
  686. goto err_reset;
  687. }
  688. switch (arizona->type) {
  689. case WM5102:
  690. ret = arizona_apply_hardware_patch(arizona);
  691. if (ret != 0) {
  692. dev_err(arizona->dev,
  693. "Failed to apply hardware patch: %d\n",
  694. ret);
  695. goto err_reset;
  696. }
  697. break;
  698. default:
  699. break;
  700. }
  701. }
  702. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  703. if (!arizona->pdata.gpio_defaults[i])
  704. continue;
  705. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  706. arizona->pdata.gpio_defaults[i]);
  707. }
  708. /*
  709. * LDO1 can only be used to supply DCVDD so if it has no
  710. * consumers then DCVDD is supplied externally.
  711. */
  712. if (arizona->pdata.ldo1 &&
  713. arizona->pdata.ldo1->num_consumer_supplies == 0)
  714. arizona->external_dcvdd = true;
  715. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  716. pm_runtime_use_autosuspend(arizona->dev);
  717. pm_runtime_enable(arizona->dev);
  718. /* Chip default */
  719. if (!arizona->pdata.clk32k_src)
  720. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  721. switch (arizona->pdata.clk32k_src) {
  722. case ARIZONA_32KZ_MCLK1:
  723. case ARIZONA_32KZ_MCLK2:
  724. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  725. ARIZONA_CLK_32K_SRC_MASK,
  726. arizona->pdata.clk32k_src - 1);
  727. arizona_clk32k_enable(arizona);
  728. break;
  729. case ARIZONA_32KZ_NONE:
  730. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  731. ARIZONA_CLK_32K_SRC_MASK, 2);
  732. break;
  733. default:
  734. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  735. arizona->pdata.clk32k_src);
  736. ret = -EINVAL;
  737. goto err_reset;
  738. }
  739. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  740. if (!arizona->pdata.micbias[i].mV &&
  741. !arizona->pdata.micbias[i].bypass)
  742. continue;
  743. /* Apply default for bypass mode */
  744. if (!arizona->pdata.micbias[i].mV)
  745. arizona->pdata.micbias[i].mV = 2800;
  746. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  747. val <<= ARIZONA_MICB1_LVL_SHIFT;
  748. if (arizona->pdata.micbias[i].ext_cap)
  749. val |= ARIZONA_MICB1_EXT_CAP;
  750. if (arizona->pdata.micbias[i].discharge)
  751. val |= ARIZONA_MICB1_DISCH;
  752. if (arizona->pdata.micbias[i].soft_start)
  753. val |= ARIZONA_MICB1_RATE;
  754. if (arizona->pdata.micbias[i].bypass)
  755. val |= ARIZONA_MICB1_BYPASS;
  756. regmap_update_bits(arizona->regmap,
  757. ARIZONA_MIC_BIAS_CTRL_1 + i,
  758. ARIZONA_MICB1_LVL_MASK |
  759. ARIZONA_MICB1_DISCH |
  760. ARIZONA_MICB1_BYPASS |
  761. ARIZONA_MICB1_RATE, val);
  762. }
  763. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  764. /* Default for both is 0 so noop with defaults */
  765. val = arizona->pdata.dmic_ref[i]
  766. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  767. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  768. regmap_update_bits(arizona->regmap,
  769. ARIZONA_IN1L_CONTROL + (i * 8),
  770. ARIZONA_IN1_DMIC_SUP_MASK |
  771. ARIZONA_IN1_MODE_MASK, val);
  772. }
  773. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  774. /* Default is 0 so noop with defaults */
  775. if (arizona->pdata.out_mono[i])
  776. val = ARIZONA_OUT1_MONO;
  777. else
  778. val = 0;
  779. regmap_update_bits(arizona->regmap,
  780. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  781. ARIZONA_OUT1_MONO, val);
  782. }
  783. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  784. if (arizona->pdata.spk_mute[i])
  785. regmap_update_bits(arizona->regmap,
  786. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  787. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  788. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  789. arizona->pdata.spk_mute[i]);
  790. if (arizona->pdata.spk_fmt[i])
  791. regmap_update_bits(arizona->regmap,
  792. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  793. ARIZONA_SPK1_FMT_MASK,
  794. arizona->pdata.spk_fmt[i]);
  795. }
  796. /* Set up for interrupts */
  797. ret = arizona_irq_init(arizona);
  798. if (ret != 0)
  799. goto err_reset;
  800. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  801. arizona_clkgen_err, arizona);
  802. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  803. arizona_overclocked, arizona);
  804. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  805. arizona_underclocked, arizona);
  806. switch (arizona->type) {
  807. case WM5102:
  808. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  809. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  810. break;
  811. case WM5110:
  812. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  813. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  814. break;
  815. case WM8997:
  816. ret = mfd_add_devices(arizona->dev, -1, wm8997_devs,
  817. ARRAY_SIZE(wm8997_devs), NULL, 0, NULL);
  818. break;
  819. }
  820. if (ret != 0) {
  821. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  822. goto err_irq;
  823. }
  824. #ifdef CONFIG_PM_RUNTIME
  825. regulator_disable(arizona->dcvdd);
  826. #endif
  827. return 0;
  828. err_irq:
  829. arizona_irq_exit(arizona);
  830. err_reset:
  831. if (arizona->pdata.reset) {
  832. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  833. gpio_free(arizona->pdata.reset);
  834. }
  835. regulator_disable(arizona->dcvdd);
  836. err_enable:
  837. regulator_bulk_disable(arizona->num_core_supplies,
  838. arizona->core_supplies);
  839. err_early:
  840. mfd_remove_devices(dev);
  841. return ret;
  842. }
  843. EXPORT_SYMBOL_GPL(arizona_dev_init);
  844. int arizona_dev_exit(struct arizona *arizona)
  845. {
  846. mfd_remove_devices(arizona->dev);
  847. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  848. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  849. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  850. pm_runtime_disable(arizona->dev);
  851. arizona_irq_exit(arizona);
  852. if (arizona->pdata.reset)
  853. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  854. regulator_disable(arizona->dcvdd);
  855. regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
  856. arizona->core_supplies);
  857. return 0;
  858. }
  859. EXPORT_SYMBOL_GPL(arizona_dev_exit);