qib_user_sdma.c 33 KB

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  1. /*
  2. * Copyright (c) 2007, 2008, 2009 QLogic Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/mm.h>
  33. #include <linux/types.h>
  34. #include <linux/device.h>
  35. #include <linux/dmapool.h>
  36. #include <linux/slab.h>
  37. #include <linux/list.h>
  38. #include <linux/highmem.h>
  39. #include <linux/io.h>
  40. #include <linux/uio.h>
  41. #include <linux/rbtree.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/delay.h>
  44. #include "qib.h"
  45. #include "qib_user_sdma.h"
  46. /* minimum size of header */
  47. #define QIB_USER_SDMA_MIN_HEADER_LENGTH 64
  48. /* expected size of headers (for dma_pool) */
  49. #define QIB_USER_SDMA_EXP_HEADER_LENGTH 64
  50. /* attempt to drain the queue for 5secs */
  51. #define QIB_USER_SDMA_DRAIN_TIMEOUT 500
  52. struct qib_user_sdma_pkt {
  53. struct list_head list; /* list element */
  54. u8 tiddma; /* if this is NEW tid-sdma */
  55. u8 largepkt; /* this is large pkt from kmalloc */
  56. u16 frag_size; /* frag size used by PSM */
  57. u16 index; /* last header index or push index */
  58. u16 naddr; /* dimension of addr (1..3) ... */
  59. u16 addrlimit; /* addr array size */
  60. u16 tidsmidx; /* current tidsm index */
  61. u16 tidsmcount; /* tidsm array item count */
  62. u16 payload_size; /* payload size so far for header */
  63. u32 bytes_togo; /* bytes for processing */
  64. u32 counter; /* sdma pkts queued counter for this entry */
  65. struct qib_tid_session_member *tidsm; /* tid session member array */
  66. struct qib_user_sdma_queue *pq; /* which pq this pkt belongs to */
  67. u64 added; /* global descq number of entries */
  68. struct {
  69. u16 offset; /* offset for kvaddr, addr */
  70. u16 length; /* length in page */
  71. u16 first_desc; /* first desc */
  72. u16 last_desc; /* last desc */
  73. u16 put_page; /* should we put_page? */
  74. u16 dma_mapped; /* is page dma_mapped? */
  75. u16 dma_length; /* for dma_unmap_page() */
  76. u16 padding;
  77. struct page *page; /* may be NULL (coherent mem) */
  78. void *kvaddr; /* FIXME: only for pio hack */
  79. dma_addr_t addr;
  80. } addr[4]; /* max pages, any more and we coalesce */
  81. };
  82. struct qib_user_sdma_queue {
  83. /*
  84. * pkts sent to dma engine are queued on this
  85. * list head. the type of the elements of this
  86. * list are struct qib_user_sdma_pkt...
  87. */
  88. struct list_head sent;
  89. /*
  90. * Because above list will be accessed by both process and
  91. * signal handler, we need a spinlock for it.
  92. */
  93. spinlock_t sent_lock ____cacheline_aligned_in_smp;
  94. /* headers with expected length are allocated from here... */
  95. char header_cache_name[64];
  96. struct dma_pool *header_cache;
  97. /* packets are allocated from the slab cache... */
  98. char pkt_slab_name[64];
  99. struct kmem_cache *pkt_slab;
  100. /* as packets go on the queued queue, they are counted... */
  101. u32 counter;
  102. u32 sent_counter;
  103. /* pending packets, not sending yet */
  104. u32 num_pending;
  105. /* sending packets, not complete yet */
  106. u32 num_sending;
  107. /* global descq number of entry of last sending packet */
  108. u64 added;
  109. /* dma page table */
  110. struct rb_root dma_pages_root;
  111. /* protect everything above... */
  112. struct mutex lock;
  113. };
  114. struct qib_user_sdma_queue *
  115. qib_user_sdma_queue_create(struct device *dev, int unit, int ctxt, int sctxt)
  116. {
  117. struct qib_user_sdma_queue *pq =
  118. kmalloc(sizeof(struct qib_user_sdma_queue), GFP_KERNEL);
  119. if (!pq)
  120. goto done;
  121. pq->counter = 0;
  122. pq->sent_counter = 0;
  123. pq->num_pending = 0;
  124. pq->num_sending = 0;
  125. pq->added = 0;
  126. INIT_LIST_HEAD(&pq->sent);
  127. spin_lock_init(&pq->sent_lock);
  128. mutex_init(&pq->lock);
  129. snprintf(pq->pkt_slab_name, sizeof(pq->pkt_slab_name),
  130. "qib-user-sdma-pkts-%u-%02u.%02u", unit, ctxt, sctxt);
  131. pq->pkt_slab = kmem_cache_create(pq->pkt_slab_name,
  132. sizeof(struct qib_user_sdma_pkt),
  133. 0, 0, NULL);
  134. if (!pq->pkt_slab)
  135. goto err_kfree;
  136. snprintf(pq->header_cache_name, sizeof(pq->header_cache_name),
  137. "qib-user-sdma-headers-%u-%02u.%02u", unit, ctxt, sctxt);
  138. pq->header_cache = dma_pool_create(pq->header_cache_name,
  139. dev,
  140. QIB_USER_SDMA_EXP_HEADER_LENGTH,
  141. 4, 0);
  142. if (!pq->header_cache)
  143. goto err_slab;
  144. pq->dma_pages_root = RB_ROOT;
  145. goto done;
  146. err_slab:
  147. kmem_cache_destroy(pq->pkt_slab);
  148. err_kfree:
  149. kfree(pq);
  150. pq = NULL;
  151. done:
  152. return pq;
  153. }
  154. static void qib_user_sdma_init_frag(struct qib_user_sdma_pkt *pkt,
  155. int i, u16 offset, u16 len,
  156. u16 first_desc, u16 last_desc,
  157. u16 put_page, u16 dma_mapped,
  158. struct page *page, void *kvaddr,
  159. dma_addr_t dma_addr, u16 dma_length)
  160. {
  161. pkt->addr[i].offset = offset;
  162. pkt->addr[i].length = len;
  163. pkt->addr[i].first_desc = first_desc;
  164. pkt->addr[i].last_desc = last_desc;
  165. pkt->addr[i].put_page = put_page;
  166. pkt->addr[i].dma_mapped = dma_mapped;
  167. pkt->addr[i].page = page;
  168. pkt->addr[i].kvaddr = kvaddr;
  169. pkt->addr[i].addr = dma_addr;
  170. pkt->addr[i].dma_length = dma_length;
  171. }
  172. static void *qib_user_sdma_alloc_header(struct qib_user_sdma_queue *pq,
  173. size_t len, dma_addr_t *dma_addr)
  174. {
  175. void *hdr;
  176. if (len == QIB_USER_SDMA_EXP_HEADER_LENGTH)
  177. hdr = dma_pool_alloc(pq->header_cache, GFP_KERNEL,
  178. dma_addr);
  179. else
  180. hdr = NULL;
  181. if (!hdr) {
  182. hdr = kmalloc(len, GFP_KERNEL);
  183. if (!hdr)
  184. return NULL;
  185. *dma_addr = 0;
  186. }
  187. return hdr;
  188. }
  189. static int qib_user_sdma_page_to_frags(const struct qib_devdata *dd,
  190. struct qib_user_sdma_queue *pq,
  191. struct qib_user_sdma_pkt *pkt,
  192. struct page *page, u16 put,
  193. u16 offset, u16 len, void *kvaddr)
  194. {
  195. __le16 *pbc16;
  196. void *pbcvaddr;
  197. struct qib_message_header *hdr;
  198. u16 newlen, pbclen, lastdesc, dma_mapped;
  199. u32 vcto;
  200. union qib_seqnum seqnum;
  201. dma_addr_t pbcdaddr;
  202. dma_addr_t dma_addr =
  203. dma_map_page(&dd->pcidev->dev,
  204. page, offset, len, DMA_TO_DEVICE);
  205. int ret = 0;
  206. if (dma_mapping_error(&dd->pcidev->dev, dma_addr)) {
  207. /*
  208. * dma mapping error, pkt has not managed
  209. * this page yet, return the page here so
  210. * the caller can ignore this page.
  211. */
  212. if (put) {
  213. put_page(page);
  214. } else {
  215. /* coalesce case */
  216. kunmap(page);
  217. __free_page(page);
  218. }
  219. ret = -ENOMEM;
  220. goto done;
  221. }
  222. offset = 0;
  223. dma_mapped = 1;
  224. next_fragment:
  225. /*
  226. * In tid-sdma, the transfer length is restricted by
  227. * receiver side current tid page length.
  228. */
  229. if (pkt->tiddma && len > pkt->tidsm[pkt->tidsmidx].length)
  230. newlen = pkt->tidsm[pkt->tidsmidx].length;
  231. else
  232. newlen = len;
  233. /*
  234. * Then the transfer length is restricted by MTU.
  235. * the last descriptor flag is determined by:
  236. * 1. the current packet is at frag size length.
  237. * 2. the current tid page is done if tid-sdma.
  238. * 3. there is no more byte togo if sdma.
  239. */
  240. lastdesc = 0;
  241. if ((pkt->payload_size + newlen) >= pkt->frag_size) {
  242. newlen = pkt->frag_size - pkt->payload_size;
  243. lastdesc = 1;
  244. } else if (pkt->tiddma) {
  245. if (newlen == pkt->tidsm[pkt->tidsmidx].length)
  246. lastdesc = 1;
  247. } else {
  248. if (newlen == pkt->bytes_togo)
  249. lastdesc = 1;
  250. }
  251. /* fill the next fragment in this page */
  252. qib_user_sdma_init_frag(pkt, pkt->naddr, /* index */
  253. offset, newlen, /* offset, len */
  254. 0, lastdesc, /* first last desc */
  255. put, dma_mapped, /* put page, dma mapped */
  256. page, kvaddr, /* struct page, virt addr */
  257. dma_addr, len); /* dma addr, dma length */
  258. pkt->bytes_togo -= newlen;
  259. pkt->payload_size += newlen;
  260. pkt->naddr++;
  261. if (pkt->naddr == pkt->addrlimit) {
  262. ret = -EFAULT;
  263. goto done;
  264. }
  265. /* If there is no more byte togo. (lastdesc==1) */
  266. if (pkt->bytes_togo == 0) {
  267. /* The packet is done, header is not dma mapped yet.
  268. * it should be from kmalloc */
  269. if (!pkt->addr[pkt->index].addr) {
  270. pkt->addr[pkt->index].addr =
  271. dma_map_single(&dd->pcidev->dev,
  272. pkt->addr[pkt->index].kvaddr,
  273. pkt->addr[pkt->index].dma_length,
  274. DMA_TO_DEVICE);
  275. if (dma_mapping_error(&dd->pcidev->dev,
  276. pkt->addr[pkt->index].addr)) {
  277. ret = -ENOMEM;
  278. goto done;
  279. }
  280. pkt->addr[pkt->index].dma_mapped = 1;
  281. }
  282. goto done;
  283. }
  284. /* If tid-sdma, advance tid info. */
  285. if (pkt->tiddma) {
  286. pkt->tidsm[pkt->tidsmidx].length -= newlen;
  287. if (pkt->tidsm[pkt->tidsmidx].length) {
  288. pkt->tidsm[pkt->tidsmidx].offset += newlen;
  289. } else {
  290. pkt->tidsmidx++;
  291. if (pkt->tidsmidx == pkt->tidsmcount) {
  292. ret = -EFAULT;
  293. goto done;
  294. }
  295. }
  296. }
  297. /*
  298. * If this is NOT the last descriptor. (newlen==len)
  299. * the current packet is not done yet, but the current
  300. * send side page is done.
  301. */
  302. if (lastdesc == 0)
  303. goto done;
  304. /*
  305. * If running this driver under PSM with message size
  306. * fitting into one transfer unit, it is not possible
  307. * to pass this line. otherwise, it is a buggggg.
  308. */
  309. /*
  310. * Since the current packet is done, and there are more
  311. * bytes togo, we need to create a new sdma header, copying
  312. * from previous sdma header and modify both.
  313. */
  314. pbclen = pkt->addr[pkt->index].length;
  315. pbcvaddr = qib_user_sdma_alloc_header(pq, pbclen, &pbcdaddr);
  316. if (!pbcvaddr) {
  317. ret = -ENOMEM;
  318. goto done;
  319. }
  320. /* Copy the previous sdma header to new sdma header */
  321. pbc16 = (__le16 *)pkt->addr[pkt->index].kvaddr;
  322. memcpy(pbcvaddr, pbc16, pbclen);
  323. /* Modify the previous sdma header */
  324. hdr = (struct qib_message_header *)&pbc16[4];
  325. /* New pbc length */
  326. pbc16[0] = cpu_to_le16(le16_to_cpu(pbc16[0])-(pkt->bytes_togo>>2));
  327. /* New packet length */
  328. hdr->lrh[2] = cpu_to_be16(le16_to_cpu(pbc16[0]));
  329. if (pkt->tiddma) {
  330. /* turn on the header suppression */
  331. hdr->iph.pkt_flags =
  332. cpu_to_le16(le16_to_cpu(hdr->iph.pkt_flags)|0x2);
  333. /* turn off ACK_REQ: 0x04 and EXPECTED_DONE: 0x20 */
  334. hdr->flags &= ~(0x04|0x20);
  335. } else {
  336. /* turn off extra bytes: 20-21 bits */
  337. hdr->bth[0] = cpu_to_be32(be32_to_cpu(hdr->bth[0])&0xFFCFFFFF);
  338. /* turn off ACK_REQ: 0x04 */
  339. hdr->flags &= ~(0x04);
  340. }
  341. /* New kdeth checksum */
  342. vcto = le32_to_cpu(hdr->iph.ver_ctxt_tid_offset);
  343. hdr->iph.chksum = cpu_to_le16(QIB_LRH_BTH +
  344. be16_to_cpu(hdr->lrh[2]) -
  345. ((vcto>>16)&0xFFFF) - (vcto&0xFFFF) -
  346. le16_to_cpu(hdr->iph.pkt_flags));
  347. /* The packet is done, header is not dma mapped yet.
  348. * it should be from kmalloc */
  349. if (!pkt->addr[pkt->index].addr) {
  350. pkt->addr[pkt->index].addr =
  351. dma_map_single(&dd->pcidev->dev,
  352. pkt->addr[pkt->index].kvaddr,
  353. pkt->addr[pkt->index].dma_length,
  354. DMA_TO_DEVICE);
  355. if (dma_mapping_error(&dd->pcidev->dev,
  356. pkt->addr[pkt->index].addr)) {
  357. ret = -ENOMEM;
  358. goto done;
  359. }
  360. pkt->addr[pkt->index].dma_mapped = 1;
  361. }
  362. /* Modify the new sdma header */
  363. pbc16 = (__le16 *)pbcvaddr;
  364. hdr = (struct qib_message_header *)&pbc16[4];
  365. /* New pbc length */
  366. pbc16[0] = cpu_to_le16(le16_to_cpu(pbc16[0])-(pkt->payload_size>>2));
  367. /* New packet length */
  368. hdr->lrh[2] = cpu_to_be16(le16_to_cpu(pbc16[0]));
  369. if (pkt->tiddma) {
  370. /* Set new tid and offset for new sdma header */
  371. hdr->iph.ver_ctxt_tid_offset = cpu_to_le32(
  372. (le32_to_cpu(hdr->iph.ver_ctxt_tid_offset)&0xFF000000) +
  373. (pkt->tidsm[pkt->tidsmidx].tid<<QLOGIC_IB_I_TID_SHIFT) +
  374. (pkt->tidsm[pkt->tidsmidx].offset>>2));
  375. } else {
  376. /* Middle protocol new packet offset */
  377. hdr->uwords[2] += pkt->payload_size;
  378. }
  379. /* New kdeth checksum */
  380. vcto = le32_to_cpu(hdr->iph.ver_ctxt_tid_offset);
  381. hdr->iph.chksum = cpu_to_le16(QIB_LRH_BTH +
  382. be16_to_cpu(hdr->lrh[2]) -
  383. ((vcto>>16)&0xFFFF) - (vcto&0xFFFF) -
  384. le16_to_cpu(hdr->iph.pkt_flags));
  385. /* Next sequence number in new sdma header */
  386. seqnum.val = be32_to_cpu(hdr->bth[2]);
  387. if (pkt->tiddma)
  388. seqnum.seq++;
  389. else
  390. seqnum.pkt++;
  391. hdr->bth[2] = cpu_to_be32(seqnum.val);
  392. /* Init new sdma header. */
  393. qib_user_sdma_init_frag(pkt, pkt->naddr, /* index */
  394. 0, pbclen, /* offset, len */
  395. 1, 0, /* first last desc */
  396. 0, 0, /* put page, dma mapped */
  397. NULL, pbcvaddr, /* struct page, virt addr */
  398. pbcdaddr, pbclen); /* dma addr, dma length */
  399. pkt->index = pkt->naddr;
  400. pkt->payload_size = 0;
  401. pkt->naddr++;
  402. if (pkt->naddr == pkt->addrlimit) {
  403. ret = -EFAULT;
  404. goto done;
  405. }
  406. /* Prepare for next fragment in this page */
  407. if (newlen != len) {
  408. if (dma_mapped) {
  409. put = 0;
  410. dma_mapped = 0;
  411. page = NULL;
  412. kvaddr = NULL;
  413. }
  414. len -= newlen;
  415. offset += newlen;
  416. goto next_fragment;
  417. }
  418. done:
  419. return ret;
  420. }
  421. /* we've too many pages in the iovec, coalesce to a single page */
  422. static int qib_user_sdma_coalesce(const struct qib_devdata *dd,
  423. struct qib_user_sdma_queue *pq,
  424. struct qib_user_sdma_pkt *pkt,
  425. const struct iovec *iov,
  426. unsigned long niov)
  427. {
  428. int ret = 0;
  429. struct page *page = alloc_page(GFP_KERNEL);
  430. void *mpage_save;
  431. char *mpage;
  432. int i;
  433. int len = 0;
  434. if (!page) {
  435. ret = -ENOMEM;
  436. goto done;
  437. }
  438. mpage = kmap(page);
  439. mpage_save = mpage;
  440. for (i = 0; i < niov; i++) {
  441. int cfur;
  442. cfur = copy_from_user(mpage,
  443. iov[i].iov_base, iov[i].iov_len);
  444. if (cfur) {
  445. ret = -EFAULT;
  446. goto free_unmap;
  447. }
  448. mpage += iov[i].iov_len;
  449. len += iov[i].iov_len;
  450. }
  451. ret = qib_user_sdma_page_to_frags(dd, pq, pkt,
  452. page, 0, 0, len, mpage_save);
  453. goto done;
  454. free_unmap:
  455. kunmap(page);
  456. __free_page(page);
  457. done:
  458. return ret;
  459. }
  460. /*
  461. * How many pages in this iovec element?
  462. */
  463. static int qib_user_sdma_num_pages(const struct iovec *iov)
  464. {
  465. const unsigned long addr = (unsigned long) iov->iov_base;
  466. const unsigned long len = iov->iov_len;
  467. const unsigned long spage = addr & PAGE_MASK;
  468. const unsigned long epage = (addr + len - 1) & PAGE_MASK;
  469. return 1 + ((epage - spage) >> PAGE_SHIFT);
  470. }
  471. static void qib_user_sdma_free_pkt_frag(struct device *dev,
  472. struct qib_user_sdma_queue *pq,
  473. struct qib_user_sdma_pkt *pkt,
  474. int frag)
  475. {
  476. const int i = frag;
  477. if (pkt->addr[i].page) {
  478. /* only user data has page */
  479. if (pkt->addr[i].dma_mapped)
  480. dma_unmap_page(dev,
  481. pkt->addr[i].addr,
  482. pkt->addr[i].dma_length,
  483. DMA_TO_DEVICE);
  484. if (pkt->addr[i].kvaddr)
  485. kunmap(pkt->addr[i].page);
  486. if (pkt->addr[i].put_page)
  487. put_page(pkt->addr[i].page);
  488. else
  489. __free_page(pkt->addr[i].page);
  490. } else if (pkt->addr[i].kvaddr) {
  491. /* for headers */
  492. if (pkt->addr[i].dma_mapped) {
  493. /* from kmalloc & dma mapped */
  494. dma_unmap_single(dev,
  495. pkt->addr[i].addr,
  496. pkt->addr[i].dma_length,
  497. DMA_TO_DEVICE);
  498. kfree(pkt->addr[i].kvaddr);
  499. } else if (pkt->addr[i].addr) {
  500. /* free coherent mem from cache... */
  501. dma_pool_free(pq->header_cache,
  502. pkt->addr[i].kvaddr, pkt->addr[i].addr);
  503. } else {
  504. /* from kmalloc but not dma mapped */
  505. kfree(pkt->addr[i].kvaddr);
  506. }
  507. }
  508. }
  509. /* return number of pages pinned... */
  510. static int qib_user_sdma_pin_pages(const struct qib_devdata *dd,
  511. struct qib_user_sdma_queue *pq,
  512. struct qib_user_sdma_pkt *pkt,
  513. unsigned long addr, int tlen, int npages)
  514. {
  515. struct page *pages[8];
  516. int i, j;
  517. int ret = 0;
  518. while (npages) {
  519. if (npages > 8)
  520. j = 8;
  521. else
  522. j = npages;
  523. ret = get_user_pages(current, current->mm, addr,
  524. j, 0, 1, pages, NULL);
  525. if (ret != j) {
  526. i = 0;
  527. j = ret;
  528. ret = -ENOMEM;
  529. goto free_pages;
  530. }
  531. for (i = 0; i < j; i++) {
  532. /* map the pages... */
  533. unsigned long fofs = addr & ~PAGE_MASK;
  534. int flen = ((fofs + tlen) > PAGE_SIZE) ?
  535. (PAGE_SIZE - fofs) : tlen;
  536. ret = qib_user_sdma_page_to_frags(dd, pq, pkt,
  537. pages[i], 1, fofs, flen, NULL);
  538. if (ret < 0) {
  539. /* current page has beed taken
  540. * care of inside above call.
  541. */
  542. i++;
  543. goto free_pages;
  544. }
  545. addr += flen;
  546. tlen -= flen;
  547. }
  548. npages -= j;
  549. }
  550. goto done;
  551. /* if error, return all pages not managed by pkt */
  552. free_pages:
  553. while (i < j)
  554. put_page(pages[i++]);
  555. done:
  556. return ret;
  557. }
  558. static int qib_user_sdma_pin_pkt(const struct qib_devdata *dd,
  559. struct qib_user_sdma_queue *pq,
  560. struct qib_user_sdma_pkt *pkt,
  561. const struct iovec *iov,
  562. unsigned long niov)
  563. {
  564. int ret = 0;
  565. unsigned long idx;
  566. for (idx = 0; idx < niov; idx++) {
  567. const int npages = qib_user_sdma_num_pages(iov + idx);
  568. const unsigned long addr = (unsigned long) iov[idx].iov_base;
  569. ret = qib_user_sdma_pin_pages(dd, pq, pkt, addr,
  570. iov[idx].iov_len, npages);
  571. if (ret < 0)
  572. goto free_pkt;
  573. }
  574. goto done;
  575. free_pkt:
  576. /* we need to ignore the first entry here */
  577. for (idx = 1; idx < pkt->naddr; idx++)
  578. qib_user_sdma_free_pkt_frag(&dd->pcidev->dev, pq, pkt, idx);
  579. /* need to dma unmap the first entry, this is to restore to
  580. * the original state so that caller can free the memory in
  581. * error condition. Caller does not know if dma mapped or not*/
  582. if (pkt->addr[0].dma_mapped) {
  583. dma_unmap_single(&dd->pcidev->dev,
  584. pkt->addr[0].addr,
  585. pkt->addr[0].dma_length,
  586. DMA_TO_DEVICE);
  587. pkt->addr[0].addr = 0;
  588. pkt->addr[0].dma_mapped = 0;
  589. }
  590. done:
  591. return ret;
  592. }
  593. static int qib_user_sdma_init_payload(const struct qib_devdata *dd,
  594. struct qib_user_sdma_queue *pq,
  595. struct qib_user_sdma_pkt *pkt,
  596. const struct iovec *iov,
  597. unsigned long niov, int npages)
  598. {
  599. int ret = 0;
  600. if (pkt->frag_size == pkt->bytes_togo &&
  601. npages >= ARRAY_SIZE(pkt->addr))
  602. ret = qib_user_sdma_coalesce(dd, pq, pkt, iov, niov);
  603. else
  604. ret = qib_user_sdma_pin_pkt(dd, pq, pkt, iov, niov);
  605. return ret;
  606. }
  607. /* free a packet list -- return counter value of last packet */
  608. static void qib_user_sdma_free_pkt_list(struct device *dev,
  609. struct qib_user_sdma_queue *pq,
  610. struct list_head *list)
  611. {
  612. struct qib_user_sdma_pkt *pkt, *pkt_next;
  613. list_for_each_entry_safe(pkt, pkt_next, list, list) {
  614. int i;
  615. for (i = 0; i < pkt->naddr; i++)
  616. qib_user_sdma_free_pkt_frag(dev, pq, pkt, i);
  617. if (pkt->largepkt)
  618. kfree(pkt);
  619. else
  620. kmem_cache_free(pq->pkt_slab, pkt);
  621. }
  622. INIT_LIST_HEAD(list);
  623. }
  624. /*
  625. * copy headers, coalesce etc -- pq->lock must be held
  626. *
  627. * we queue all the packets to list, returning the
  628. * number of bytes total. list must be empty initially,
  629. * as, if there is an error we clean it...
  630. */
  631. static int qib_user_sdma_queue_pkts(const struct qib_devdata *dd,
  632. struct qib_pportdata *ppd,
  633. struct qib_user_sdma_queue *pq,
  634. const struct iovec *iov,
  635. unsigned long niov,
  636. struct list_head *list,
  637. int *maxpkts, int *ndesc)
  638. {
  639. unsigned long idx = 0;
  640. int ret = 0;
  641. int npkts = 0;
  642. __le32 *pbc;
  643. dma_addr_t dma_addr;
  644. struct qib_user_sdma_pkt *pkt = NULL;
  645. size_t len;
  646. size_t nw;
  647. u32 counter = pq->counter;
  648. u16 frag_size;
  649. while (idx < niov && npkts < *maxpkts) {
  650. const unsigned long addr = (unsigned long) iov[idx].iov_base;
  651. const unsigned long idx_save = idx;
  652. unsigned pktnw;
  653. unsigned pktnwc;
  654. int nfrags = 0;
  655. int npages = 0;
  656. int bytes_togo = 0;
  657. int tiddma = 0;
  658. int cfur;
  659. len = iov[idx].iov_len;
  660. nw = len >> 2;
  661. if (len < QIB_USER_SDMA_MIN_HEADER_LENGTH ||
  662. len > PAGE_SIZE || len & 3 || addr & 3) {
  663. ret = -EINVAL;
  664. goto free_list;
  665. }
  666. pbc = qib_user_sdma_alloc_header(pq, len, &dma_addr);
  667. if (!pbc) {
  668. ret = -ENOMEM;
  669. goto free_list;
  670. }
  671. cfur = copy_from_user(pbc, iov[idx].iov_base, len);
  672. if (cfur) {
  673. ret = -EFAULT;
  674. goto free_pbc;
  675. }
  676. /*
  677. * This assignment is a bit strange. it's because the
  678. * the pbc counts the number of 32 bit words in the full
  679. * packet _except_ the first word of the pbc itself...
  680. */
  681. pktnwc = nw - 1;
  682. /*
  683. * pktnw computation yields the number of 32 bit words
  684. * that the caller has indicated in the PBC. note that
  685. * this is one less than the total number of words that
  686. * goes to the send DMA engine as the first 32 bit word
  687. * of the PBC itself is not counted. Armed with this count,
  688. * we can verify that the packet is consistent with the
  689. * iovec lengths.
  690. */
  691. pktnw = le32_to_cpu(*pbc) & 0xFFFF;
  692. if (pktnw < pktnwc) {
  693. ret = -EINVAL;
  694. goto free_pbc;
  695. }
  696. idx++;
  697. while (pktnwc < pktnw && idx < niov) {
  698. const size_t slen = iov[idx].iov_len;
  699. const unsigned long faddr =
  700. (unsigned long) iov[idx].iov_base;
  701. if (slen & 3 || faddr & 3 || !slen) {
  702. ret = -EINVAL;
  703. goto free_pbc;
  704. }
  705. npages += qib_user_sdma_num_pages(&iov[idx]);
  706. bytes_togo += slen;
  707. pktnwc += slen >> 2;
  708. idx++;
  709. nfrags++;
  710. }
  711. if (pktnwc != pktnw) {
  712. ret = -EINVAL;
  713. goto free_pbc;
  714. }
  715. frag_size = ((le32_to_cpu(*pbc))>>16) & 0xFFFF;
  716. if (((frag_size ? frag_size : bytes_togo) + len) >
  717. ppd->ibmaxlen) {
  718. ret = -EINVAL;
  719. goto free_pbc;
  720. }
  721. if (frag_size) {
  722. int pktsize, tidsmsize, n;
  723. n = npages*((2*PAGE_SIZE/frag_size)+1);
  724. pktsize = sizeof(*pkt) + sizeof(pkt->addr[0])*n;
  725. /*
  726. * Determine if this is tid-sdma or just sdma.
  727. */
  728. tiddma = (((le32_to_cpu(pbc[7])>>
  729. QLOGIC_IB_I_TID_SHIFT)&
  730. QLOGIC_IB_I_TID_MASK) !=
  731. QLOGIC_IB_I_TID_MASK);
  732. if (tiddma)
  733. tidsmsize = iov[idx].iov_len;
  734. else
  735. tidsmsize = 0;
  736. pkt = kmalloc(pktsize+tidsmsize, GFP_KERNEL);
  737. if (!pkt) {
  738. ret = -ENOMEM;
  739. goto free_pbc;
  740. }
  741. pkt->largepkt = 1;
  742. pkt->frag_size = frag_size;
  743. pkt->addrlimit = n + ARRAY_SIZE(pkt->addr);
  744. if (tiddma) {
  745. char *tidsm = (char *)pkt + pktsize;
  746. cfur = copy_from_user(tidsm,
  747. iov[idx].iov_base, tidsmsize);
  748. if (cfur) {
  749. ret = -EFAULT;
  750. goto free_pkt;
  751. }
  752. pkt->tidsm =
  753. (struct qib_tid_session_member *)tidsm;
  754. pkt->tidsmcount = tidsmsize/
  755. sizeof(struct qib_tid_session_member);
  756. pkt->tidsmidx = 0;
  757. idx++;
  758. }
  759. /*
  760. * pbc 'fill1' field is borrowed to pass frag size,
  761. * we need to clear it after picking frag size, the
  762. * hardware requires this field to be zero.
  763. */
  764. *pbc = cpu_to_le32(le32_to_cpu(*pbc) & 0x0000FFFF);
  765. } else {
  766. pkt = kmem_cache_alloc(pq->pkt_slab, GFP_KERNEL);
  767. if (!pkt) {
  768. ret = -ENOMEM;
  769. goto free_pbc;
  770. }
  771. pkt->largepkt = 0;
  772. pkt->frag_size = bytes_togo;
  773. pkt->addrlimit = ARRAY_SIZE(pkt->addr);
  774. }
  775. pkt->bytes_togo = bytes_togo;
  776. pkt->payload_size = 0;
  777. pkt->counter = counter;
  778. pkt->tiddma = tiddma;
  779. /* setup the first header */
  780. qib_user_sdma_init_frag(pkt, 0, /* index */
  781. 0, len, /* offset, len */
  782. 1, 0, /* first last desc */
  783. 0, 0, /* put page, dma mapped */
  784. NULL, pbc, /* struct page, virt addr */
  785. dma_addr, len); /* dma addr, dma length */
  786. pkt->index = 0;
  787. pkt->naddr = 1;
  788. if (nfrags) {
  789. ret = qib_user_sdma_init_payload(dd, pq, pkt,
  790. iov + idx_save + 1,
  791. nfrags, npages);
  792. if (ret < 0)
  793. goto free_pkt;
  794. } else {
  795. /* since there is no payload, mark the
  796. * header as the last desc. */
  797. pkt->addr[0].last_desc = 1;
  798. if (dma_addr == 0) {
  799. /*
  800. * the header is not dma mapped yet.
  801. * it should be from kmalloc.
  802. */
  803. dma_addr = dma_map_single(&dd->pcidev->dev,
  804. pbc, len, DMA_TO_DEVICE);
  805. if (dma_mapping_error(&dd->pcidev->dev,
  806. dma_addr)) {
  807. ret = -ENOMEM;
  808. goto free_pkt;
  809. }
  810. pkt->addr[0].addr = dma_addr;
  811. pkt->addr[0].dma_mapped = 1;
  812. }
  813. }
  814. counter++;
  815. npkts++;
  816. pkt->pq = pq;
  817. pkt->index = 0; /* reset index for push on hw */
  818. *ndesc += pkt->naddr;
  819. list_add_tail(&pkt->list, list);
  820. }
  821. *maxpkts = npkts;
  822. ret = idx;
  823. goto done;
  824. free_pkt:
  825. if (pkt->largepkt)
  826. kfree(pkt);
  827. else
  828. kmem_cache_free(pq->pkt_slab, pkt);
  829. free_pbc:
  830. if (dma_addr)
  831. dma_pool_free(pq->header_cache, pbc, dma_addr);
  832. else
  833. kfree(pbc);
  834. free_list:
  835. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, list);
  836. done:
  837. return ret;
  838. }
  839. static void qib_user_sdma_set_complete_counter(struct qib_user_sdma_queue *pq,
  840. u32 c)
  841. {
  842. pq->sent_counter = c;
  843. }
  844. /* try to clean out queue -- needs pq->lock */
  845. static int qib_user_sdma_queue_clean(struct qib_pportdata *ppd,
  846. struct qib_user_sdma_queue *pq)
  847. {
  848. struct qib_devdata *dd = ppd->dd;
  849. struct list_head free_list;
  850. struct qib_user_sdma_pkt *pkt;
  851. struct qib_user_sdma_pkt *pkt_prev;
  852. unsigned long flags;
  853. int ret = 0;
  854. if (!pq->num_sending)
  855. return 0;
  856. INIT_LIST_HEAD(&free_list);
  857. /*
  858. * We need this spin lock here because interrupt handler
  859. * might modify this list in qib_user_sdma_send_desc(), also
  860. * we can not get interrupted, otherwise it is a deadlock.
  861. */
  862. spin_lock_irqsave(&pq->sent_lock, flags);
  863. list_for_each_entry_safe(pkt, pkt_prev, &pq->sent, list) {
  864. s64 descd = ppd->sdma_descq_removed - pkt->added;
  865. if (descd < 0)
  866. break;
  867. list_move_tail(&pkt->list, &free_list);
  868. /* one more packet cleaned */
  869. ret++;
  870. pq->num_sending--;
  871. }
  872. spin_unlock_irqrestore(&pq->sent_lock, flags);
  873. if (!list_empty(&free_list)) {
  874. u32 counter;
  875. pkt = list_entry(free_list.prev,
  876. struct qib_user_sdma_pkt, list);
  877. counter = pkt->counter;
  878. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &free_list);
  879. qib_user_sdma_set_complete_counter(pq, counter);
  880. }
  881. return ret;
  882. }
  883. void qib_user_sdma_queue_destroy(struct qib_user_sdma_queue *pq)
  884. {
  885. if (!pq)
  886. return;
  887. kmem_cache_destroy(pq->pkt_slab);
  888. dma_pool_destroy(pq->header_cache);
  889. kfree(pq);
  890. }
  891. /* clean descriptor queue, returns > 0 if some elements cleaned */
  892. static int qib_user_sdma_hwqueue_clean(struct qib_pportdata *ppd)
  893. {
  894. int ret;
  895. unsigned long flags;
  896. spin_lock_irqsave(&ppd->sdma_lock, flags);
  897. ret = qib_sdma_make_progress(ppd);
  898. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  899. return ret;
  900. }
  901. /* we're in close, drain packets so that we can cleanup successfully... */
  902. void qib_user_sdma_queue_drain(struct qib_pportdata *ppd,
  903. struct qib_user_sdma_queue *pq)
  904. {
  905. struct qib_devdata *dd = ppd->dd;
  906. unsigned long flags;
  907. int i;
  908. if (!pq)
  909. return;
  910. for (i = 0; i < QIB_USER_SDMA_DRAIN_TIMEOUT; i++) {
  911. mutex_lock(&pq->lock);
  912. if (!pq->num_pending && !pq->num_sending) {
  913. mutex_unlock(&pq->lock);
  914. break;
  915. }
  916. qib_user_sdma_hwqueue_clean(ppd);
  917. qib_user_sdma_queue_clean(ppd, pq);
  918. mutex_unlock(&pq->lock);
  919. msleep(10);
  920. }
  921. if (pq->num_pending || pq->num_sending) {
  922. struct qib_user_sdma_pkt *pkt;
  923. struct qib_user_sdma_pkt *pkt_prev;
  924. struct list_head free_list;
  925. mutex_lock(&pq->lock);
  926. spin_lock_irqsave(&ppd->sdma_lock, flags);
  927. /*
  928. * Since we hold sdma_lock, it is safe without sent_lock.
  929. */
  930. if (pq->num_pending) {
  931. list_for_each_entry_safe(pkt, pkt_prev,
  932. &ppd->sdma_userpending, list) {
  933. if (pkt->pq == pq) {
  934. list_move_tail(&pkt->list, &pq->sent);
  935. pq->num_pending--;
  936. pq->num_sending++;
  937. }
  938. }
  939. }
  940. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  941. qib_dev_err(dd, "user sdma lists not empty: forcing!\n");
  942. INIT_LIST_HEAD(&free_list);
  943. list_splice_init(&pq->sent, &free_list);
  944. pq->num_sending = 0;
  945. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &free_list);
  946. mutex_unlock(&pq->lock);
  947. }
  948. }
  949. static inline __le64 qib_sdma_make_desc0(u8 gen,
  950. u64 addr, u64 dwlen, u64 dwoffset)
  951. {
  952. return cpu_to_le64(/* SDmaPhyAddr[31:0] */
  953. ((addr & 0xfffffffcULL) << 32) |
  954. /* SDmaGeneration[1:0] */
  955. ((gen & 3ULL) << 30) |
  956. /* SDmaDwordCount[10:0] */
  957. ((dwlen & 0x7ffULL) << 16) |
  958. /* SDmaBufOffset[12:2] */
  959. (dwoffset & 0x7ffULL));
  960. }
  961. static inline __le64 qib_sdma_make_first_desc0(__le64 descq)
  962. {
  963. return descq | cpu_to_le64(1ULL << 12);
  964. }
  965. static inline __le64 qib_sdma_make_last_desc0(__le64 descq)
  966. {
  967. /* last */ /* dma head */
  968. return descq | cpu_to_le64(1ULL << 11 | 1ULL << 13);
  969. }
  970. static inline __le64 qib_sdma_make_desc1(u64 addr)
  971. {
  972. /* SDmaPhyAddr[47:32] */
  973. return cpu_to_le64(addr >> 32);
  974. }
  975. static void qib_user_sdma_send_frag(struct qib_pportdata *ppd,
  976. struct qib_user_sdma_pkt *pkt, int idx,
  977. unsigned ofs, u16 tail, u8 gen)
  978. {
  979. const u64 addr = (u64) pkt->addr[idx].addr +
  980. (u64) pkt->addr[idx].offset;
  981. const u64 dwlen = (u64) pkt->addr[idx].length / 4;
  982. __le64 *descqp;
  983. __le64 descq0;
  984. descqp = &ppd->sdma_descq[tail].qw[0];
  985. descq0 = qib_sdma_make_desc0(gen, addr, dwlen, ofs);
  986. if (pkt->addr[idx].first_desc)
  987. descq0 = qib_sdma_make_first_desc0(descq0);
  988. if (pkt->addr[idx].last_desc) {
  989. descq0 = qib_sdma_make_last_desc0(descq0);
  990. if (ppd->sdma_intrequest) {
  991. descq0 |= cpu_to_le64(1ULL << 15);
  992. ppd->sdma_intrequest = 0;
  993. }
  994. }
  995. descqp[0] = descq0;
  996. descqp[1] = qib_sdma_make_desc1(addr);
  997. }
  998. void qib_user_sdma_send_desc(struct qib_pportdata *ppd,
  999. struct list_head *pktlist)
  1000. {
  1001. struct qib_devdata *dd = ppd->dd;
  1002. u16 nfree, nsent;
  1003. u16 tail, tail_c;
  1004. u8 gen, gen_c;
  1005. nfree = qib_sdma_descq_freecnt(ppd);
  1006. if (!nfree)
  1007. return;
  1008. retry:
  1009. nsent = 0;
  1010. tail_c = tail = ppd->sdma_descq_tail;
  1011. gen_c = gen = ppd->sdma_generation;
  1012. while (!list_empty(pktlist)) {
  1013. struct qib_user_sdma_pkt *pkt =
  1014. list_entry(pktlist->next, struct qib_user_sdma_pkt,
  1015. list);
  1016. int i, j, c = 0;
  1017. unsigned ofs = 0;
  1018. u16 dtail = tail;
  1019. for (i = pkt->index; i < pkt->naddr && nfree; i++) {
  1020. qib_user_sdma_send_frag(ppd, pkt, i, ofs, tail, gen);
  1021. ofs += pkt->addr[i].length >> 2;
  1022. if (++tail == ppd->sdma_descq_cnt) {
  1023. tail = 0;
  1024. ++gen;
  1025. ppd->sdma_intrequest = 1;
  1026. } else if (tail == (ppd->sdma_descq_cnt>>1)) {
  1027. ppd->sdma_intrequest = 1;
  1028. }
  1029. nfree--;
  1030. if (pkt->addr[i].last_desc == 0)
  1031. continue;
  1032. /*
  1033. * If the packet is >= 2KB mtu equivalent, we
  1034. * have to use the large buffers, and have to
  1035. * mark each descriptor as part of a large
  1036. * buffer packet.
  1037. */
  1038. if (ofs > dd->piosize2kmax_dwords) {
  1039. for (j = pkt->index; j <= i; j++) {
  1040. ppd->sdma_descq[dtail].qw[0] |=
  1041. cpu_to_le64(1ULL << 14);
  1042. if (++dtail == ppd->sdma_descq_cnt)
  1043. dtail = 0;
  1044. }
  1045. }
  1046. c += i + 1 - pkt->index;
  1047. pkt->index = i + 1; /* index for next first */
  1048. tail_c = dtail = tail;
  1049. gen_c = gen;
  1050. ofs = 0; /* reset for next packet */
  1051. }
  1052. ppd->sdma_descq_added += c;
  1053. nsent += c;
  1054. if (pkt->index == pkt->naddr) {
  1055. pkt->added = ppd->sdma_descq_added;
  1056. pkt->pq->added = pkt->added;
  1057. pkt->pq->num_pending--;
  1058. spin_lock(&pkt->pq->sent_lock);
  1059. pkt->pq->num_sending++;
  1060. list_move_tail(&pkt->list, &pkt->pq->sent);
  1061. spin_unlock(&pkt->pq->sent_lock);
  1062. }
  1063. if (!nfree || (nsent<<2) > ppd->sdma_descq_cnt)
  1064. break;
  1065. }
  1066. /* advance the tail on the chip if necessary */
  1067. if (ppd->sdma_descq_tail != tail_c) {
  1068. ppd->sdma_generation = gen_c;
  1069. dd->f_sdma_update_tail(ppd, tail_c);
  1070. }
  1071. if (nfree && !list_empty(pktlist))
  1072. goto retry;
  1073. return;
  1074. }
  1075. /* pq->lock must be held, get packets on the wire... */
  1076. static int qib_user_sdma_push_pkts(struct qib_pportdata *ppd,
  1077. struct qib_user_sdma_queue *pq,
  1078. struct list_head *pktlist, int count)
  1079. {
  1080. int ret = 0;
  1081. unsigned long flags;
  1082. if (unlikely(!(ppd->lflags & QIBL_LINKACTIVE)))
  1083. return -ECOMM;
  1084. spin_lock_irqsave(&ppd->sdma_lock, flags);
  1085. if (unlikely(!__qib_sdma_running(ppd))) {
  1086. ret = -ECOMM;
  1087. goto unlock;
  1088. }
  1089. pq->num_pending += count;
  1090. list_splice_tail_init(pktlist, &ppd->sdma_userpending);
  1091. qib_user_sdma_send_desc(ppd, &ppd->sdma_userpending);
  1092. unlock:
  1093. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1094. return ret;
  1095. }
  1096. int qib_user_sdma_writev(struct qib_ctxtdata *rcd,
  1097. struct qib_user_sdma_queue *pq,
  1098. const struct iovec *iov,
  1099. unsigned long dim)
  1100. {
  1101. struct qib_devdata *dd = rcd->dd;
  1102. struct qib_pportdata *ppd = rcd->ppd;
  1103. int ret = 0;
  1104. struct list_head list;
  1105. int npkts = 0;
  1106. INIT_LIST_HEAD(&list);
  1107. mutex_lock(&pq->lock);
  1108. /* why not -ECOMM like qib_user_sdma_push_pkts() below? */
  1109. if (!qib_sdma_running(ppd))
  1110. goto done_unlock;
  1111. /* if I have packets not complete yet */
  1112. if (pq->added > ppd->sdma_descq_removed)
  1113. qib_user_sdma_hwqueue_clean(ppd);
  1114. /* if I have complete packets to be freed */
  1115. if (pq->num_sending)
  1116. qib_user_sdma_queue_clean(ppd, pq);
  1117. while (dim) {
  1118. int mxp = 8;
  1119. int ndesc = 0;
  1120. down_write(&current->mm->mmap_sem);
  1121. ret = qib_user_sdma_queue_pkts(dd, ppd, pq,
  1122. iov, dim, &list, &mxp, &ndesc);
  1123. up_write(&current->mm->mmap_sem);
  1124. if (ret < 0)
  1125. goto done_unlock;
  1126. else {
  1127. dim -= ret;
  1128. iov += ret;
  1129. }
  1130. /* force packets onto the sdma hw queue... */
  1131. if (!list_empty(&list)) {
  1132. /*
  1133. * Lazily clean hw queue.
  1134. */
  1135. if (qib_sdma_descq_freecnt(ppd) < ndesc) {
  1136. qib_user_sdma_hwqueue_clean(ppd);
  1137. if (pq->num_sending)
  1138. qib_user_sdma_queue_clean(ppd, pq);
  1139. }
  1140. ret = qib_user_sdma_push_pkts(ppd, pq, &list, mxp);
  1141. if (ret < 0)
  1142. goto done_unlock;
  1143. else {
  1144. npkts += mxp;
  1145. pq->counter += mxp;
  1146. }
  1147. }
  1148. }
  1149. done_unlock:
  1150. if (!list_empty(&list))
  1151. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &list);
  1152. mutex_unlock(&pq->lock);
  1153. return (ret < 0) ? ret : npkts;
  1154. }
  1155. int qib_user_sdma_make_progress(struct qib_pportdata *ppd,
  1156. struct qib_user_sdma_queue *pq)
  1157. {
  1158. int ret = 0;
  1159. mutex_lock(&pq->lock);
  1160. qib_user_sdma_hwqueue_clean(ppd);
  1161. ret = qib_user_sdma_queue_clean(ppd, pq);
  1162. mutex_unlock(&pq->lock);
  1163. return ret;
  1164. }
  1165. u32 qib_user_sdma_complete_counter(const struct qib_user_sdma_queue *pq)
  1166. {
  1167. return pq ? pq->sent_counter : 0;
  1168. }
  1169. u32 qib_user_sdma_inflight_counter(struct qib_user_sdma_queue *pq)
  1170. {
  1171. return pq ? pq->counter : 0;
  1172. }