ocrdma_verbs.c 79 KB

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  1. /*******************************************************************
  2. * This file is part of the Emulex RoCE Device Driver for *
  3. * RoCE (RDMA over Converged Ethernet) adapters. *
  4. * Copyright (C) 2008-2012 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * *
  8. * This program is free software; you can redistribute it and/or *
  9. * modify it under the terms of version 2 of the GNU General *
  10. * Public License as published by the Free Software Foundation. *
  11. * This program is distributed in the hope that it will be useful. *
  12. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  13. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  14. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  15. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  17. * more details, a copy of which can be found in the file COPYING *
  18. * included with this package. *
  19. *
  20. * Contact Information:
  21. * linux-drivers@emulex.com
  22. *
  23. * Emulex
  24. * 3333 Susan Street
  25. * Costa Mesa, CA 92626
  26. *******************************************************************/
  27. #include <linux/dma-mapping.h>
  28. #include <rdma/ib_verbs.h>
  29. #include <rdma/ib_user_verbs.h>
  30. #include <rdma/iw_cm.h>
  31. #include <rdma/ib_umem.h>
  32. #include <rdma/ib_addr.h>
  33. #include "ocrdma.h"
  34. #include "ocrdma_hw.h"
  35. #include "ocrdma_verbs.h"
  36. #include "ocrdma_abi.h"
  37. int ocrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  38. {
  39. if (index > 1)
  40. return -EINVAL;
  41. *pkey = 0xffff;
  42. return 0;
  43. }
  44. int ocrdma_query_gid(struct ib_device *ibdev, u8 port,
  45. int index, union ib_gid *sgid)
  46. {
  47. struct ocrdma_dev *dev;
  48. dev = get_ocrdma_dev(ibdev);
  49. memset(sgid, 0, sizeof(*sgid));
  50. if (index >= OCRDMA_MAX_SGID)
  51. return -EINVAL;
  52. memcpy(sgid, &dev->sgid_tbl[index], sizeof(*sgid));
  53. return 0;
  54. }
  55. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr)
  56. {
  57. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  58. memset(attr, 0, sizeof *attr);
  59. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  60. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  61. ocrdma_get_guid(dev, (u8 *)&attr->sys_image_guid);
  62. attr->max_mr_size = ~0ull;
  63. attr->page_size_cap = 0xffff000;
  64. attr->vendor_id = dev->nic_info.pdev->vendor;
  65. attr->vendor_part_id = dev->nic_info.pdev->device;
  66. attr->hw_ver = 0;
  67. attr->max_qp = dev->attr.max_qp;
  68. attr->max_ah = OCRDMA_MAX_AH;
  69. attr->max_qp_wr = dev->attr.max_wqe;
  70. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  71. IB_DEVICE_RC_RNR_NAK_GEN |
  72. IB_DEVICE_SHUTDOWN_PORT |
  73. IB_DEVICE_SYS_IMAGE_GUID |
  74. IB_DEVICE_LOCAL_DMA_LKEY |
  75. IB_DEVICE_MEM_MGT_EXTENSIONS;
  76. attr->max_sge = min(dev->attr.max_send_sge, dev->attr.max_srq_sge);
  77. attr->max_sge_rd = 0;
  78. attr->max_cq = dev->attr.max_cq;
  79. attr->max_cqe = dev->attr.max_cqe;
  80. attr->max_mr = dev->attr.max_mr;
  81. attr->max_mw = 0;
  82. attr->max_pd = dev->attr.max_pd;
  83. attr->atomic_cap = 0;
  84. attr->max_fmr = 0;
  85. attr->max_map_per_fmr = 0;
  86. attr->max_qp_rd_atom =
  87. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  88. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  89. attr->max_srq = dev->attr.max_srq;
  90. attr->max_srq_sge = dev->attr.max_srq_sge;
  91. attr->max_srq_wr = dev->attr.max_rqe;
  92. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  93. attr->max_fast_reg_page_list_len = 0;
  94. attr->max_pkeys = 1;
  95. return 0;
  96. }
  97. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  98. u8 *ib_speed, u8 *ib_width)
  99. {
  100. int status;
  101. u8 speed;
  102. status = ocrdma_mbx_get_link_speed(dev, &speed);
  103. if (status)
  104. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  105. switch (speed) {
  106. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  107. *ib_speed = IB_SPEED_SDR;
  108. *ib_width = IB_WIDTH_1X;
  109. break;
  110. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  111. *ib_speed = IB_SPEED_QDR;
  112. *ib_width = IB_WIDTH_1X;
  113. break;
  114. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  115. *ib_speed = IB_SPEED_DDR;
  116. *ib_width = IB_WIDTH_4X;
  117. break;
  118. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  119. *ib_speed = IB_SPEED_QDR;
  120. *ib_width = IB_WIDTH_4X;
  121. break;
  122. default:
  123. /* Unsupported */
  124. *ib_speed = IB_SPEED_SDR;
  125. *ib_width = IB_WIDTH_1X;
  126. };
  127. }
  128. int ocrdma_query_port(struct ib_device *ibdev,
  129. u8 port, struct ib_port_attr *props)
  130. {
  131. enum ib_port_state port_state;
  132. struct ocrdma_dev *dev;
  133. struct net_device *netdev;
  134. dev = get_ocrdma_dev(ibdev);
  135. if (port > 1) {
  136. pr_err("%s(%d) invalid_port=0x%x\n", __func__,
  137. dev->id, port);
  138. return -EINVAL;
  139. }
  140. netdev = dev->nic_info.netdev;
  141. if (netif_running(netdev) && netif_oper_up(netdev)) {
  142. port_state = IB_PORT_ACTIVE;
  143. props->phys_state = 5;
  144. } else {
  145. port_state = IB_PORT_DOWN;
  146. props->phys_state = 3;
  147. }
  148. props->max_mtu = IB_MTU_4096;
  149. props->active_mtu = iboe_get_mtu(netdev->mtu);
  150. props->lid = 0;
  151. props->lmc = 0;
  152. props->sm_lid = 0;
  153. props->sm_sl = 0;
  154. props->state = port_state;
  155. props->port_cap_flags =
  156. IB_PORT_CM_SUP |
  157. IB_PORT_REINIT_SUP |
  158. IB_PORT_DEVICE_MGMT_SUP | IB_PORT_VENDOR_CLASS_SUP;
  159. props->gid_tbl_len = OCRDMA_MAX_SGID;
  160. props->pkey_tbl_len = 1;
  161. props->bad_pkey_cntr = 0;
  162. props->qkey_viol_cntr = 0;
  163. get_link_speed_and_width(dev, &props->active_speed,
  164. &props->active_width);
  165. props->max_msg_sz = 0x80000000;
  166. props->max_vl_num = 4;
  167. return 0;
  168. }
  169. int ocrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
  170. struct ib_port_modify *props)
  171. {
  172. struct ocrdma_dev *dev;
  173. dev = get_ocrdma_dev(ibdev);
  174. if (port > 1) {
  175. pr_err("%s(%d) invalid_port=0x%x\n", __func__, dev->id, port);
  176. return -EINVAL;
  177. }
  178. return 0;
  179. }
  180. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  181. unsigned long len)
  182. {
  183. struct ocrdma_mm *mm;
  184. mm = kzalloc(sizeof(*mm), GFP_KERNEL);
  185. if (mm == NULL)
  186. return -ENOMEM;
  187. mm->key.phy_addr = phy_addr;
  188. mm->key.len = len;
  189. INIT_LIST_HEAD(&mm->entry);
  190. mutex_lock(&uctx->mm_list_lock);
  191. list_add_tail(&mm->entry, &uctx->mm_head);
  192. mutex_unlock(&uctx->mm_list_lock);
  193. return 0;
  194. }
  195. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  196. unsigned long len)
  197. {
  198. struct ocrdma_mm *mm, *tmp;
  199. mutex_lock(&uctx->mm_list_lock);
  200. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  201. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  202. continue;
  203. list_del(&mm->entry);
  204. kfree(mm);
  205. break;
  206. }
  207. mutex_unlock(&uctx->mm_list_lock);
  208. }
  209. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  210. unsigned long len)
  211. {
  212. bool found = false;
  213. struct ocrdma_mm *mm;
  214. mutex_lock(&uctx->mm_list_lock);
  215. list_for_each_entry(mm, &uctx->mm_head, entry) {
  216. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  217. continue;
  218. found = true;
  219. break;
  220. }
  221. mutex_unlock(&uctx->mm_list_lock);
  222. return found;
  223. }
  224. static struct ocrdma_pd *_ocrdma_alloc_pd(struct ocrdma_dev *dev,
  225. struct ocrdma_ucontext *uctx,
  226. struct ib_udata *udata)
  227. {
  228. struct ocrdma_pd *pd = NULL;
  229. int status = 0;
  230. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  231. if (!pd)
  232. return ERR_PTR(-ENOMEM);
  233. if (udata && uctx) {
  234. pd->dpp_enabled =
  235. dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY;
  236. pd->num_dpp_qp =
  237. pd->dpp_enabled ? OCRDMA_PD_MAX_DPP_ENABLED_QP : 0;
  238. }
  239. retry:
  240. status = ocrdma_mbx_alloc_pd(dev, pd);
  241. if (status) {
  242. if (pd->dpp_enabled) {
  243. pd->dpp_enabled = false;
  244. pd->num_dpp_qp = 0;
  245. goto retry;
  246. } else {
  247. kfree(pd);
  248. return ERR_PTR(status);
  249. }
  250. }
  251. return pd;
  252. }
  253. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  254. struct ocrdma_pd *pd)
  255. {
  256. return (uctx->cntxt_pd == pd ? true : false);
  257. }
  258. static int _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  259. struct ocrdma_pd *pd)
  260. {
  261. int status = 0;
  262. status = ocrdma_mbx_dealloc_pd(dev, pd);
  263. kfree(pd);
  264. return status;
  265. }
  266. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  267. struct ocrdma_ucontext *uctx,
  268. struct ib_udata *udata)
  269. {
  270. int status = 0;
  271. uctx->cntxt_pd = _ocrdma_alloc_pd(dev, uctx, udata);
  272. if (IS_ERR(uctx->cntxt_pd)) {
  273. status = PTR_ERR(uctx->cntxt_pd);
  274. uctx->cntxt_pd = NULL;
  275. goto err;
  276. }
  277. uctx->cntxt_pd->uctx = uctx;
  278. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  279. err:
  280. return status;
  281. }
  282. static int ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  283. {
  284. int status = 0;
  285. struct ocrdma_pd *pd = uctx->cntxt_pd;
  286. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  287. BUG_ON(uctx->pd_in_use);
  288. uctx->cntxt_pd = NULL;
  289. status = _ocrdma_dealloc_pd(dev, pd);
  290. return status;
  291. }
  292. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  293. {
  294. struct ocrdma_pd *pd = NULL;
  295. mutex_lock(&uctx->mm_list_lock);
  296. if (!uctx->pd_in_use) {
  297. uctx->pd_in_use = true;
  298. pd = uctx->cntxt_pd;
  299. }
  300. mutex_unlock(&uctx->mm_list_lock);
  301. return pd;
  302. }
  303. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  304. {
  305. mutex_lock(&uctx->mm_list_lock);
  306. uctx->pd_in_use = false;
  307. mutex_unlock(&uctx->mm_list_lock);
  308. }
  309. struct ib_ucontext *ocrdma_alloc_ucontext(struct ib_device *ibdev,
  310. struct ib_udata *udata)
  311. {
  312. int status;
  313. struct ocrdma_ucontext *ctx;
  314. struct ocrdma_alloc_ucontext_resp resp;
  315. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  316. struct pci_dev *pdev = dev->nic_info.pdev;
  317. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  318. if (!udata)
  319. return ERR_PTR(-EFAULT);
  320. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  321. if (!ctx)
  322. return ERR_PTR(-ENOMEM);
  323. INIT_LIST_HEAD(&ctx->mm_head);
  324. mutex_init(&ctx->mm_list_lock);
  325. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  326. &ctx->ah_tbl.pa, GFP_KERNEL);
  327. if (!ctx->ah_tbl.va) {
  328. kfree(ctx);
  329. return ERR_PTR(-ENOMEM);
  330. }
  331. memset(ctx->ah_tbl.va, 0, map_len);
  332. ctx->ah_tbl.len = map_len;
  333. memset(&resp, 0, sizeof(resp));
  334. resp.ah_tbl_len = ctx->ah_tbl.len;
  335. resp.ah_tbl_page = ctx->ah_tbl.pa;
  336. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  337. if (status)
  338. goto map_err;
  339. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  340. if (status)
  341. goto pd_err;
  342. resp.dev_id = dev->id;
  343. resp.max_inline_data = dev->attr.max_inline_data;
  344. resp.wqe_size = dev->attr.wqe_size;
  345. resp.rqe_size = dev->attr.rqe_size;
  346. resp.dpp_wqe_size = dev->attr.wqe_size;
  347. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  348. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  349. if (status)
  350. goto cpy_err;
  351. return &ctx->ibucontext;
  352. cpy_err:
  353. pd_err:
  354. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  355. map_err:
  356. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  357. ctx->ah_tbl.pa);
  358. kfree(ctx);
  359. return ERR_PTR(status);
  360. }
  361. int ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  362. {
  363. int status = 0;
  364. struct ocrdma_mm *mm, *tmp;
  365. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  366. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  367. struct pci_dev *pdev = dev->nic_info.pdev;
  368. status = ocrdma_dealloc_ucontext_pd(uctx);
  369. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  370. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  371. uctx->ah_tbl.pa);
  372. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  373. list_del(&mm->entry);
  374. kfree(mm);
  375. }
  376. kfree(uctx);
  377. return status;
  378. }
  379. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  380. {
  381. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  382. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  383. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  384. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  385. unsigned long len = (vma->vm_end - vma->vm_start);
  386. int status = 0;
  387. bool found;
  388. if (vma->vm_start & (PAGE_SIZE - 1))
  389. return -EINVAL;
  390. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  391. if (!found)
  392. return -EINVAL;
  393. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  394. dev->nic_info.db_total_size)) &&
  395. (len <= dev->nic_info.db_page_size)) {
  396. if (vma->vm_flags & VM_READ)
  397. return -EPERM;
  398. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  399. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  400. len, vma->vm_page_prot);
  401. } else if (dev->nic_info.dpp_unmapped_len &&
  402. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  403. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  404. dev->nic_info.dpp_unmapped_len)) &&
  405. (len <= dev->nic_info.dpp_unmapped_len)) {
  406. if (vma->vm_flags & VM_READ)
  407. return -EPERM;
  408. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  409. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  410. len, vma->vm_page_prot);
  411. } else {
  412. status = remap_pfn_range(vma, vma->vm_start,
  413. vma->vm_pgoff, len, vma->vm_page_prot);
  414. }
  415. return status;
  416. }
  417. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  418. struct ib_ucontext *ib_ctx,
  419. struct ib_udata *udata)
  420. {
  421. int status;
  422. u64 db_page_addr;
  423. u64 dpp_page_addr = 0;
  424. u32 db_page_size;
  425. struct ocrdma_alloc_pd_uresp rsp;
  426. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  427. memset(&rsp, 0, sizeof(rsp));
  428. rsp.id = pd->id;
  429. rsp.dpp_enabled = pd->dpp_enabled;
  430. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  431. db_page_size = dev->nic_info.db_page_size;
  432. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  433. if (status)
  434. return status;
  435. if (pd->dpp_enabled) {
  436. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  437. (pd->id * PAGE_SIZE);
  438. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  439. PAGE_SIZE);
  440. if (status)
  441. goto dpp_map_err;
  442. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  443. rsp.dpp_page_addr_lo = dpp_page_addr;
  444. }
  445. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  446. if (status)
  447. goto ucopy_err;
  448. pd->uctx = uctx;
  449. return 0;
  450. ucopy_err:
  451. if (pd->dpp_enabled)
  452. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  453. dpp_map_err:
  454. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  455. return status;
  456. }
  457. struct ib_pd *ocrdma_alloc_pd(struct ib_device *ibdev,
  458. struct ib_ucontext *context,
  459. struct ib_udata *udata)
  460. {
  461. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  462. struct ocrdma_pd *pd;
  463. struct ocrdma_ucontext *uctx = NULL;
  464. int status;
  465. u8 is_uctx_pd = false;
  466. if (udata && context) {
  467. uctx = get_ocrdma_ucontext(context);
  468. pd = ocrdma_get_ucontext_pd(uctx);
  469. if (pd) {
  470. is_uctx_pd = true;
  471. goto pd_mapping;
  472. }
  473. }
  474. pd = _ocrdma_alloc_pd(dev, uctx, udata);
  475. if (IS_ERR(pd)) {
  476. status = PTR_ERR(pd);
  477. goto exit;
  478. }
  479. pd_mapping:
  480. if (udata && context) {
  481. status = ocrdma_copy_pd_uresp(dev, pd, context, udata);
  482. if (status)
  483. goto err;
  484. }
  485. return &pd->ibpd;
  486. err:
  487. if (is_uctx_pd) {
  488. ocrdma_release_ucontext_pd(uctx);
  489. } else {
  490. status = ocrdma_mbx_dealloc_pd(dev, pd);
  491. kfree(pd);
  492. }
  493. exit:
  494. return ERR_PTR(status);
  495. }
  496. int ocrdma_dealloc_pd(struct ib_pd *ibpd)
  497. {
  498. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  499. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  500. struct ocrdma_ucontext *uctx = NULL;
  501. int status = 0;
  502. u64 usr_db;
  503. uctx = pd->uctx;
  504. if (uctx) {
  505. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  506. (pd->id * PAGE_SIZE);
  507. if (pd->dpp_enabled)
  508. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  509. usr_db = ocrdma_get_db_addr(dev, pd->id);
  510. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  511. if (is_ucontext_pd(uctx, pd)) {
  512. ocrdma_release_ucontext_pd(uctx);
  513. return status;
  514. }
  515. }
  516. status = _ocrdma_dealloc_pd(dev, pd);
  517. return status;
  518. }
  519. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  520. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  521. {
  522. int status;
  523. mr->hwmr.fr_mr = 0;
  524. mr->hwmr.local_rd = 1;
  525. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  526. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  527. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  528. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  529. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  530. mr->hwmr.num_pbls = num_pbls;
  531. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  532. if (status)
  533. return status;
  534. mr->ibmr.lkey = mr->hwmr.lkey;
  535. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  536. mr->ibmr.rkey = mr->hwmr.lkey;
  537. return 0;
  538. }
  539. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  540. {
  541. int status;
  542. struct ocrdma_mr *mr;
  543. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  544. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  545. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  546. pr_err("%s err, invalid access rights\n", __func__);
  547. return ERR_PTR(-EINVAL);
  548. }
  549. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  550. if (!mr)
  551. return ERR_PTR(-ENOMEM);
  552. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  553. OCRDMA_ADDR_CHECK_DISABLE);
  554. if (status) {
  555. kfree(mr);
  556. return ERR_PTR(status);
  557. }
  558. return &mr->ibmr;
  559. }
  560. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  561. struct ocrdma_hw_mr *mr)
  562. {
  563. struct pci_dev *pdev = dev->nic_info.pdev;
  564. int i = 0;
  565. if (mr->pbl_table) {
  566. for (i = 0; i < mr->num_pbls; i++) {
  567. if (!mr->pbl_table[i].va)
  568. continue;
  569. dma_free_coherent(&pdev->dev, mr->pbl_size,
  570. mr->pbl_table[i].va,
  571. mr->pbl_table[i].pa);
  572. }
  573. kfree(mr->pbl_table);
  574. mr->pbl_table = NULL;
  575. }
  576. }
  577. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  578. u32 num_pbes)
  579. {
  580. u32 num_pbls = 0;
  581. u32 idx = 0;
  582. int status = 0;
  583. u32 pbl_size;
  584. do {
  585. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  586. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  587. status = -EFAULT;
  588. break;
  589. }
  590. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  591. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  592. idx++;
  593. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  594. mr->hwmr.num_pbes = num_pbes;
  595. mr->hwmr.num_pbls = num_pbls;
  596. mr->hwmr.pbl_size = pbl_size;
  597. return status;
  598. }
  599. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  600. {
  601. int status = 0;
  602. int i;
  603. u32 dma_len = mr->pbl_size;
  604. struct pci_dev *pdev = dev->nic_info.pdev;
  605. void *va;
  606. dma_addr_t pa;
  607. mr->pbl_table = kzalloc(sizeof(struct ocrdma_pbl) *
  608. mr->num_pbls, GFP_KERNEL);
  609. if (!mr->pbl_table)
  610. return -ENOMEM;
  611. for (i = 0; i < mr->num_pbls; i++) {
  612. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  613. if (!va) {
  614. ocrdma_free_mr_pbl_tbl(dev, mr);
  615. status = -ENOMEM;
  616. break;
  617. }
  618. memset(va, 0, dma_len);
  619. mr->pbl_table[i].va = va;
  620. mr->pbl_table[i].pa = pa;
  621. }
  622. return status;
  623. }
  624. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  625. u32 num_pbes)
  626. {
  627. struct ocrdma_pbe *pbe;
  628. struct ib_umem_chunk *chunk;
  629. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  630. struct ib_umem *umem = mr->umem;
  631. int i, shift, pg_cnt, pages, pbe_cnt, total_num_pbes = 0;
  632. if (!mr->hwmr.num_pbes)
  633. return;
  634. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  635. pbe_cnt = 0;
  636. shift = ilog2(umem->page_size);
  637. list_for_each_entry(chunk, &umem->chunk_list, list) {
  638. /* get all the dma regions from the chunk. */
  639. for (i = 0; i < chunk->nmap; i++) {
  640. pages = sg_dma_len(&chunk->page_list[i]) >> shift;
  641. for (pg_cnt = 0; pg_cnt < pages; pg_cnt++) {
  642. /* store the page address in pbe */
  643. pbe->pa_lo =
  644. cpu_to_le32(sg_dma_address
  645. (&chunk->page_list[i]) +
  646. (umem->page_size * pg_cnt));
  647. pbe->pa_hi =
  648. cpu_to_le32(upper_32_bits
  649. ((sg_dma_address
  650. (&chunk->page_list[i]) +
  651. umem->page_size * pg_cnt)));
  652. pbe_cnt += 1;
  653. total_num_pbes += 1;
  654. pbe++;
  655. /* if done building pbes, issue the mbx cmd. */
  656. if (total_num_pbes == num_pbes)
  657. return;
  658. /* if the given pbl is full storing the pbes,
  659. * move to next pbl.
  660. */
  661. if (pbe_cnt ==
  662. (mr->hwmr.pbl_size / sizeof(u64))) {
  663. pbl_tbl++;
  664. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  665. pbe_cnt = 0;
  666. }
  667. }
  668. }
  669. }
  670. }
  671. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  672. u64 usr_addr, int acc, struct ib_udata *udata)
  673. {
  674. int status = -ENOMEM;
  675. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  676. struct ocrdma_mr *mr;
  677. struct ocrdma_pd *pd;
  678. u32 num_pbes;
  679. pd = get_ocrdma_pd(ibpd);
  680. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  681. return ERR_PTR(-EINVAL);
  682. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  683. if (!mr)
  684. return ERR_PTR(status);
  685. mr->umem = ib_umem_get(ibpd->uobject->context, start, len, acc, 0);
  686. if (IS_ERR(mr->umem)) {
  687. status = -EFAULT;
  688. goto umem_err;
  689. }
  690. num_pbes = ib_umem_page_count(mr->umem);
  691. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  692. if (status)
  693. goto umem_err;
  694. mr->hwmr.pbe_size = mr->umem->page_size;
  695. mr->hwmr.fbo = mr->umem->offset;
  696. mr->hwmr.va = usr_addr;
  697. mr->hwmr.len = len;
  698. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  699. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  700. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  701. mr->hwmr.local_rd = 1;
  702. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  703. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  704. if (status)
  705. goto umem_err;
  706. build_user_pbes(dev, mr, num_pbes);
  707. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  708. if (status)
  709. goto mbx_err;
  710. mr->ibmr.lkey = mr->hwmr.lkey;
  711. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  712. mr->ibmr.rkey = mr->hwmr.lkey;
  713. return &mr->ibmr;
  714. mbx_err:
  715. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  716. umem_err:
  717. kfree(mr);
  718. return ERR_PTR(status);
  719. }
  720. int ocrdma_dereg_mr(struct ib_mr *ib_mr)
  721. {
  722. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  723. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  724. int status;
  725. status = ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  726. if (mr->hwmr.fr_mr == 0)
  727. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  728. /* it could be user registered memory. */
  729. if (mr->umem)
  730. ib_umem_release(mr->umem);
  731. kfree(mr);
  732. return status;
  733. }
  734. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  735. struct ib_udata *udata,
  736. struct ib_ucontext *ib_ctx)
  737. {
  738. int status;
  739. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ib_ctx);
  740. struct ocrdma_create_cq_uresp uresp;
  741. memset(&uresp, 0, sizeof(uresp));
  742. uresp.cq_id = cq->id;
  743. uresp.page_size = PAGE_ALIGN(cq->len);
  744. uresp.num_pages = 1;
  745. uresp.max_hw_cqe = cq->max_hw_cqe;
  746. uresp.page_addr[0] = cq->pa;
  747. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  748. uresp.db_page_size = dev->nic_info.db_page_size;
  749. uresp.phase_change = cq->phase_change ? 1 : 0;
  750. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  751. if (status) {
  752. pr_err("%s(%d) copy error cqid=0x%x.\n",
  753. __func__, dev->id, cq->id);
  754. goto err;
  755. }
  756. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  757. if (status)
  758. goto err;
  759. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  760. if (status) {
  761. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  762. goto err;
  763. }
  764. cq->ucontext = uctx;
  765. err:
  766. return status;
  767. }
  768. struct ib_cq *ocrdma_create_cq(struct ib_device *ibdev, int entries, int vector,
  769. struct ib_ucontext *ib_ctx,
  770. struct ib_udata *udata)
  771. {
  772. struct ocrdma_cq *cq;
  773. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  774. struct ocrdma_ucontext *uctx = NULL;
  775. u16 pd_id = 0;
  776. int status;
  777. struct ocrdma_create_cq_ureq ureq;
  778. if (udata) {
  779. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  780. return ERR_PTR(-EFAULT);
  781. } else
  782. ureq.dpp_cq = 0;
  783. cq = kzalloc(sizeof(*cq), GFP_KERNEL);
  784. if (!cq)
  785. return ERR_PTR(-ENOMEM);
  786. spin_lock_init(&cq->cq_lock);
  787. spin_lock_init(&cq->comp_handler_lock);
  788. INIT_LIST_HEAD(&cq->sq_head);
  789. INIT_LIST_HEAD(&cq->rq_head);
  790. if (ib_ctx) {
  791. uctx = get_ocrdma_ucontext(ib_ctx);
  792. pd_id = uctx->cntxt_pd->id;
  793. }
  794. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  795. if (status) {
  796. kfree(cq);
  797. return ERR_PTR(status);
  798. }
  799. if (ib_ctx) {
  800. status = ocrdma_copy_cq_uresp(dev, cq, udata, ib_ctx);
  801. if (status)
  802. goto ctx_err;
  803. }
  804. cq->phase = OCRDMA_CQE_VALID;
  805. cq->arm_needed = true;
  806. dev->cq_tbl[cq->id] = cq;
  807. return &cq->ibcq;
  808. ctx_err:
  809. ocrdma_mbx_destroy_cq(dev, cq);
  810. kfree(cq);
  811. return ERR_PTR(status);
  812. }
  813. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  814. struct ib_udata *udata)
  815. {
  816. int status = 0;
  817. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  818. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  819. status = -EINVAL;
  820. return status;
  821. }
  822. ibcq->cqe = new_cnt;
  823. return status;
  824. }
  825. int ocrdma_destroy_cq(struct ib_cq *ibcq)
  826. {
  827. int status;
  828. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  829. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  830. int pdid = 0;
  831. status = ocrdma_mbx_destroy_cq(dev, cq);
  832. if (cq->ucontext) {
  833. pdid = cq->ucontext->cntxt_pd->id;
  834. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  835. PAGE_ALIGN(cq->len));
  836. ocrdma_del_mmap(cq->ucontext,
  837. ocrdma_get_db_addr(dev, pdid),
  838. dev->nic_info.db_page_size);
  839. }
  840. dev->cq_tbl[cq->id] = NULL;
  841. kfree(cq);
  842. return status;
  843. }
  844. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  845. {
  846. int status = -EINVAL;
  847. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  848. dev->qp_tbl[qp->id] = qp;
  849. status = 0;
  850. }
  851. return status;
  852. }
  853. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  854. {
  855. dev->qp_tbl[qp->id] = NULL;
  856. }
  857. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  858. struct ib_qp_init_attr *attrs)
  859. {
  860. if ((attrs->qp_type != IB_QPT_GSI) &&
  861. (attrs->qp_type != IB_QPT_RC) &&
  862. (attrs->qp_type != IB_QPT_UC) &&
  863. (attrs->qp_type != IB_QPT_UD)) {
  864. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  865. __func__, dev->id, attrs->qp_type);
  866. return -EINVAL;
  867. }
  868. /* Skip the check for QP1 to support CM size of 128 */
  869. if ((attrs->qp_type != IB_QPT_GSI) &&
  870. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  871. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  872. __func__, dev->id, attrs->cap.max_send_wr);
  873. pr_err("%s(%d) supported send_wr=0x%x\n",
  874. __func__, dev->id, dev->attr.max_wqe);
  875. return -EINVAL;
  876. }
  877. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  878. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  879. __func__, dev->id, attrs->cap.max_recv_wr);
  880. pr_err("%s(%d) supported recv_wr=0x%x\n",
  881. __func__, dev->id, dev->attr.max_rqe);
  882. return -EINVAL;
  883. }
  884. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  885. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  886. __func__, dev->id, attrs->cap.max_inline_data);
  887. pr_err("%s(%d) supported inline data size=0x%x\n",
  888. __func__, dev->id, dev->attr.max_inline_data);
  889. return -EINVAL;
  890. }
  891. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  892. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  893. __func__, dev->id, attrs->cap.max_send_sge);
  894. pr_err("%s(%d) supported send_sge=0x%x\n",
  895. __func__, dev->id, dev->attr.max_send_sge);
  896. return -EINVAL;
  897. }
  898. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  899. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  900. __func__, dev->id, attrs->cap.max_recv_sge);
  901. pr_err("%s(%d) supported recv_sge=0x%x\n",
  902. __func__, dev->id, dev->attr.max_recv_sge);
  903. return -EINVAL;
  904. }
  905. /* unprivileged user space cannot create special QP */
  906. if (ibpd->uobject && attrs->qp_type == IB_QPT_GSI) {
  907. pr_err
  908. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  909. __func__, dev->id, attrs->qp_type);
  910. return -EINVAL;
  911. }
  912. /* allow creating only one GSI type of QP */
  913. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  914. pr_err("%s(%d) GSI special QPs already created.\n",
  915. __func__, dev->id);
  916. return -EINVAL;
  917. }
  918. /* verify consumer QPs are not trying to use GSI QP's CQ */
  919. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  920. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  921. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  922. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  923. __func__, dev->id);
  924. return -EINVAL;
  925. }
  926. }
  927. return 0;
  928. }
  929. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  930. struct ib_udata *udata, int dpp_offset,
  931. int dpp_credit_lmt, int srq)
  932. {
  933. int status = 0;
  934. u64 usr_db;
  935. struct ocrdma_create_qp_uresp uresp;
  936. struct ocrdma_dev *dev = qp->dev;
  937. struct ocrdma_pd *pd = qp->pd;
  938. memset(&uresp, 0, sizeof(uresp));
  939. usr_db = dev->nic_info.unmapped_db +
  940. (pd->id * dev->nic_info.db_page_size);
  941. uresp.qp_id = qp->id;
  942. uresp.sq_dbid = qp->sq.dbid;
  943. uresp.num_sq_pages = 1;
  944. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  945. uresp.sq_page_addr[0] = qp->sq.pa;
  946. uresp.num_wqe_allocated = qp->sq.max_cnt;
  947. if (!srq) {
  948. uresp.rq_dbid = qp->rq.dbid;
  949. uresp.num_rq_pages = 1;
  950. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  951. uresp.rq_page_addr[0] = qp->rq.pa;
  952. uresp.num_rqe_allocated = qp->rq.max_cnt;
  953. }
  954. uresp.db_page_addr = usr_db;
  955. uresp.db_page_size = dev->nic_info.db_page_size;
  956. if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
  957. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  958. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  959. uresp.db_shift = 24;
  960. } else {
  961. uresp.db_sq_offset = OCRDMA_DB_SQ_OFFSET;
  962. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  963. uresp.db_shift = 16;
  964. }
  965. if (qp->dpp_enabled) {
  966. uresp.dpp_credit = dpp_credit_lmt;
  967. uresp.dpp_offset = dpp_offset;
  968. }
  969. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  970. if (status) {
  971. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  972. goto err;
  973. }
  974. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  975. uresp.sq_page_size);
  976. if (status)
  977. goto err;
  978. if (!srq) {
  979. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  980. uresp.rq_page_size);
  981. if (status)
  982. goto rq_map_err;
  983. }
  984. return status;
  985. rq_map_err:
  986. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  987. err:
  988. return status;
  989. }
  990. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  991. struct ocrdma_pd *pd)
  992. {
  993. if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
  994. qp->sq_db = dev->nic_info.db +
  995. (pd->id * dev->nic_info.db_page_size) +
  996. OCRDMA_DB_GEN2_SQ_OFFSET;
  997. qp->rq_db = dev->nic_info.db +
  998. (pd->id * dev->nic_info.db_page_size) +
  999. OCRDMA_DB_GEN2_RQ_OFFSET;
  1000. } else {
  1001. qp->sq_db = dev->nic_info.db +
  1002. (pd->id * dev->nic_info.db_page_size) +
  1003. OCRDMA_DB_SQ_OFFSET;
  1004. qp->rq_db = dev->nic_info.db +
  1005. (pd->id * dev->nic_info.db_page_size) +
  1006. OCRDMA_DB_RQ_OFFSET;
  1007. }
  1008. }
  1009. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1010. {
  1011. qp->wqe_wr_id_tbl =
  1012. kzalloc(sizeof(*(qp->wqe_wr_id_tbl)) * qp->sq.max_cnt,
  1013. GFP_KERNEL);
  1014. if (qp->wqe_wr_id_tbl == NULL)
  1015. return -ENOMEM;
  1016. qp->rqe_wr_id_tbl =
  1017. kzalloc(sizeof(u64) * qp->rq.max_cnt, GFP_KERNEL);
  1018. if (qp->rqe_wr_id_tbl == NULL)
  1019. return -ENOMEM;
  1020. return 0;
  1021. }
  1022. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1023. struct ocrdma_pd *pd,
  1024. struct ib_qp_init_attr *attrs)
  1025. {
  1026. qp->pd = pd;
  1027. spin_lock_init(&qp->q_lock);
  1028. INIT_LIST_HEAD(&qp->sq_entry);
  1029. INIT_LIST_HEAD(&qp->rq_entry);
  1030. qp->qp_type = attrs->qp_type;
  1031. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1032. qp->max_inline_data = attrs->cap.max_inline_data;
  1033. qp->sq.max_sges = attrs->cap.max_send_sge;
  1034. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1035. qp->state = OCRDMA_QPS_RST;
  1036. qp->signaled = (attrs->sq_sig_type == IB_SIGNAL_ALL_WR) ? true : false;
  1037. }
  1038. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1039. struct ib_qp_init_attr *attrs)
  1040. {
  1041. if (attrs->qp_type == IB_QPT_GSI) {
  1042. dev->gsi_qp_created = 1;
  1043. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1044. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1045. }
  1046. }
  1047. struct ib_qp *ocrdma_create_qp(struct ib_pd *ibpd,
  1048. struct ib_qp_init_attr *attrs,
  1049. struct ib_udata *udata)
  1050. {
  1051. int status;
  1052. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1053. struct ocrdma_qp *qp;
  1054. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1055. struct ocrdma_create_qp_ureq ureq;
  1056. u16 dpp_credit_lmt, dpp_offset;
  1057. status = ocrdma_check_qp_params(ibpd, dev, attrs);
  1058. if (status)
  1059. goto gen_err;
  1060. memset(&ureq, 0, sizeof(ureq));
  1061. if (udata) {
  1062. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1063. return ERR_PTR(-EFAULT);
  1064. }
  1065. qp = kzalloc(sizeof(*qp), GFP_KERNEL);
  1066. if (!qp) {
  1067. status = -ENOMEM;
  1068. goto gen_err;
  1069. }
  1070. qp->dev = dev;
  1071. ocrdma_set_qp_init_params(qp, pd, attrs);
  1072. if (udata == NULL)
  1073. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1074. OCRDMA_QP_FAST_REG);
  1075. mutex_lock(&dev->dev_lock);
  1076. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1077. ureq.dpp_cq_id,
  1078. &dpp_offset, &dpp_credit_lmt);
  1079. if (status)
  1080. goto mbx_err;
  1081. /* user space QP's wr_id table are managed in library */
  1082. if (udata == NULL) {
  1083. status = ocrdma_alloc_wr_id_tbl(qp);
  1084. if (status)
  1085. goto map_err;
  1086. }
  1087. status = ocrdma_add_qpn_map(dev, qp);
  1088. if (status)
  1089. goto map_err;
  1090. ocrdma_set_qp_db(dev, qp, pd);
  1091. if (udata) {
  1092. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1093. dpp_credit_lmt,
  1094. (attrs->srq != NULL));
  1095. if (status)
  1096. goto cpy_err;
  1097. }
  1098. ocrdma_store_gsi_qp_cq(dev, attrs);
  1099. qp->ibqp.qp_num = qp->id;
  1100. mutex_unlock(&dev->dev_lock);
  1101. return &qp->ibqp;
  1102. cpy_err:
  1103. ocrdma_del_qpn_map(dev, qp);
  1104. map_err:
  1105. ocrdma_mbx_destroy_qp(dev, qp);
  1106. mbx_err:
  1107. mutex_unlock(&dev->dev_lock);
  1108. kfree(qp->wqe_wr_id_tbl);
  1109. kfree(qp->rqe_wr_id_tbl);
  1110. kfree(qp);
  1111. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1112. gen_err:
  1113. return ERR_PTR(status);
  1114. }
  1115. static void ocrdma_flush_rq_db(struct ocrdma_qp *qp)
  1116. {
  1117. if (qp->db_cache) {
  1118. u32 val = qp->rq.dbid | (qp->db_cache <<
  1119. ocrdma_get_num_posted_shift(qp));
  1120. iowrite32(val, qp->rq_db);
  1121. qp->db_cache = 0;
  1122. }
  1123. }
  1124. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1125. int attr_mask)
  1126. {
  1127. int status = 0;
  1128. struct ocrdma_qp *qp;
  1129. struct ocrdma_dev *dev;
  1130. enum ib_qp_state old_qps;
  1131. qp = get_ocrdma_qp(ibqp);
  1132. dev = qp->dev;
  1133. if (attr_mask & IB_QP_STATE)
  1134. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1135. /* if new and previous states are same hw doesn't need to
  1136. * know about it.
  1137. */
  1138. if (status < 0)
  1139. return status;
  1140. status = ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask, old_qps);
  1141. if (!status && attr_mask & IB_QP_STATE && attr->qp_state == IB_QPS_RTR)
  1142. ocrdma_flush_rq_db(qp);
  1143. return status;
  1144. }
  1145. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1146. int attr_mask, struct ib_udata *udata)
  1147. {
  1148. unsigned long flags;
  1149. int status = -EINVAL;
  1150. struct ocrdma_qp *qp;
  1151. struct ocrdma_dev *dev;
  1152. enum ib_qp_state old_qps, new_qps;
  1153. qp = get_ocrdma_qp(ibqp);
  1154. dev = qp->dev;
  1155. /* syncronize with multiple context trying to change, retrive qps */
  1156. mutex_lock(&dev->dev_lock);
  1157. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1158. spin_lock_irqsave(&qp->q_lock, flags);
  1159. old_qps = get_ibqp_state(qp->state);
  1160. if (attr_mask & IB_QP_STATE)
  1161. new_qps = attr->qp_state;
  1162. else
  1163. new_qps = old_qps;
  1164. spin_unlock_irqrestore(&qp->q_lock, flags);
  1165. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask)) {
  1166. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1167. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1168. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1169. old_qps, new_qps);
  1170. goto param_err;
  1171. }
  1172. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1173. if (status > 0)
  1174. status = 0;
  1175. param_err:
  1176. mutex_unlock(&dev->dev_lock);
  1177. return status;
  1178. }
  1179. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1180. {
  1181. switch (mtu) {
  1182. case 256:
  1183. return IB_MTU_256;
  1184. case 512:
  1185. return IB_MTU_512;
  1186. case 1024:
  1187. return IB_MTU_1024;
  1188. case 2048:
  1189. return IB_MTU_2048;
  1190. case 4096:
  1191. return IB_MTU_4096;
  1192. default:
  1193. return IB_MTU_1024;
  1194. }
  1195. }
  1196. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1197. {
  1198. int ib_qp_acc_flags = 0;
  1199. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1200. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1201. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1202. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1203. return ib_qp_acc_flags;
  1204. }
  1205. int ocrdma_query_qp(struct ib_qp *ibqp,
  1206. struct ib_qp_attr *qp_attr,
  1207. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1208. {
  1209. int status;
  1210. u32 qp_state;
  1211. struct ocrdma_qp_params params;
  1212. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1213. struct ocrdma_dev *dev = qp->dev;
  1214. memset(&params, 0, sizeof(params));
  1215. mutex_lock(&dev->dev_lock);
  1216. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1217. mutex_unlock(&dev->dev_lock);
  1218. if (status)
  1219. goto mbx_err;
  1220. qp_attr->qp_state = get_ibqp_state(IB_QPS_INIT);
  1221. qp_attr->cur_qp_state = get_ibqp_state(IB_QPS_INIT);
  1222. qp_attr->path_mtu =
  1223. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1224. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1225. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1226. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1227. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1228. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1229. qp_attr->dest_qp_num =
  1230. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1231. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1232. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1233. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1234. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1235. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1236. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1237. qp_init_attr->cap = qp_attr->cap;
  1238. memcpy(&qp_attr->ah_attr.grh.dgid, &params.dgid[0],
  1239. sizeof(params.dgid));
  1240. qp_attr->ah_attr.grh.flow_label = params.rnt_rc_sl_fl &
  1241. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK;
  1242. qp_attr->ah_attr.grh.sgid_index = qp->sgid_idx;
  1243. qp_attr->ah_attr.grh.hop_limit = (params.hop_lmt_rq_psn &
  1244. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1245. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT;
  1246. qp_attr->ah_attr.grh.traffic_class = (params.tclass_sq_psn &
  1247. OCRDMA_QP_PARAMS_SQ_PSN_MASK) >>
  1248. OCRDMA_QP_PARAMS_TCLASS_SHIFT;
  1249. qp_attr->ah_attr.ah_flags = IB_AH_GRH;
  1250. qp_attr->ah_attr.port_num = 1;
  1251. qp_attr->ah_attr.sl = (params.rnt_rc_sl_fl &
  1252. OCRDMA_QP_PARAMS_SL_MASK) >>
  1253. OCRDMA_QP_PARAMS_SL_SHIFT;
  1254. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1255. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1256. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1257. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1258. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1259. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1260. qp_attr->retry_cnt =
  1261. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1262. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1263. qp_attr->min_rnr_timer = 0;
  1264. qp_attr->pkey_index = 0;
  1265. qp_attr->port_num = 1;
  1266. qp_attr->ah_attr.src_path_bits = 0;
  1267. qp_attr->ah_attr.static_rate = 0;
  1268. qp_attr->alt_pkey_index = 0;
  1269. qp_attr->alt_port_num = 0;
  1270. qp_attr->alt_timeout = 0;
  1271. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1272. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1273. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1274. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1275. qp_attr->max_dest_rd_atomic =
  1276. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1277. qp_attr->max_rd_atomic =
  1278. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1279. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1280. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1281. mbx_err:
  1282. return status;
  1283. }
  1284. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, int idx)
  1285. {
  1286. int i = idx / 32;
  1287. unsigned int mask = (1 << (idx % 32));
  1288. if (srq->idx_bit_fields[i] & mask)
  1289. srq->idx_bit_fields[i] &= ~mask;
  1290. else
  1291. srq->idx_bit_fields[i] |= mask;
  1292. }
  1293. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1294. {
  1295. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1296. }
  1297. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1298. {
  1299. return (qp->sq.tail == qp->sq.head);
  1300. }
  1301. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1302. {
  1303. return (qp->rq.tail == qp->rq.head);
  1304. }
  1305. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1306. {
  1307. return q->va + (q->head * q->entry_size);
  1308. }
  1309. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1310. u32 idx)
  1311. {
  1312. return q->va + (idx * q->entry_size);
  1313. }
  1314. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1315. {
  1316. q->head = (q->head + 1) & q->max_wqe_idx;
  1317. }
  1318. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1319. {
  1320. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1321. }
  1322. /* discard the cqe for a given QP */
  1323. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1324. {
  1325. unsigned long cq_flags;
  1326. unsigned long flags;
  1327. int discard_cnt = 0;
  1328. u32 cur_getp, stop_getp;
  1329. struct ocrdma_cqe *cqe;
  1330. u32 qpn = 0;
  1331. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1332. /* traverse through the CQEs in the hw CQ,
  1333. * find the matching CQE for a given qp,
  1334. * mark the matching one discarded by clearing qpn.
  1335. * ring the doorbell in the poll_cq() as
  1336. * we don't complete out of order cqe.
  1337. */
  1338. cur_getp = cq->getp;
  1339. /* find upto when do we reap the cq. */
  1340. stop_getp = cur_getp;
  1341. do {
  1342. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1343. break;
  1344. cqe = cq->va + cur_getp;
  1345. /* if (a) done reaping whole hw cq, or
  1346. * (b) qp_xq becomes empty.
  1347. * then exit
  1348. */
  1349. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1350. /* if previously discarded cqe found, skip that too. */
  1351. /* check for matching qp */
  1352. if (qpn == 0 || qpn != qp->id)
  1353. goto skip_cqe;
  1354. /* mark cqe discarded so that it is not picked up later
  1355. * in the poll_cq().
  1356. */
  1357. discard_cnt += 1;
  1358. cqe->cmn.qpn = 0;
  1359. if (is_cqe_for_sq(cqe)) {
  1360. ocrdma_hwq_inc_tail(&qp->sq);
  1361. } else {
  1362. if (qp->srq) {
  1363. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1364. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1365. ocrdma_srq_toggle_bit(qp->srq, cur_getp);
  1366. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1367. } else {
  1368. ocrdma_hwq_inc_tail(&qp->rq);
  1369. }
  1370. }
  1371. skip_cqe:
  1372. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1373. } while (cur_getp != stop_getp);
  1374. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1375. }
  1376. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1377. {
  1378. int found = false;
  1379. unsigned long flags;
  1380. struct ocrdma_dev *dev = qp->dev;
  1381. /* sync with any active CQ poll */
  1382. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1383. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1384. if (found)
  1385. list_del(&qp->sq_entry);
  1386. if (!qp->srq) {
  1387. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1388. if (found)
  1389. list_del(&qp->rq_entry);
  1390. }
  1391. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1392. }
  1393. int ocrdma_destroy_qp(struct ib_qp *ibqp)
  1394. {
  1395. int status;
  1396. struct ocrdma_pd *pd;
  1397. struct ocrdma_qp *qp;
  1398. struct ocrdma_dev *dev;
  1399. struct ib_qp_attr attrs;
  1400. int attr_mask = IB_QP_STATE;
  1401. unsigned long flags;
  1402. qp = get_ocrdma_qp(ibqp);
  1403. dev = qp->dev;
  1404. attrs.qp_state = IB_QPS_ERR;
  1405. pd = qp->pd;
  1406. /* change the QP state to ERROR */
  1407. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1408. /* ensure that CQEs for newly created QP (whose id may be same with
  1409. * one which just getting destroyed are same), dont get
  1410. * discarded until the old CQEs are discarded.
  1411. */
  1412. mutex_lock(&dev->dev_lock);
  1413. status = ocrdma_mbx_destroy_qp(dev, qp);
  1414. /*
  1415. * acquire CQ lock while destroy is in progress, in order to
  1416. * protect against proessing in-flight CQEs for this QP.
  1417. */
  1418. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1419. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1420. spin_lock(&qp->rq_cq->cq_lock);
  1421. ocrdma_del_qpn_map(dev, qp);
  1422. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq))
  1423. spin_unlock(&qp->rq_cq->cq_lock);
  1424. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1425. if (!pd->uctx) {
  1426. ocrdma_discard_cqes(qp, qp->sq_cq);
  1427. ocrdma_discard_cqes(qp, qp->rq_cq);
  1428. }
  1429. mutex_unlock(&dev->dev_lock);
  1430. if (pd->uctx) {
  1431. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1432. PAGE_ALIGN(qp->sq.len));
  1433. if (!qp->srq)
  1434. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1435. PAGE_ALIGN(qp->rq.len));
  1436. }
  1437. ocrdma_del_flush_qp(qp);
  1438. kfree(qp->wqe_wr_id_tbl);
  1439. kfree(qp->rqe_wr_id_tbl);
  1440. kfree(qp);
  1441. return status;
  1442. }
  1443. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1444. struct ib_udata *udata)
  1445. {
  1446. int status;
  1447. struct ocrdma_create_srq_uresp uresp;
  1448. memset(&uresp, 0, sizeof(uresp));
  1449. uresp.rq_dbid = srq->rq.dbid;
  1450. uresp.num_rq_pages = 1;
  1451. uresp.rq_page_addr[0] = srq->rq.pa;
  1452. uresp.rq_page_size = srq->rq.len;
  1453. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1454. (srq->pd->id * dev->nic_info.db_page_size);
  1455. uresp.db_page_size = dev->nic_info.db_page_size;
  1456. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1457. if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
  1458. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1459. uresp.db_shift = 24;
  1460. } else {
  1461. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1462. uresp.db_shift = 16;
  1463. }
  1464. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1465. if (status)
  1466. return status;
  1467. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1468. uresp.rq_page_size);
  1469. if (status)
  1470. return status;
  1471. return status;
  1472. }
  1473. struct ib_srq *ocrdma_create_srq(struct ib_pd *ibpd,
  1474. struct ib_srq_init_attr *init_attr,
  1475. struct ib_udata *udata)
  1476. {
  1477. int status = -ENOMEM;
  1478. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1479. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  1480. struct ocrdma_srq *srq;
  1481. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1482. return ERR_PTR(-EINVAL);
  1483. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1484. return ERR_PTR(-EINVAL);
  1485. srq = kzalloc(sizeof(*srq), GFP_KERNEL);
  1486. if (!srq)
  1487. return ERR_PTR(status);
  1488. spin_lock_init(&srq->q_lock);
  1489. srq->pd = pd;
  1490. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1491. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1492. if (status)
  1493. goto err;
  1494. if (udata == NULL) {
  1495. srq->rqe_wr_id_tbl = kzalloc(sizeof(u64) * srq->rq.max_cnt,
  1496. GFP_KERNEL);
  1497. if (srq->rqe_wr_id_tbl == NULL)
  1498. goto arm_err;
  1499. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1500. (srq->rq.max_cnt % 32 ? 1 : 0);
  1501. srq->idx_bit_fields =
  1502. kmalloc(srq->bit_fields_len * sizeof(u32), GFP_KERNEL);
  1503. if (srq->idx_bit_fields == NULL)
  1504. goto arm_err;
  1505. memset(srq->idx_bit_fields, 0xff,
  1506. srq->bit_fields_len * sizeof(u32));
  1507. }
  1508. if (init_attr->attr.srq_limit) {
  1509. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1510. if (status)
  1511. goto arm_err;
  1512. }
  1513. if (udata) {
  1514. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1515. if (status)
  1516. goto arm_err;
  1517. }
  1518. return &srq->ibsrq;
  1519. arm_err:
  1520. ocrdma_mbx_destroy_srq(dev, srq);
  1521. err:
  1522. kfree(srq->rqe_wr_id_tbl);
  1523. kfree(srq->idx_bit_fields);
  1524. kfree(srq);
  1525. return ERR_PTR(status);
  1526. }
  1527. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1528. struct ib_srq_attr *srq_attr,
  1529. enum ib_srq_attr_mask srq_attr_mask,
  1530. struct ib_udata *udata)
  1531. {
  1532. int status = 0;
  1533. struct ocrdma_srq *srq;
  1534. srq = get_ocrdma_srq(ibsrq);
  1535. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1536. status = -EINVAL;
  1537. else
  1538. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1539. return status;
  1540. }
  1541. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1542. {
  1543. int status;
  1544. struct ocrdma_srq *srq;
  1545. srq = get_ocrdma_srq(ibsrq);
  1546. status = ocrdma_mbx_query_srq(srq, srq_attr);
  1547. return status;
  1548. }
  1549. int ocrdma_destroy_srq(struct ib_srq *ibsrq)
  1550. {
  1551. int status;
  1552. struct ocrdma_srq *srq;
  1553. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1554. srq = get_ocrdma_srq(ibsrq);
  1555. status = ocrdma_mbx_destroy_srq(dev, srq);
  1556. if (srq->pd->uctx)
  1557. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1558. PAGE_ALIGN(srq->rq.len));
  1559. kfree(srq->idx_bit_fields);
  1560. kfree(srq->rqe_wr_id_tbl);
  1561. kfree(srq);
  1562. return status;
  1563. }
  1564. /* unprivileged verbs and their support functions. */
  1565. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1566. struct ocrdma_hdr_wqe *hdr,
  1567. struct ib_send_wr *wr)
  1568. {
  1569. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1570. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1571. struct ocrdma_ah *ah = get_ocrdma_ah(wr->wr.ud.ah);
  1572. ud_hdr->rsvd_dest_qpn = wr->wr.ud.remote_qpn;
  1573. if (qp->qp_type == IB_QPT_GSI)
  1574. ud_hdr->qkey = qp->qkey;
  1575. else
  1576. ud_hdr->qkey = wr->wr.ud.remote_qkey;
  1577. ud_hdr->rsvd_ahid = ah->id;
  1578. }
  1579. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1580. struct ocrdma_sge *sge, int num_sge,
  1581. struct ib_sge *sg_list)
  1582. {
  1583. int i;
  1584. for (i = 0; i < num_sge; i++) {
  1585. sge[i].lrkey = sg_list[i].lkey;
  1586. sge[i].addr_lo = sg_list[i].addr;
  1587. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1588. sge[i].len = sg_list[i].length;
  1589. hdr->total_len += sg_list[i].length;
  1590. }
  1591. if (num_sge == 0)
  1592. memset(sge, 0, sizeof(*sge));
  1593. }
  1594. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1595. {
  1596. uint32_t total_len = 0, i;
  1597. for (i = 0; i < num_sge; i++)
  1598. total_len += sg_list[i].length;
  1599. return total_len;
  1600. }
  1601. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1602. struct ocrdma_hdr_wqe *hdr,
  1603. struct ocrdma_sge *sge,
  1604. struct ib_send_wr *wr, u32 wqe_size)
  1605. {
  1606. int i;
  1607. char *dpp_addr;
  1608. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1609. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1610. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1611. pr_err("%s() supported_len=0x%x,\n"
  1612. " unspported len req=0x%x\n", __func__,
  1613. qp->max_inline_data, hdr->total_len);
  1614. return -EINVAL;
  1615. }
  1616. dpp_addr = (char *)sge;
  1617. for (i = 0; i < wr->num_sge; i++) {
  1618. memcpy(dpp_addr,
  1619. (void *)(unsigned long)wr->sg_list[i].addr,
  1620. wr->sg_list[i].length);
  1621. dpp_addr += wr->sg_list[i].length;
  1622. }
  1623. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1624. if (0 == hdr->total_len)
  1625. wqe_size += sizeof(struct ocrdma_sge);
  1626. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1627. } else {
  1628. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1629. if (wr->num_sge)
  1630. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1631. else
  1632. wqe_size += sizeof(struct ocrdma_sge);
  1633. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1634. }
  1635. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1636. return 0;
  1637. }
  1638. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1639. struct ib_send_wr *wr)
  1640. {
  1641. int status;
  1642. struct ocrdma_sge *sge;
  1643. u32 wqe_size = sizeof(*hdr);
  1644. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1645. ocrdma_build_ud_hdr(qp, hdr, wr);
  1646. sge = (struct ocrdma_sge *)(hdr + 2);
  1647. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1648. } else {
  1649. sge = (struct ocrdma_sge *)(hdr + 1);
  1650. }
  1651. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1652. return status;
  1653. }
  1654. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1655. struct ib_send_wr *wr)
  1656. {
  1657. int status;
  1658. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1659. struct ocrdma_sge *sge = ext_rw + 1;
  1660. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1661. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1662. if (status)
  1663. return status;
  1664. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1665. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1666. ext_rw->lrkey = wr->wr.rdma.rkey;
  1667. ext_rw->len = hdr->total_len;
  1668. return 0;
  1669. }
  1670. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1671. struct ib_send_wr *wr)
  1672. {
  1673. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1674. struct ocrdma_sge *sge = ext_rw + 1;
  1675. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1676. sizeof(struct ocrdma_hdr_wqe);
  1677. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1678. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1679. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1680. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1681. ext_rw->addr_lo = wr->wr.rdma.remote_addr;
  1682. ext_rw->addr_hi = upper_32_bits(wr->wr.rdma.remote_addr);
  1683. ext_rw->lrkey = wr->wr.rdma.rkey;
  1684. ext_rw->len = hdr->total_len;
  1685. }
  1686. static void build_frmr_pbes(struct ib_send_wr *wr, struct ocrdma_pbl *pbl_tbl,
  1687. struct ocrdma_hw_mr *hwmr)
  1688. {
  1689. int i;
  1690. u64 buf_addr = 0;
  1691. int num_pbes;
  1692. struct ocrdma_pbe *pbe;
  1693. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1694. num_pbes = 0;
  1695. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  1696. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  1697. /* number of pbes can be more for one OS buf, when
  1698. * buffers are of different sizes.
  1699. * split the ib_buf to one or more pbes.
  1700. */
  1701. buf_addr = wr->wr.fast_reg.page_list->page_list[i];
  1702. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1703. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1704. num_pbes += 1;
  1705. pbe++;
  1706. /* if the pbl is full storing the pbes,
  1707. * move to next pbl.
  1708. */
  1709. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  1710. pbl_tbl++;
  1711. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1712. }
  1713. }
  1714. return;
  1715. }
  1716. static int get_encoded_page_size(int pg_sz)
  1717. {
  1718. /* Max size is 256M 4096 << 16 */
  1719. int i = 0;
  1720. for (; i < 17; i++)
  1721. if (pg_sz == (4096 << i))
  1722. break;
  1723. return i;
  1724. }
  1725. static int ocrdma_build_fr(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1726. struct ib_send_wr *wr)
  1727. {
  1728. u64 fbo;
  1729. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1730. struct ocrdma_mr *mr;
  1731. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1732. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1733. if ((wr->wr.fast_reg.page_list_len >
  1734. qp->dev->attr.max_pages_per_frmr) ||
  1735. (wr->wr.fast_reg.length > 0xffffffffULL))
  1736. return -EINVAL;
  1737. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1738. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1739. if (wr->wr.fast_reg.page_list_len == 0)
  1740. BUG();
  1741. if (wr->wr.fast_reg.access_flags & IB_ACCESS_LOCAL_WRITE)
  1742. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1743. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_WRITE)
  1744. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1745. if (wr->wr.fast_reg.access_flags & IB_ACCESS_REMOTE_READ)
  1746. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1747. hdr->lkey = wr->wr.fast_reg.rkey;
  1748. hdr->total_len = wr->wr.fast_reg.length;
  1749. fbo = wr->wr.fast_reg.iova_start -
  1750. (wr->wr.fast_reg.page_list->page_list[0] & PAGE_MASK);
  1751. fast_reg->va_hi = upper_32_bits(wr->wr.fast_reg.iova_start);
  1752. fast_reg->va_lo = (u32) (wr->wr.fast_reg.iova_start & 0xffffffff);
  1753. fast_reg->fbo_hi = upper_32_bits(fbo);
  1754. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1755. fast_reg->num_sges = wr->wr.fast_reg.page_list_len;
  1756. fast_reg->size_sge =
  1757. get_encoded_page_size(1 << wr->wr.fast_reg.page_shift);
  1758. mr = (struct ocrdma_mr *) (unsigned long) qp->dev->stag_arr[(hdr->lkey >> 8) &
  1759. (OCRDMA_MAX_STAG - 1)];
  1760. build_frmr_pbes(wr, mr->hwmr.pbl_table, &mr->hwmr);
  1761. return 0;
  1762. }
  1763. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1764. {
  1765. u32 val = qp->sq.dbid | (1 << 16);
  1766. iowrite32(val, qp->sq_db);
  1767. }
  1768. int ocrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  1769. struct ib_send_wr **bad_wr)
  1770. {
  1771. int status = 0;
  1772. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1773. struct ocrdma_hdr_wqe *hdr;
  1774. unsigned long flags;
  1775. spin_lock_irqsave(&qp->q_lock, flags);
  1776. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1777. spin_unlock_irqrestore(&qp->q_lock, flags);
  1778. *bad_wr = wr;
  1779. return -EINVAL;
  1780. }
  1781. while (wr) {
  1782. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1783. wr->num_sge > qp->sq.max_sges) {
  1784. *bad_wr = wr;
  1785. status = -ENOMEM;
  1786. break;
  1787. }
  1788. hdr = ocrdma_hwq_head(&qp->sq);
  1789. hdr->cw = 0;
  1790. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1791. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1792. if (wr->send_flags & IB_SEND_FENCE)
  1793. hdr->cw |=
  1794. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1795. if (wr->send_flags & IB_SEND_SOLICITED)
  1796. hdr->cw |=
  1797. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1798. hdr->total_len = 0;
  1799. switch (wr->opcode) {
  1800. case IB_WR_SEND_WITH_IMM:
  1801. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1802. hdr->immdt = ntohl(wr->ex.imm_data);
  1803. case IB_WR_SEND:
  1804. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1805. ocrdma_build_send(qp, hdr, wr);
  1806. break;
  1807. case IB_WR_SEND_WITH_INV:
  1808. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1809. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1810. hdr->lkey = wr->ex.invalidate_rkey;
  1811. status = ocrdma_build_send(qp, hdr, wr);
  1812. break;
  1813. case IB_WR_RDMA_WRITE_WITH_IMM:
  1814. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1815. hdr->immdt = ntohl(wr->ex.imm_data);
  1816. case IB_WR_RDMA_WRITE:
  1817. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1818. status = ocrdma_build_write(qp, hdr, wr);
  1819. break;
  1820. case IB_WR_RDMA_READ_WITH_INV:
  1821. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1822. case IB_WR_RDMA_READ:
  1823. ocrdma_build_read(qp, hdr, wr);
  1824. break;
  1825. case IB_WR_LOCAL_INV:
  1826. hdr->cw |=
  1827. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1828. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1829. sizeof(struct ocrdma_sge)) /
  1830. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1831. hdr->lkey = wr->ex.invalidate_rkey;
  1832. break;
  1833. case IB_WR_FAST_REG_MR:
  1834. status = ocrdma_build_fr(qp, hdr, wr);
  1835. break;
  1836. default:
  1837. status = -EINVAL;
  1838. break;
  1839. }
  1840. if (status) {
  1841. *bad_wr = wr;
  1842. break;
  1843. }
  1844. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1845. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  1846. else
  1847. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  1848. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  1849. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  1850. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  1851. /* make sure wqe is written before adapter can access it */
  1852. wmb();
  1853. /* inform hw to start processing it */
  1854. ocrdma_ring_sq_db(qp);
  1855. /* update pointer, counter for next wr */
  1856. ocrdma_hwq_inc_head(&qp->sq);
  1857. wr = wr->next;
  1858. }
  1859. spin_unlock_irqrestore(&qp->q_lock, flags);
  1860. return status;
  1861. }
  1862. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  1863. {
  1864. u32 val = qp->rq.dbid | (1 << ocrdma_get_num_posted_shift(qp));
  1865. if (qp->state != OCRDMA_QPS_INIT)
  1866. iowrite32(val, qp->rq_db);
  1867. else
  1868. qp->db_cache++;
  1869. }
  1870. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe, struct ib_recv_wr *wr,
  1871. u16 tag)
  1872. {
  1873. u32 wqe_size = 0;
  1874. struct ocrdma_sge *sge;
  1875. if (wr->num_sge)
  1876. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  1877. else
  1878. wqe_size = sizeof(*sge) + sizeof(*rqe);
  1879. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  1880. OCRDMA_WQE_SIZE_SHIFT);
  1881. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1882. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1883. rqe->total_len = 0;
  1884. rqe->rsvd_tag = tag;
  1885. sge = (struct ocrdma_sge *)(rqe + 1);
  1886. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  1887. ocrdma_cpu_to_le32(rqe, wqe_size);
  1888. }
  1889. int ocrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  1890. struct ib_recv_wr **bad_wr)
  1891. {
  1892. int status = 0;
  1893. unsigned long flags;
  1894. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1895. struct ocrdma_hdr_wqe *rqe;
  1896. spin_lock_irqsave(&qp->q_lock, flags);
  1897. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  1898. spin_unlock_irqrestore(&qp->q_lock, flags);
  1899. *bad_wr = wr;
  1900. return -EINVAL;
  1901. }
  1902. while (wr) {
  1903. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  1904. wr->num_sge > qp->rq.max_sges) {
  1905. *bad_wr = wr;
  1906. status = -ENOMEM;
  1907. break;
  1908. }
  1909. rqe = ocrdma_hwq_head(&qp->rq);
  1910. ocrdma_build_rqe(rqe, wr, 0);
  1911. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  1912. /* make sure rqe is written before adapter can access it */
  1913. wmb();
  1914. /* inform hw to start processing it */
  1915. ocrdma_ring_rq_db(qp);
  1916. /* update pointer, counter for next wr */
  1917. ocrdma_hwq_inc_head(&qp->rq);
  1918. wr = wr->next;
  1919. }
  1920. spin_unlock_irqrestore(&qp->q_lock, flags);
  1921. return status;
  1922. }
  1923. /* cqe for srq's rqe can potentially arrive out of order.
  1924. * index gives the entry in the shadow table where to store
  1925. * the wr_id. tag/index is returned in cqe to reference back
  1926. * for a given rqe.
  1927. */
  1928. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  1929. {
  1930. int row = 0;
  1931. int indx = 0;
  1932. for (row = 0; row < srq->bit_fields_len; row++) {
  1933. if (srq->idx_bit_fields[row]) {
  1934. indx = ffs(srq->idx_bit_fields[row]);
  1935. indx = (row * 32) + (indx - 1);
  1936. if (indx >= srq->rq.max_cnt)
  1937. BUG();
  1938. ocrdma_srq_toggle_bit(srq, indx);
  1939. break;
  1940. }
  1941. }
  1942. if (row == srq->bit_fields_len)
  1943. BUG();
  1944. return indx;
  1945. }
  1946. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  1947. {
  1948. u32 val = srq->rq.dbid | (1 << 16);
  1949. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  1950. }
  1951. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  1952. struct ib_recv_wr **bad_wr)
  1953. {
  1954. int status = 0;
  1955. unsigned long flags;
  1956. struct ocrdma_srq *srq;
  1957. struct ocrdma_hdr_wqe *rqe;
  1958. u16 tag;
  1959. srq = get_ocrdma_srq(ibsrq);
  1960. spin_lock_irqsave(&srq->q_lock, flags);
  1961. while (wr) {
  1962. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  1963. wr->num_sge > srq->rq.max_sges) {
  1964. status = -ENOMEM;
  1965. *bad_wr = wr;
  1966. break;
  1967. }
  1968. tag = ocrdma_srq_get_idx(srq);
  1969. rqe = ocrdma_hwq_head(&srq->rq);
  1970. ocrdma_build_rqe(rqe, wr, tag);
  1971. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  1972. /* make sure rqe is written before adapter can perform DMA */
  1973. wmb();
  1974. /* inform hw to start processing it */
  1975. ocrdma_ring_srq_db(srq);
  1976. /* update pointer, counter for next wr */
  1977. ocrdma_hwq_inc_head(&srq->rq);
  1978. wr = wr->next;
  1979. }
  1980. spin_unlock_irqrestore(&srq->q_lock, flags);
  1981. return status;
  1982. }
  1983. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  1984. {
  1985. enum ib_wc_status ibwc_status;
  1986. switch (status) {
  1987. case OCRDMA_CQE_GENERAL_ERR:
  1988. ibwc_status = IB_WC_GENERAL_ERR;
  1989. break;
  1990. case OCRDMA_CQE_LOC_LEN_ERR:
  1991. ibwc_status = IB_WC_LOC_LEN_ERR;
  1992. break;
  1993. case OCRDMA_CQE_LOC_QP_OP_ERR:
  1994. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  1995. break;
  1996. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  1997. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  1998. break;
  1999. case OCRDMA_CQE_LOC_PROT_ERR:
  2000. ibwc_status = IB_WC_LOC_PROT_ERR;
  2001. break;
  2002. case OCRDMA_CQE_WR_FLUSH_ERR:
  2003. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2004. break;
  2005. case OCRDMA_CQE_MW_BIND_ERR:
  2006. ibwc_status = IB_WC_MW_BIND_ERR;
  2007. break;
  2008. case OCRDMA_CQE_BAD_RESP_ERR:
  2009. ibwc_status = IB_WC_BAD_RESP_ERR;
  2010. break;
  2011. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2012. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2013. break;
  2014. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2015. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2016. break;
  2017. case OCRDMA_CQE_REM_ACCESS_ERR:
  2018. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2019. break;
  2020. case OCRDMA_CQE_REM_OP_ERR:
  2021. ibwc_status = IB_WC_REM_OP_ERR;
  2022. break;
  2023. case OCRDMA_CQE_RETRY_EXC_ERR:
  2024. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2025. break;
  2026. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2027. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2028. break;
  2029. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2030. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2031. break;
  2032. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2033. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2034. break;
  2035. case OCRDMA_CQE_REM_ABORT_ERR:
  2036. ibwc_status = IB_WC_REM_ABORT_ERR;
  2037. break;
  2038. case OCRDMA_CQE_INV_EECN_ERR:
  2039. ibwc_status = IB_WC_INV_EECN_ERR;
  2040. break;
  2041. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2042. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2043. break;
  2044. case OCRDMA_CQE_FATAL_ERR:
  2045. ibwc_status = IB_WC_FATAL_ERR;
  2046. break;
  2047. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2048. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2049. break;
  2050. default:
  2051. ibwc_status = IB_WC_GENERAL_ERR;
  2052. break;
  2053. };
  2054. return ibwc_status;
  2055. }
  2056. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2057. u32 wqe_idx)
  2058. {
  2059. struct ocrdma_hdr_wqe *hdr;
  2060. struct ocrdma_sge *rw;
  2061. int opcode;
  2062. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2063. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2064. /* Undo the hdr->cw swap */
  2065. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2066. switch (opcode) {
  2067. case OCRDMA_WRITE:
  2068. ibwc->opcode = IB_WC_RDMA_WRITE;
  2069. break;
  2070. case OCRDMA_READ:
  2071. rw = (struct ocrdma_sge *)(hdr + 1);
  2072. ibwc->opcode = IB_WC_RDMA_READ;
  2073. ibwc->byte_len = rw->len;
  2074. break;
  2075. case OCRDMA_SEND:
  2076. ibwc->opcode = IB_WC_SEND;
  2077. break;
  2078. case OCRDMA_FR_MR:
  2079. ibwc->opcode = IB_WC_FAST_REG_MR;
  2080. break;
  2081. case OCRDMA_LKEY_INV:
  2082. ibwc->opcode = IB_WC_LOCAL_INV;
  2083. break;
  2084. default:
  2085. ibwc->status = IB_WC_GENERAL_ERR;
  2086. pr_err("%s() invalid opcode received = 0x%x\n",
  2087. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2088. break;
  2089. };
  2090. }
  2091. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2092. struct ocrdma_cqe *cqe)
  2093. {
  2094. if (is_cqe_for_sq(cqe)) {
  2095. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2096. cqe->flags_status_srcqpn) &
  2097. ~OCRDMA_CQE_STATUS_MASK);
  2098. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2099. cqe->flags_status_srcqpn) |
  2100. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2101. OCRDMA_CQE_STATUS_SHIFT));
  2102. } else {
  2103. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2104. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2105. cqe->flags_status_srcqpn) &
  2106. ~OCRDMA_CQE_UD_STATUS_MASK);
  2107. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2108. cqe->flags_status_srcqpn) |
  2109. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2110. OCRDMA_CQE_UD_STATUS_SHIFT));
  2111. } else {
  2112. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2113. cqe->flags_status_srcqpn) &
  2114. ~OCRDMA_CQE_STATUS_MASK);
  2115. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2116. cqe->flags_status_srcqpn) |
  2117. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2118. OCRDMA_CQE_STATUS_SHIFT));
  2119. }
  2120. }
  2121. }
  2122. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2123. struct ocrdma_qp *qp, int status)
  2124. {
  2125. bool expand = false;
  2126. ibwc->byte_len = 0;
  2127. ibwc->qp = &qp->ibqp;
  2128. ibwc->status = ocrdma_to_ibwc_err(status);
  2129. ocrdma_flush_qp(qp);
  2130. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2131. /* if wqe/rqe pending for which cqe needs to be returned,
  2132. * trigger inflating it.
  2133. */
  2134. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2135. expand = true;
  2136. ocrdma_set_cqe_status_flushed(qp, cqe);
  2137. }
  2138. return expand;
  2139. }
  2140. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2141. struct ocrdma_qp *qp, int status)
  2142. {
  2143. ibwc->opcode = IB_WC_RECV;
  2144. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2145. ocrdma_hwq_inc_tail(&qp->rq);
  2146. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2147. }
  2148. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2149. struct ocrdma_qp *qp, int status)
  2150. {
  2151. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2152. ocrdma_hwq_inc_tail(&qp->sq);
  2153. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2154. }
  2155. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2156. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2157. bool *polled, bool *stop)
  2158. {
  2159. bool expand;
  2160. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2161. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2162. /* when hw sq is empty, but rq is not empty, so we continue
  2163. * to keep the cqe in order to get the cq event again.
  2164. */
  2165. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2166. /* when cq for rq and sq is same, it is safe to return
  2167. * flush cqe for RQEs.
  2168. */
  2169. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2170. *polled = true;
  2171. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2172. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2173. } else {
  2174. /* stop processing further cqe as this cqe is used for
  2175. * triggering cq event on buddy cq of RQ.
  2176. * When QP is destroyed, this cqe will be removed
  2177. * from the cq's hardware q.
  2178. */
  2179. *polled = false;
  2180. *stop = true;
  2181. expand = false;
  2182. }
  2183. } else {
  2184. *polled = true;
  2185. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2186. }
  2187. return expand;
  2188. }
  2189. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2190. struct ocrdma_cqe *cqe,
  2191. struct ib_wc *ibwc, bool *polled)
  2192. {
  2193. bool expand = false;
  2194. int tail = qp->sq.tail;
  2195. u32 wqe_idx;
  2196. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2197. *polled = false; /* WC cannot be consumed yet */
  2198. } else {
  2199. ibwc->status = IB_WC_SUCCESS;
  2200. ibwc->wc_flags = 0;
  2201. ibwc->qp = &qp->ibqp;
  2202. ocrdma_update_wc(qp, ibwc, tail);
  2203. *polled = true;
  2204. }
  2205. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2206. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2207. if (tail != wqe_idx)
  2208. expand = true; /* Coalesced CQE can't be consumed yet */
  2209. ocrdma_hwq_inc_tail(&qp->sq);
  2210. return expand;
  2211. }
  2212. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2213. struct ib_wc *ibwc, bool *polled, bool *stop)
  2214. {
  2215. int status;
  2216. bool expand;
  2217. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2218. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2219. if (status == OCRDMA_CQE_SUCCESS)
  2220. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2221. else
  2222. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2223. return expand;
  2224. }
  2225. static int ocrdma_update_ud_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe)
  2226. {
  2227. int status;
  2228. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2229. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2230. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2231. OCRDMA_CQE_SRCQP_MASK;
  2232. ibwc->pkey_index = le32_to_cpu(cqe->ud.rxlen_pkey) &
  2233. OCRDMA_CQE_PKEY_MASK;
  2234. ibwc->wc_flags = IB_WC_GRH;
  2235. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2236. OCRDMA_CQE_UD_XFER_LEN_SHIFT);
  2237. return status;
  2238. }
  2239. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2240. struct ocrdma_cqe *cqe,
  2241. struct ocrdma_qp *qp)
  2242. {
  2243. unsigned long flags;
  2244. struct ocrdma_srq *srq;
  2245. u32 wqe_idx;
  2246. srq = get_ocrdma_srq(qp->ibqp.srq);
  2247. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2248. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2249. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2250. spin_lock_irqsave(&srq->q_lock, flags);
  2251. ocrdma_srq_toggle_bit(srq, wqe_idx);
  2252. spin_unlock_irqrestore(&srq->q_lock, flags);
  2253. ocrdma_hwq_inc_tail(&srq->rq);
  2254. }
  2255. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2256. struct ib_wc *ibwc, bool *polled, bool *stop,
  2257. int status)
  2258. {
  2259. bool expand;
  2260. /* when hw_rq is empty, but wq is not empty, so continue
  2261. * to keep the cqe to get the cq event again.
  2262. */
  2263. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2264. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2265. *polled = true;
  2266. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2267. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2268. } else {
  2269. *polled = false;
  2270. *stop = true;
  2271. expand = false;
  2272. }
  2273. } else {
  2274. *polled = true;
  2275. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2276. }
  2277. return expand;
  2278. }
  2279. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2280. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2281. {
  2282. ibwc->opcode = IB_WC_RECV;
  2283. ibwc->qp = &qp->ibqp;
  2284. ibwc->status = IB_WC_SUCCESS;
  2285. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2286. ocrdma_update_ud_rcqe(ibwc, cqe);
  2287. else
  2288. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2289. if (is_cqe_imm(cqe)) {
  2290. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2291. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2292. } else if (is_cqe_wr_imm(cqe)) {
  2293. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2294. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2295. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2296. } else if (is_cqe_invalidated(cqe)) {
  2297. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2298. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2299. }
  2300. if (qp->ibqp.srq) {
  2301. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2302. } else {
  2303. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2304. ocrdma_hwq_inc_tail(&qp->rq);
  2305. }
  2306. }
  2307. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2308. struct ib_wc *ibwc, bool *polled, bool *stop)
  2309. {
  2310. int status;
  2311. bool expand = false;
  2312. ibwc->wc_flags = 0;
  2313. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2314. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2315. OCRDMA_CQE_UD_STATUS_MASK) >>
  2316. OCRDMA_CQE_UD_STATUS_SHIFT;
  2317. } else {
  2318. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2319. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2320. }
  2321. if (status == OCRDMA_CQE_SUCCESS) {
  2322. *polled = true;
  2323. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2324. } else {
  2325. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2326. status);
  2327. }
  2328. return expand;
  2329. }
  2330. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2331. u16 cur_getp)
  2332. {
  2333. if (cq->phase_change) {
  2334. if (cur_getp == 0)
  2335. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2336. } else {
  2337. /* clear valid bit */
  2338. cqe->flags_status_srcqpn = 0;
  2339. }
  2340. }
  2341. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2342. struct ib_wc *ibwc)
  2343. {
  2344. u16 qpn = 0;
  2345. int i = 0;
  2346. bool expand = false;
  2347. int polled_hw_cqes = 0;
  2348. struct ocrdma_qp *qp = NULL;
  2349. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2350. struct ocrdma_cqe *cqe;
  2351. u16 cur_getp; bool polled = false; bool stop = false;
  2352. cur_getp = cq->getp;
  2353. while (num_entries) {
  2354. cqe = cq->va + cur_getp;
  2355. /* check whether valid cqe or not */
  2356. if (!is_cqe_valid(cq, cqe))
  2357. break;
  2358. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2359. /* ignore discarded cqe */
  2360. if (qpn == 0)
  2361. goto skip_cqe;
  2362. qp = dev->qp_tbl[qpn];
  2363. BUG_ON(qp == NULL);
  2364. if (is_cqe_for_sq(cqe)) {
  2365. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2366. &stop);
  2367. } else {
  2368. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2369. &stop);
  2370. }
  2371. if (expand)
  2372. goto expand_cqe;
  2373. if (stop)
  2374. goto stop_cqe;
  2375. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2376. cqe->cmn.qpn = 0;
  2377. skip_cqe:
  2378. polled_hw_cqes += 1;
  2379. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2380. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2381. expand_cqe:
  2382. if (polled) {
  2383. num_entries -= 1;
  2384. i += 1;
  2385. ibwc = ibwc + 1;
  2386. polled = false;
  2387. }
  2388. }
  2389. stop_cqe:
  2390. cq->getp = cur_getp;
  2391. if (polled_hw_cqes || expand || stop) {
  2392. ocrdma_ring_cq_db(dev, cq->id, cq->armed, cq->solicited,
  2393. polled_hw_cqes);
  2394. }
  2395. return i;
  2396. }
  2397. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2398. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2399. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2400. {
  2401. int err_cqes = 0;
  2402. while (num_entries) {
  2403. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2404. break;
  2405. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2406. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2407. ocrdma_hwq_inc_tail(&qp->sq);
  2408. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2409. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2410. ocrdma_hwq_inc_tail(&qp->rq);
  2411. } else {
  2412. return err_cqes;
  2413. }
  2414. ibwc->byte_len = 0;
  2415. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2416. ibwc = ibwc + 1;
  2417. err_cqes += 1;
  2418. num_entries -= 1;
  2419. }
  2420. return err_cqes;
  2421. }
  2422. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2423. {
  2424. int cqes_to_poll = num_entries;
  2425. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2426. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2427. int num_os_cqe = 0, err_cqes = 0;
  2428. struct ocrdma_qp *qp;
  2429. unsigned long flags;
  2430. /* poll cqes from adapter CQ */
  2431. spin_lock_irqsave(&cq->cq_lock, flags);
  2432. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2433. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2434. cqes_to_poll -= num_os_cqe;
  2435. if (cqes_to_poll) {
  2436. wc = wc + num_os_cqe;
  2437. /* adapter returns single error cqe when qp moves to
  2438. * error state. So insert error cqes with wc_status as
  2439. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2440. * respectively which uses this CQ.
  2441. */
  2442. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2443. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2444. if (cqes_to_poll == 0)
  2445. break;
  2446. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2447. cqes_to_poll -= err_cqes;
  2448. num_os_cqe += err_cqes;
  2449. wc = wc + err_cqes;
  2450. }
  2451. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2452. }
  2453. return num_os_cqe;
  2454. }
  2455. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2456. {
  2457. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2458. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2459. u16 cq_id;
  2460. u16 cur_getp;
  2461. struct ocrdma_cqe *cqe;
  2462. unsigned long flags;
  2463. cq_id = cq->id;
  2464. spin_lock_irqsave(&cq->cq_lock, flags);
  2465. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2466. cq->armed = true;
  2467. if (cq_flags & IB_CQ_SOLICITED)
  2468. cq->solicited = true;
  2469. cur_getp = cq->getp;
  2470. cqe = cq->va + cur_getp;
  2471. /* check whether any valid cqe exist or not, if not then safe to
  2472. * arm. If cqe is not yet consumed, then let it get consumed and then
  2473. * we arm it to avoid false interrupts.
  2474. */
  2475. if (!is_cqe_valid(cq, cqe) || cq->arm_needed) {
  2476. cq->arm_needed = false;
  2477. ocrdma_ring_cq_db(dev, cq_id, cq->armed, cq->solicited, 0);
  2478. }
  2479. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2480. return 0;
  2481. }
  2482. struct ib_mr *ocrdma_alloc_frmr(struct ib_pd *ibpd, int max_page_list_len)
  2483. {
  2484. int status;
  2485. struct ocrdma_mr *mr;
  2486. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2487. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2488. if (max_page_list_len > dev->attr.max_pages_per_frmr)
  2489. return ERR_PTR(-EINVAL);
  2490. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2491. if (!mr)
  2492. return ERR_PTR(-ENOMEM);
  2493. status = ocrdma_get_pbl_info(dev, mr, max_page_list_len);
  2494. if (status)
  2495. goto pbl_err;
  2496. mr->hwmr.fr_mr = 1;
  2497. mr->hwmr.remote_rd = 0;
  2498. mr->hwmr.remote_wr = 0;
  2499. mr->hwmr.local_rd = 0;
  2500. mr->hwmr.local_wr = 0;
  2501. mr->hwmr.mw_bind = 0;
  2502. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2503. if (status)
  2504. goto pbl_err;
  2505. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2506. if (status)
  2507. goto mbx_err;
  2508. mr->ibmr.rkey = mr->hwmr.lkey;
  2509. mr->ibmr.lkey = mr->hwmr.lkey;
  2510. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] = (unsigned long) mr;
  2511. return &mr->ibmr;
  2512. mbx_err:
  2513. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2514. pbl_err:
  2515. kfree(mr);
  2516. return ERR_PTR(-ENOMEM);
  2517. }
  2518. struct ib_fast_reg_page_list *ocrdma_alloc_frmr_page_list(struct ib_device
  2519. *ibdev,
  2520. int page_list_len)
  2521. {
  2522. struct ib_fast_reg_page_list *frmr_list;
  2523. int size;
  2524. size = sizeof(*frmr_list) + (page_list_len * sizeof(u64));
  2525. frmr_list = kzalloc(size, GFP_KERNEL);
  2526. if (!frmr_list)
  2527. return ERR_PTR(-ENOMEM);
  2528. frmr_list->page_list = (u64 *)(frmr_list + 1);
  2529. return frmr_list;
  2530. }
  2531. void ocrdma_free_frmr_page_list(struct ib_fast_reg_page_list *page_list)
  2532. {
  2533. kfree(page_list);
  2534. }
  2535. #define MAX_KERNEL_PBE_SIZE 65536
  2536. static inline int count_kernel_pbes(struct ib_phys_buf *buf_list,
  2537. int buf_cnt, u32 *pbe_size)
  2538. {
  2539. u64 total_size = 0;
  2540. u64 buf_size = 0;
  2541. int i;
  2542. *pbe_size = roundup(buf_list[0].size, PAGE_SIZE);
  2543. *pbe_size = roundup_pow_of_two(*pbe_size);
  2544. /* find the smallest PBE size that we can have */
  2545. for (i = 0; i < buf_cnt; i++) {
  2546. /* first addr may not be page aligned, so ignore checking */
  2547. if ((i != 0) && ((buf_list[i].addr & ~PAGE_MASK) ||
  2548. (buf_list[i].size & ~PAGE_MASK))) {
  2549. return 0;
  2550. }
  2551. /* if configured PBE size is greater then the chosen one,
  2552. * reduce the PBE size.
  2553. */
  2554. buf_size = roundup(buf_list[i].size, PAGE_SIZE);
  2555. /* pbe_size has to be even multiple of 4K 1,2,4,8...*/
  2556. buf_size = roundup_pow_of_two(buf_size);
  2557. if (*pbe_size > buf_size)
  2558. *pbe_size = buf_size;
  2559. total_size += buf_size;
  2560. }
  2561. *pbe_size = *pbe_size > MAX_KERNEL_PBE_SIZE ?
  2562. (MAX_KERNEL_PBE_SIZE) : (*pbe_size);
  2563. /* num_pbes = total_size / (*pbe_size); this is implemented below. */
  2564. return total_size >> ilog2(*pbe_size);
  2565. }
  2566. static void build_kernel_pbes(struct ib_phys_buf *buf_list, int ib_buf_cnt,
  2567. u32 pbe_size, struct ocrdma_pbl *pbl_tbl,
  2568. struct ocrdma_hw_mr *hwmr)
  2569. {
  2570. int i;
  2571. int idx;
  2572. int pbes_per_buf = 0;
  2573. u64 buf_addr = 0;
  2574. int num_pbes;
  2575. struct ocrdma_pbe *pbe;
  2576. int total_num_pbes = 0;
  2577. if (!hwmr->num_pbes)
  2578. return;
  2579. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2580. num_pbes = 0;
  2581. /* go through the OS phy regions & fill hw pbe entries into pbls. */
  2582. for (i = 0; i < ib_buf_cnt; i++) {
  2583. buf_addr = buf_list[i].addr;
  2584. pbes_per_buf =
  2585. roundup_pow_of_two(roundup(buf_list[i].size, PAGE_SIZE)) /
  2586. pbe_size;
  2587. hwmr->len += buf_list[i].size;
  2588. /* number of pbes can be more for one OS buf, when
  2589. * buffers are of different sizes.
  2590. * split the ib_buf to one or more pbes.
  2591. */
  2592. for (idx = 0; idx < pbes_per_buf; idx++) {
  2593. /* we program always page aligned addresses,
  2594. * first unaligned address is taken care by fbo.
  2595. */
  2596. if (i == 0) {
  2597. /* for non zero fbo, assign the
  2598. * start of the page.
  2599. */
  2600. pbe->pa_lo =
  2601. cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  2602. pbe->pa_hi =
  2603. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2604. } else {
  2605. pbe->pa_lo =
  2606. cpu_to_le32((u32) (buf_addr & 0xffffffff));
  2607. pbe->pa_hi =
  2608. cpu_to_le32((u32) upper_32_bits(buf_addr));
  2609. }
  2610. buf_addr += pbe_size;
  2611. num_pbes += 1;
  2612. total_num_pbes += 1;
  2613. pbe++;
  2614. if (total_num_pbes == hwmr->num_pbes)
  2615. goto mr_tbl_done;
  2616. /* if the pbl is full storing the pbes,
  2617. * move to next pbl.
  2618. */
  2619. if (num_pbes == (hwmr->pbl_size/sizeof(u64))) {
  2620. pbl_tbl++;
  2621. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  2622. num_pbes = 0;
  2623. }
  2624. }
  2625. }
  2626. mr_tbl_done:
  2627. return;
  2628. }
  2629. struct ib_mr *ocrdma_reg_kernel_mr(struct ib_pd *ibpd,
  2630. struct ib_phys_buf *buf_list,
  2631. int buf_cnt, int acc, u64 *iova_start)
  2632. {
  2633. int status = -ENOMEM;
  2634. struct ocrdma_mr *mr;
  2635. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2636. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2637. u32 num_pbes;
  2638. u32 pbe_size = 0;
  2639. if ((acc & IB_ACCESS_REMOTE_WRITE) && !(acc & IB_ACCESS_LOCAL_WRITE))
  2640. return ERR_PTR(-EINVAL);
  2641. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  2642. if (!mr)
  2643. return ERR_PTR(status);
  2644. num_pbes = count_kernel_pbes(buf_list, buf_cnt, &pbe_size);
  2645. if (num_pbes == 0) {
  2646. status = -EINVAL;
  2647. goto pbl_err;
  2648. }
  2649. status = ocrdma_get_pbl_info(dev, mr, num_pbes);
  2650. if (status)
  2651. goto pbl_err;
  2652. mr->hwmr.pbe_size = pbe_size;
  2653. mr->hwmr.fbo = *iova_start - (buf_list[0].addr & PAGE_MASK);
  2654. mr->hwmr.va = *iova_start;
  2655. mr->hwmr.local_rd = 1;
  2656. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  2657. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  2658. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  2659. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  2660. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  2661. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2662. if (status)
  2663. goto pbl_err;
  2664. build_kernel_pbes(buf_list, buf_cnt, pbe_size, mr->hwmr.pbl_table,
  2665. &mr->hwmr);
  2666. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  2667. if (status)
  2668. goto mbx_err;
  2669. mr->ibmr.lkey = mr->hwmr.lkey;
  2670. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  2671. mr->ibmr.rkey = mr->hwmr.lkey;
  2672. return &mr->ibmr;
  2673. mbx_err:
  2674. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2675. pbl_err:
  2676. kfree(mr);
  2677. return ERR_PTR(status);
  2678. }