cq.c 24 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include "iw_cxgb4.h"
  33. static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
  34. struct c4iw_dev_ucontext *uctx)
  35. {
  36. struct fw_ri_res_wr *res_wr;
  37. struct fw_ri_res *res;
  38. int wr_len;
  39. struct c4iw_wr_wait wr_wait;
  40. struct sk_buff *skb;
  41. int ret;
  42. wr_len = sizeof *res_wr + sizeof *res;
  43. skb = alloc_skb(wr_len, GFP_KERNEL);
  44. if (!skb)
  45. return -ENOMEM;
  46. set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
  47. res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
  48. memset(res_wr, 0, wr_len);
  49. res_wr->op_nres = cpu_to_be32(
  50. FW_WR_OP(FW_RI_RES_WR) |
  51. V_FW_RI_RES_WR_NRES(1) |
  52. FW_WR_COMPL(1));
  53. res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
  54. res_wr->cookie = (unsigned long) &wr_wait;
  55. res = res_wr->res;
  56. res->u.cq.restype = FW_RI_RES_TYPE_CQ;
  57. res->u.cq.op = FW_RI_RES_OP_RESET;
  58. res->u.cq.iqid = cpu_to_be32(cq->cqid);
  59. c4iw_init_wr_wait(&wr_wait);
  60. ret = c4iw_ofld_send(rdev, skb);
  61. if (!ret) {
  62. ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
  63. }
  64. kfree(cq->sw_queue);
  65. dma_free_coherent(&(rdev->lldi.pdev->dev),
  66. cq->memsize, cq->queue,
  67. dma_unmap_addr(cq, mapping));
  68. c4iw_put_cqid(rdev, cq->cqid, uctx);
  69. return ret;
  70. }
  71. static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
  72. struct c4iw_dev_ucontext *uctx)
  73. {
  74. struct fw_ri_res_wr *res_wr;
  75. struct fw_ri_res *res;
  76. int wr_len;
  77. int user = (uctx != &rdev->uctx);
  78. struct c4iw_wr_wait wr_wait;
  79. int ret;
  80. struct sk_buff *skb;
  81. cq->cqid = c4iw_get_cqid(rdev, uctx);
  82. if (!cq->cqid) {
  83. ret = -ENOMEM;
  84. goto err1;
  85. }
  86. if (!user) {
  87. cq->sw_queue = kzalloc(cq->memsize, GFP_KERNEL);
  88. if (!cq->sw_queue) {
  89. ret = -ENOMEM;
  90. goto err2;
  91. }
  92. }
  93. cq->queue = dma_alloc_coherent(&rdev->lldi.pdev->dev, cq->memsize,
  94. &cq->dma_addr, GFP_KERNEL);
  95. if (!cq->queue) {
  96. ret = -ENOMEM;
  97. goto err3;
  98. }
  99. dma_unmap_addr_set(cq, mapping, cq->dma_addr);
  100. memset(cq->queue, 0, cq->memsize);
  101. /* build fw_ri_res_wr */
  102. wr_len = sizeof *res_wr + sizeof *res;
  103. skb = alloc_skb(wr_len, GFP_KERNEL);
  104. if (!skb) {
  105. ret = -ENOMEM;
  106. goto err4;
  107. }
  108. set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
  109. res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
  110. memset(res_wr, 0, wr_len);
  111. res_wr->op_nres = cpu_to_be32(
  112. FW_WR_OP(FW_RI_RES_WR) |
  113. V_FW_RI_RES_WR_NRES(1) |
  114. FW_WR_COMPL(1));
  115. res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
  116. res_wr->cookie = (unsigned long) &wr_wait;
  117. res = res_wr->res;
  118. res->u.cq.restype = FW_RI_RES_TYPE_CQ;
  119. res->u.cq.op = FW_RI_RES_OP_WRITE;
  120. res->u.cq.iqid = cpu_to_be32(cq->cqid);
  121. res->u.cq.iqandst_to_iqandstindex = cpu_to_be32(
  122. V_FW_RI_RES_WR_IQANUS(0) |
  123. V_FW_RI_RES_WR_IQANUD(1) |
  124. F_FW_RI_RES_WR_IQANDST |
  125. V_FW_RI_RES_WR_IQANDSTINDEX(*rdev->lldi.rxq_ids));
  126. res->u.cq.iqdroprss_to_iqesize = cpu_to_be16(
  127. F_FW_RI_RES_WR_IQDROPRSS |
  128. V_FW_RI_RES_WR_IQPCIECH(2) |
  129. V_FW_RI_RES_WR_IQINTCNTTHRESH(0) |
  130. F_FW_RI_RES_WR_IQO |
  131. V_FW_RI_RES_WR_IQESIZE(1));
  132. res->u.cq.iqsize = cpu_to_be16(cq->size);
  133. res->u.cq.iqaddr = cpu_to_be64(cq->dma_addr);
  134. c4iw_init_wr_wait(&wr_wait);
  135. ret = c4iw_ofld_send(rdev, skb);
  136. if (ret)
  137. goto err4;
  138. PDBG("%s wait_event wr_wait %p\n", __func__, &wr_wait);
  139. ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__);
  140. if (ret)
  141. goto err4;
  142. cq->gen = 1;
  143. cq->gts = rdev->lldi.gts_reg;
  144. cq->rdev = rdev;
  145. if (user) {
  146. cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
  147. (cq->cqid << rdev->cqshift);
  148. cq->ugts &= PAGE_MASK;
  149. }
  150. return 0;
  151. err4:
  152. dma_free_coherent(&rdev->lldi.pdev->dev, cq->memsize, cq->queue,
  153. dma_unmap_addr(cq, mapping));
  154. err3:
  155. kfree(cq->sw_queue);
  156. err2:
  157. c4iw_put_cqid(rdev, cq->cqid, uctx);
  158. err1:
  159. return ret;
  160. }
  161. static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq)
  162. {
  163. struct t4_cqe cqe;
  164. PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
  165. wq, cq, cq->sw_cidx, cq->sw_pidx);
  166. memset(&cqe, 0, sizeof(cqe));
  167. cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
  168. V_CQE_OPCODE(FW_RI_SEND) |
  169. V_CQE_TYPE(0) |
  170. V_CQE_SWCQE(1) |
  171. V_CQE_QPID(wq->sq.qid));
  172. cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
  173. cq->sw_queue[cq->sw_pidx] = cqe;
  174. t4_swcq_produce(cq);
  175. }
  176. int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
  177. {
  178. int flushed = 0;
  179. int in_use = wq->rq.in_use - count;
  180. BUG_ON(in_use < 0);
  181. PDBG("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__,
  182. wq, cq, wq->rq.in_use, count);
  183. while (in_use--) {
  184. insert_recv_cqe(wq, cq);
  185. flushed++;
  186. }
  187. return flushed;
  188. }
  189. static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
  190. struct t4_swsqe *swcqe)
  191. {
  192. struct t4_cqe cqe;
  193. PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
  194. wq, cq, cq->sw_cidx, cq->sw_pidx);
  195. memset(&cqe, 0, sizeof(cqe));
  196. cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
  197. V_CQE_OPCODE(swcqe->opcode) |
  198. V_CQE_TYPE(1) |
  199. V_CQE_SWCQE(1) |
  200. V_CQE_QPID(wq->sq.qid));
  201. CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
  202. cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
  203. cq->sw_queue[cq->sw_pidx] = cqe;
  204. t4_swcq_produce(cq);
  205. }
  206. static void advance_oldest_read(struct t4_wq *wq);
  207. int c4iw_flush_sq(struct c4iw_qp *qhp)
  208. {
  209. int flushed = 0;
  210. struct t4_wq *wq = &qhp->wq;
  211. struct c4iw_cq *chp = to_c4iw_cq(qhp->ibqp.send_cq);
  212. struct t4_cq *cq = &chp->cq;
  213. int idx;
  214. struct t4_swsqe *swsqe;
  215. int error = (qhp->attr.state != C4IW_QP_STATE_CLOSING &&
  216. qhp->attr.state != C4IW_QP_STATE_IDLE);
  217. if (wq->sq.flush_cidx == -1)
  218. wq->sq.flush_cidx = wq->sq.cidx;
  219. idx = wq->sq.flush_cidx;
  220. BUG_ON(idx >= wq->sq.size);
  221. while (idx != wq->sq.pidx) {
  222. if (error) {
  223. swsqe = &wq->sq.sw_sq[idx];
  224. BUG_ON(swsqe->flushed);
  225. swsqe->flushed = 1;
  226. insert_sq_cqe(wq, cq, swsqe);
  227. if (wq->sq.oldest_read == swsqe) {
  228. BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
  229. advance_oldest_read(wq);
  230. }
  231. flushed++;
  232. } else {
  233. t4_sq_consume(wq);
  234. }
  235. if (++idx == wq->sq.size)
  236. idx = 0;
  237. }
  238. wq->sq.flush_cidx += flushed;
  239. if (wq->sq.flush_cidx >= wq->sq.size)
  240. wq->sq.flush_cidx -= wq->sq.size;
  241. return flushed;
  242. }
  243. static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
  244. {
  245. struct t4_swsqe *swsqe;
  246. int cidx;
  247. if (wq->sq.flush_cidx == -1)
  248. wq->sq.flush_cidx = wq->sq.cidx;
  249. cidx = wq->sq.flush_cidx;
  250. BUG_ON(cidx > wq->sq.size);
  251. while (cidx != wq->sq.pidx) {
  252. swsqe = &wq->sq.sw_sq[cidx];
  253. if (!swsqe->signaled) {
  254. if (++cidx == wq->sq.size)
  255. cidx = 0;
  256. } else if (swsqe->complete) {
  257. BUG_ON(swsqe->flushed);
  258. /*
  259. * Insert this completed cqe into the swcq.
  260. */
  261. PDBG("%s moving cqe into swcq sq idx %u cq idx %u\n",
  262. __func__, cidx, cq->sw_pidx);
  263. swsqe->cqe.header |= htonl(V_CQE_SWCQE(1));
  264. cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
  265. t4_swcq_produce(cq);
  266. swsqe->flushed = 1;
  267. if (++cidx == wq->sq.size)
  268. cidx = 0;
  269. wq->sq.flush_cidx = cidx;
  270. } else
  271. break;
  272. }
  273. }
  274. static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
  275. struct t4_cqe *read_cqe)
  276. {
  277. read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
  278. read_cqe->len = htonl(wq->sq.oldest_read->read_len);
  279. read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(hw_cqe)) |
  280. V_CQE_SWCQE(SW_CQE(hw_cqe)) |
  281. V_CQE_OPCODE(FW_RI_READ_REQ) |
  282. V_CQE_TYPE(1));
  283. read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
  284. }
  285. static void advance_oldest_read(struct t4_wq *wq)
  286. {
  287. u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
  288. if (rptr == wq->sq.size)
  289. rptr = 0;
  290. while (rptr != wq->sq.pidx) {
  291. wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
  292. if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
  293. return;
  294. if (++rptr == wq->sq.size)
  295. rptr = 0;
  296. }
  297. wq->sq.oldest_read = NULL;
  298. }
  299. /*
  300. * Move all CQEs from the HWCQ into the SWCQ.
  301. * Deal with out-of-order and/or completions that complete
  302. * prior unsignalled WRs.
  303. */
  304. void c4iw_flush_hw_cq(struct c4iw_cq *chp)
  305. {
  306. struct t4_cqe *hw_cqe, *swcqe, read_cqe;
  307. struct c4iw_qp *qhp;
  308. struct t4_swsqe *swsqe;
  309. int ret;
  310. PDBG("%s cqid 0x%x\n", __func__, chp->cq.cqid);
  311. ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
  312. /*
  313. * This logic is similar to poll_cq(), but not quite the same
  314. * unfortunately. Need to move pertinent HW CQEs to the SW CQ but
  315. * also do any translation magic that poll_cq() normally does.
  316. */
  317. while (!ret) {
  318. qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
  319. /*
  320. * drop CQEs with no associated QP
  321. */
  322. if (qhp == NULL)
  323. goto next_cqe;
  324. if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
  325. goto next_cqe;
  326. if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
  327. /*
  328. * drop peer2peer RTR reads.
  329. */
  330. if (CQE_WRID_STAG(hw_cqe) == 1)
  331. goto next_cqe;
  332. /*
  333. * Eat completions for unsignaled read WRs.
  334. */
  335. if (!qhp->wq.sq.oldest_read->signaled) {
  336. advance_oldest_read(&qhp->wq);
  337. goto next_cqe;
  338. }
  339. /*
  340. * Don't write to the HWCQ, create a new read req CQE
  341. * in local memory and move it into the swcq.
  342. */
  343. create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
  344. hw_cqe = &read_cqe;
  345. advance_oldest_read(&qhp->wq);
  346. }
  347. /* if its a SQ completion, then do the magic to move all the
  348. * unsignaled and now in-order completions into the swcq.
  349. */
  350. if (SQ_TYPE(hw_cqe)) {
  351. swsqe = &qhp->wq.sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
  352. swsqe->cqe = *hw_cqe;
  353. swsqe->complete = 1;
  354. flush_completed_wrs(&qhp->wq, &chp->cq);
  355. } else {
  356. swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
  357. *swcqe = *hw_cqe;
  358. swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
  359. t4_swcq_produce(&chp->cq);
  360. }
  361. next_cqe:
  362. t4_hwcq_consume(&chp->cq);
  363. ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
  364. }
  365. }
  366. static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
  367. {
  368. if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
  369. return 0;
  370. if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
  371. return 0;
  372. if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
  373. return 0;
  374. if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
  375. return 0;
  376. return 1;
  377. }
  378. void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
  379. {
  380. struct t4_cqe *cqe;
  381. u32 ptr;
  382. *count = 0;
  383. PDBG("%s count zero %d\n", __func__, *count);
  384. ptr = cq->sw_cidx;
  385. while (ptr != cq->sw_pidx) {
  386. cqe = &cq->sw_queue[ptr];
  387. if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
  388. (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
  389. (*count)++;
  390. if (++ptr == cq->size)
  391. ptr = 0;
  392. }
  393. PDBG("%s cq %p count %d\n", __func__, cq, *count);
  394. }
  395. /*
  396. * poll_cq
  397. *
  398. * Caller must:
  399. * check the validity of the first CQE,
  400. * supply the wq assicated with the qpid.
  401. *
  402. * credit: cq credit to return to sge.
  403. * cqe_flushed: 1 iff the CQE is flushed.
  404. * cqe: copy of the polled CQE.
  405. *
  406. * return value:
  407. * 0 CQE returned ok.
  408. * -EAGAIN CQE skipped, try again.
  409. * -EOVERFLOW CQ overflow detected.
  410. */
  411. static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
  412. u8 *cqe_flushed, u64 *cookie, u32 *credit)
  413. {
  414. int ret = 0;
  415. struct t4_cqe *hw_cqe, read_cqe;
  416. *cqe_flushed = 0;
  417. *credit = 0;
  418. ret = t4_next_cqe(cq, &hw_cqe);
  419. if (ret)
  420. return ret;
  421. PDBG("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x"
  422. " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
  423. __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
  424. CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
  425. CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
  426. CQE_WRID_LOW(hw_cqe));
  427. /*
  428. * skip cqe's not affiliated with a QP.
  429. */
  430. if (wq == NULL) {
  431. ret = -EAGAIN;
  432. goto skip_cqe;
  433. }
  434. /*
  435. * skip hw cqe's if the wq is flushed.
  436. */
  437. if (wq->flushed && !SW_CQE(hw_cqe)) {
  438. ret = -EAGAIN;
  439. goto skip_cqe;
  440. }
  441. /*
  442. * skip TERMINATE cqes...
  443. */
  444. if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
  445. ret = -EAGAIN;
  446. goto skip_cqe;
  447. }
  448. /*
  449. * Gotta tweak READ completions:
  450. * 1) the cqe doesn't contain the sq_wptr from the wr.
  451. * 2) opcode not reflected from the wr.
  452. * 3) read_len not reflected from the wr.
  453. * 4) cq_type is RQ_TYPE not SQ_TYPE.
  454. */
  455. if (RQ_TYPE(hw_cqe) && (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP)) {
  456. /*
  457. * If this is an unsolicited read response, then the read
  458. * was generated by the kernel driver as part of peer-2-peer
  459. * connection setup. So ignore the completion.
  460. */
  461. if (CQE_WRID_STAG(hw_cqe) == 1) {
  462. if (CQE_STATUS(hw_cqe))
  463. t4_set_wq_in_error(wq);
  464. ret = -EAGAIN;
  465. goto skip_cqe;
  466. }
  467. /*
  468. * Eat completions for unsignaled read WRs.
  469. */
  470. if (!wq->sq.oldest_read->signaled) {
  471. advance_oldest_read(wq);
  472. ret = -EAGAIN;
  473. goto skip_cqe;
  474. }
  475. /*
  476. * Don't write to the HWCQ, so create a new read req CQE
  477. * in local memory.
  478. */
  479. create_read_req_cqe(wq, hw_cqe, &read_cqe);
  480. hw_cqe = &read_cqe;
  481. advance_oldest_read(wq);
  482. }
  483. if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
  484. *cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
  485. t4_set_wq_in_error(wq);
  486. }
  487. /*
  488. * RECV completion.
  489. */
  490. if (RQ_TYPE(hw_cqe)) {
  491. /*
  492. * HW only validates 4 bits of MSN. So we must validate that
  493. * the MSN in the SEND is the next expected MSN. If its not,
  494. * then we complete this with T4_ERR_MSN and mark the wq in
  495. * error.
  496. */
  497. if (t4_rq_empty(wq)) {
  498. t4_set_wq_in_error(wq);
  499. ret = -EAGAIN;
  500. goto skip_cqe;
  501. }
  502. if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
  503. t4_set_wq_in_error(wq);
  504. hw_cqe->header |= htonl(V_CQE_STATUS(T4_ERR_MSN));
  505. goto proc_cqe;
  506. }
  507. goto proc_cqe;
  508. }
  509. /*
  510. * If we get here its a send completion.
  511. *
  512. * Handle out of order completion. These get stuffed
  513. * in the SW SQ. Then the SW SQ is walked to move any
  514. * now in-order completions into the SW CQ. This handles
  515. * 2 cases:
  516. * 1) reaping unsignaled WRs when the first subsequent
  517. * signaled WR is completed.
  518. * 2) out of order read completions.
  519. */
  520. if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
  521. struct t4_swsqe *swsqe;
  522. PDBG("%s out of order completion going in sw_sq at idx %u\n",
  523. __func__, CQE_WRID_SQ_IDX(hw_cqe));
  524. swsqe = &wq->sq.sw_sq[CQE_WRID_SQ_IDX(hw_cqe)];
  525. swsqe->cqe = *hw_cqe;
  526. swsqe->complete = 1;
  527. ret = -EAGAIN;
  528. goto flush_wq;
  529. }
  530. proc_cqe:
  531. *cqe = *hw_cqe;
  532. /*
  533. * Reap the associated WR(s) that are freed up with this
  534. * completion.
  535. */
  536. if (SQ_TYPE(hw_cqe)) {
  537. int idx = CQE_WRID_SQ_IDX(hw_cqe);
  538. BUG_ON(idx > wq->sq.size);
  539. /*
  540. * Account for any unsignaled completions completed by
  541. * this signaled completion. In this case, cidx points
  542. * to the first unsignaled one, and idx points to the
  543. * signaled one. So adjust in_use based on this delta.
  544. * if this is not completing any unsigned wrs, then the
  545. * delta will be 0. Handle wrapping also!
  546. */
  547. if (idx < wq->sq.cidx)
  548. wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
  549. else
  550. wq->sq.in_use -= idx - wq->sq.cidx;
  551. BUG_ON(wq->sq.in_use < 0 && wq->sq.in_use < wq->sq.size);
  552. wq->sq.cidx = (uint16_t)idx;
  553. PDBG("%s completing sq idx %u\n", __func__, wq->sq.cidx);
  554. *cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
  555. t4_sq_consume(wq);
  556. } else {
  557. PDBG("%s completing rq idx %u\n", __func__, wq->rq.cidx);
  558. *cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
  559. BUG_ON(t4_rq_empty(wq));
  560. t4_rq_consume(wq);
  561. goto skip_cqe;
  562. }
  563. flush_wq:
  564. /*
  565. * Flush any completed cqes that are now in-order.
  566. */
  567. flush_completed_wrs(wq, cq);
  568. skip_cqe:
  569. if (SW_CQE(hw_cqe)) {
  570. PDBG("%s cq %p cqid 0x%x skip sw cqe cidx %u\n",
  571. __func__, cq, cq->cqid, cq->sw_cidx);
  572. t4_swcq_consume(cq);
  573. } else {
  574. PDBG("%s cq %p cqid 0x%x skip hw cqe cidx %u\n",
  575. __func__, cq, cq->cqid, cq->cidx);
  576. t4_hwcq_consume(cq);
  577. }
  578. return ret;
  579. }
  580. /*
  581. * Get one cq entry from c4iw and map it to openib.
  582. *
  583. * Returns:
  584. * 0 cqe returned
  585. * -ENODATA EMPTY;
  586. * -EAGAIN caller must try again
  587. * any other -errno fatal error
  588. */
  589. static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ib_wc *wc)
  590. {
  591. struct c4iw_qp *qhp = NULL;
  592. struct t4_cqe cqe = {0, 0}, *rd_cqe;
  593. struct t4_wq *wq;
  594. u32 credit = 0;
  595. u8 cqe_flushed;
  596. u64 cookie = 0;
  597. int ret;
  598. ret = t4_next_cqe(&chp->cq, &rd_cqe);
  599. if (ret)
  600. return ret;
  601. qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
  602. if (!qhp)
  603. wq = NULL;
  604. else {
  605. spin_lock(&qhp->lock);
  606. wq = &(qhp->wq);
  607. }
  608. ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit);
  609. if (ret)
  610. goto out;
  611. wc->wr_id = cookie;
  612. wc->qp = &qhp->ibqp;
  613. wc->vendor_err = CQE_STATUS(&cqe);
  614. wc->wc_flags = 0;
  615. PDBG("%s qpid 0x%x type %d opcode %d status 0x%x len %u wrid hi 0x%x "
  616. "lo 0x%x cookie 0x%llx\n", __func__, CQE_QPID(&cqe),
  617. CQE_TYPE(&cqe), CQE_OPCODE(&cqe), CQE_STATUS(&cqe), CQE_LEN(&cqe),
  618. CQE_WRID_HI(&cqe), CQE_WRID_LOW(&cqe), (unsigned long long)cookie);
  619. if (CQE_TYPE(&cqe) == 0) {
  620. if (!CQE_STATUS(&cqe))
  621. wc->byte_len = CQE_LEN(&cqe);
  622. else
  623. wc->byte_len = 0;
  624. wc->opcode = IB_WC_RECV;
  625. if (CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_INV ||
  626. CQE_OPCODE(&cqe) == FW_RI_SEND_WITH_SE_INV) {
  627. wc->ex.invalidate_rkey = CQE_WRID_STAG(&cqe);
  628. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  629. }
  630. } else {
  631. switch (CQE_OPCODE(&cqe)) {
  632. case FW_RI_RDMA_WRITE:
  633. wc->opcode = IB_WC_RDMA_WRITE;
  634. break;
  635. case FW_RI_READ_REQ:
  636. wc->opcode = IB_WC_RDMA_READ;
  637. wc->byte_len = CQE_LEN(&cqe);
  638. break;
  639. case FW_RI_SEND_WITH_INV:
  640. case FW_RI_SEND_WITH_SE_INV:
  641. wc->opcode = IB_WC_SEND;
  642. wc->wc_flags |= IB_WC_WITH_INVALIDATE;
  643. break;
  644. case FW_RI_SEND:
  645. case FW_RI_SEND_WITH_SE:
  646. wc->opcode = IB_WC_SEND;
  647. break;
  648. case FW_RI_BIND_MW:
  649. wc->opcode = IB_WC_BIND_MW;
  650. break;
  651. case FW_RI_LOCAL_INV:
  652. wc->opcode = IB_WC_LOCAL_INV;
  653. break;
  654. case FW_RI_FAST_REGISTER:
  655. wc->opcode = IB_WC_FAST_REG_MR;
  656. break;
  657. default:
  658. printk(KERN_ERR MOD "Unexpected opcode %d "
  659. "in the CQE received for QPID=0x%0x\n",
  660. CQE_OPCODE(&cqe), CQE_QPID(&cqe));
  661. ret = -EINVAL;
  662. goto out;
  663. }
  664. }
  665. if (cqe_flushed)
  666. wc->status = IB_WC_WR_FLUSH_ERR;
  667. else {
  668. switch (CQE_STATUS(&cqe)) {
  669. case T4_ERR_SUCCESS:
  670. wc->status = IB_WC_SUCCESS;
  671. break;
  672. case T4_ERR_STAG:
  673. wc->status = IB_WC_LOC_ACCESS_ERR;
  674. break;
  675. case T4_ERR_PDID:
  676. wc->status = IB_WC_LOC_PROT_ERR;
  677. break;
  678. case T4_ERR_QPID:
  679. case T4_ERR_ACCESS:
  680. wc->status = IB_WC_LOC_ACCESS_ERR;
  681. break;
  682. case T4_ERR_WRAP:
  683. wc->status = IB_WC_GENERAL_ERR;
  684. break;
  685. case T4_ERR_BOUND:
  686. wc->status = IB_WC_LOC_LEN_ERR;
  687. break;
  688. case T4_ERR_INVALIDATE_SHARED_MR:
  689. case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
  690. wc->status = IB_WC_MW_BIND_ERR;
  691. break;
  692. case T4_ERR_CRC:
  693. case T4_ERR_MARKER:
  694. case T4_ERR_PDU_LEN_ERR:
  695. case T4_ERR_OUT_OF_RQE:
  696. case T4_ERR_DDP_VERSION:
  697. case T4_ERR_RDMA_VERSION:
  698. case T4_ERR_DDP_QUEUE_NUM:
  699. case T4_ERR_MSN:
  700. case T4_ERR_TBIT:
  701. case T4_ERR_MO:
  702. case T4_ERR_MSN_RANGE:
  703. case T4_ERR_IRD_OVERFLOW:
  704. case T4_ERR_OPCODE:
  705. case T4_ERR_INTERNAL_ERR:
  706. wc->status = IB_WC_FATAL_ERR;
  707. break;
  708. case T4_ERR_SWFLUSH:
  709. wc->status = IB_WC_WR_FLUSH_ERR;
  710. break;
  711. default:
  712. printk(KERN_ERR MOD
  713. "Unexpected cqe_status 0x%x for QPID=0x%0x\n",
  714. CQE_STATUS(&cqe), CQE_QPID(&cqe));
  715. ret = -EINVAL;
  716. }
  717. }
  718. out:
  719. if (wq)
  720. spin_unlock(&qhp->lock);
  721. return ret;
  722. }
  723. int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  724. {
  725. struct c4iw_cq *chp;
  726. unsigned long flags;
  727. int npolled;
  728. int err = 0;
  729. chp = to_c4iw_cq(ibcq);
  730. spin_lock_irqsave(&chp->lock, flags);
  731. for (npolled = 0; npolled < num_entries; ++npolled) {
  732. do {
  733. err = c4iw_poll_cq_one(chp, wc + npolled);
  734. } while (err == -EAGAIN);
  735. if (err)
  736. break;
  737. }
  738. spin_unlock_irqrestore(&chp->lock, flags);
  739. return !err || err == -ENODATA ? npolled : err;
  740. }
  741. int c4iw_destroy_cq(struct ib_cq *ib_cq)
  742. {
  743. struct c4iw_cq *chp;
  744. struct c4iw_ucontext *ucontext;
  745. PDBG("%s ib_cq %p\n", __func__, ib_cq);
  746. chp = to_c4iw_cq(ib_cq);
  747. remove_handle(chp->rhp, &chp->rhp->cqidr, chp->cq.cqid);
  748. atomic_dec(&chp->refcnt);
  749. wait_event(chp->wait, !atomic_read(&chp->refcnt));
  750. ucontext = ib_cq->uobject ? to_c4iw_ucontext(ib_cq->uobject->context)
  751. : NULL;
  752. destroy_cq(&chp->rhp->rdev, &chp->cq,
  753. ucontext ? &ucontext->uctx : &chp->cq.rdev->uctx);
  754. kfree(chp);
  755. return 0;
  756. }
  757. struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
  758. int vector, struct ib_ucontext *ib_context,
  759. struct ib_udata *udata)
  760. {
  761. struct c4iw_dev *rhp;
  762. struct c4iw_cq *chp;
  763. struct c4iw_create_cq_resp uresp;
  764. struct c4iw_ucontext *ucontext = NULL;
  765. int ret;
  766. size_t memsize, hwentries;
  767. struct c4iw_mm_entry *mm, *mm2;
  768. PDBG("%s ib_dev %p entries %d\n", __func__, ibdev, entries);
  769. rhp = to_c4iw_dev(ibdev);
  770. chp = kzalloc(sizeof(*chp), GFP_KERNEL);
  771. if (!chp)
  772. return ERR_PTR(-ENOMEM);
  773. if (ib_context)
  774. ucontext = to_c4iw_ucontext(ib_context);
  775. /* account for the status page. */
  776. entries++;
  777. /* IQ needs one extra entry to differentiate full vs empty. */
  778. entries++;
  779. /*
  780. * entries must be multiple of 16 for HW.
  781. */
  782. entries = roundup(entries, 16);
  783. /*
  784. * Make actual HW queue 2x to avoid cdix_inc overflows.
  785. */
  786. hwentries = entries * 2;
  787. /*
  788. * Make HW queue at least 64 entries so GTS updates aren't too
  789. * frequent.
  790. */
  791. if (hwentries < 64)
  792. hwentries = 64;
  793. memsize = hwentries * sizeof *chp->cq.queue;
  794. /*
  795. * memsize must be a multiple of the page size if its a user cq.
  796. */
  797. if (ucontext) {
  798. memsize = roundup(memsize, PAGE_SIZE);
  799. hwentries = memsize / sizeof *chp->cq.queue;
  800. while (hwentries > T4_MAX_IQ_SIZE) {
  801. memsize -= PAGE_SIZE;
  802. hwentries = memsize / sizeof *chp->cq.queue;
  803. }
  804. }
  805. chp->cq.size = hwentries;
  806. chp->cq.memsize = memsize;
  807. ret = create_cq(&rhp->rdev, &chp->cq,
  808. ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
  809. if (ret)
  810. goto err1;
  811. chp->rhp = rhp;
  812. chp->cq.size--; /* status page */
  813. chp->ibcq.cqe = entries - 2;
  814. spin_lock_init(&chp->lock);
  815. spin_lock_init(&chp->comp_handler_lock);
  816. atomic_set(&chp->refcnt, 1);
  817. init_waitqueue_head(&chp->wait);
  818. ret = insert_handle(rhp, &rhp->cqidr, chp, chp->cq.cqid);
  819. if (ret)
  820. goto err2;
  821. if (ucontext) {
  822. mm = kmalloc(sizeof *mm, GFP_KERNEL);
  823. if (!mm)
  824. goto err3;
  825. mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
  826. if (!mm2)
  827. goto err4;
  828. uresp.qid_mask = rhp->rdev.cqmask;
  829. uresp.cqid = chp->cq.cqid;
  830. uresp.size = chp->cq.size;
  831. uresp.memsize = chp->cq.memsize;
  832. spin_lock(&ucontext->mmap_lock);
  833. uresp.key = ucontext->key;
  834. ucontext->key += PAGE_SIZE;
  835. uresp.gts_key = ucontext->key;
  836. ucontext->key += PAGE_SIZE;
  837. spin_unlock(&ucontext->mmap_lock);
  838. ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
  839. if (ret)
  840. goto err5;
  841. mm->key = uresp.key;
  842. mm->addr = virt_to_phys(chp->cq.queue);
  843. mm->len = chp->cq.memsize;
  844. insert_mmap(ucontext, mm);
  845. mm2->key = uresp.gts_key;
  846. mm2->addr = chp->cq.ugts;
  847. mm2->len = PAGE_SIZE;
  848. insert_mmap(ucontext, mm2);
  849. }
  850. PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",
  851. __func__, chp->cq.cqid, chp, chp->cq.size,
  852. chp->cq.memsize,
  853. (unsigned long long) chp->cq.dma_addr);
  854. return &chp->ibcq;
  855. err5:
  856. kfree(mm2);
  857. err4:
  858. kfree(mm);
  859. err3:
  860. remove_handle(rhp, &rhp->cqidr, chp->cq.cqid);
  861. err2:
  862. destroy_cq(&chp->rhp->rdev, &chp->cq,
  863. ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
  864. err1:
  865. kfree(chp);
  866. return ERR_PTR(ret);
  867. }
  868. int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata)
  869. {
  870. return -ENOSYS;
  871. }
  872. int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
  873. {
  874. struct c4iw_cq *chp;
  875. int ret;
  876. unsigned long flag;
  877. chp = to_c4iw_cq(ibcq);
  878. spin_lock_irqsave(&chp->lock, flag);
  879. ret = t4_arm_cq(&chp->cq,
  880. (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED);
  881. spin_unlock_irqrestore(&chp->lock, flag);
  882. if (ret && !(flags & IB_CQ_REPORT_MISSED_EVENTS))
  883. ret = 0;
  884. return ret;
  885. }