intel_panel.c 20 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/moduleparam.h>
  32. #include "intel_drv.h"
  33. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34. void
  35. intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  36. struct drm_display_mode *adjusted_mode)
  37. {
  38. drm_mode_copy(adjusted_mode, fixed_mode);
  39. drm_mode_set_crtcinfo(adjusted_mode, 0);
  40. }
  41. /* adjusted_mode has been preset to be the panel's fixed mode */
  42. void
  43. intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  44. struct intel_crtc_config *pipe_config,
  45. int fitting_mode)
  46. {
  47. struct drm_display_mode *mode, *adjusted_mode;
  48. int x, y, width, height;
  49. mode = &pipe_config->requested_mode;
  50. adjusted_mode = &pipe_config->adjusted_mode;
  51. x = y = width = height = 0;
  52. /* Native modes don't need fitting */
  53. if (adjusted_mode->hdisplay == mode->hdisplay &&
  54. adjusted_mode->vdisplay == mode->vdisplay)
  55. goto done;
  56. switch (fitting_mode) {
  57. case DRM_MODE_SCALE_CENTER:
  58. width = mode->hdisplay;
  59. height = mode->vdisplay;
  60. x = (adjusted_mode->hdisplay - width + 1)/2;
  61. y = (adjusted_mode->vdisplay - height + 1)/2;
  62. break;
  63. case DRM_MODE_SCALE_ASPECT:
  64. /* Scale but preserve the aspect ratio */
  65. {
  66. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  67. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  68. if (scaled_width > scaled_height) { /* pillar */
  69. width = scaled_height / mode->vdisplay;
  70. if (width & 1)
  71. width++;
  72. x = (adjusted_mode->hdisplay - width + 1) / 2;
  73. y = 0;
  74. height = adjusted_mode->vdisplay;
  75. } else if (scaled_width < scaled_height) { /* letter */
  76. height = scaled_width / mode->hdisplay;
  77. if (height & 1)
  78. height++;
  79. y = (adjusted_mode->vdisplay - height + 1) / 2;
  80. x = 0;
  81. width = adjusted_mode->hdisplay;
  82. } else {
  83. x = y = 0;
  84. width = adjusted_mode->hdisplay;
  85. height = adjusted_mode->vdisplay;
  86. }
  87. }
  88. break;
  89. case DRM_MODE_SCALE_FULLSCREEN:
  90. x = y = 0;
  91. width = adjusted_mode->hdisplay;
  92. height = adjusted_mode->vdisplay;
  93. break;
  94. default:
  95. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  96. return;
  97. }
  98. done:
  99. pipe_config->pch_pfit.pos = (x << 16) | y;
  100. pipe_config->pch_pfit.size = (width << 16) | height;
  101. }
  102. static void
  103. centre_horizontally(struct drm_display_mode *mode,
  104. int width)
  105. {
  106. u32 border, sync_pos, blank_width, sync_width;
  107. /* keep the hsync and hblank widths constant */
  108. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  109. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  110. sync_pos = (blank_width - sync_width + 1) / 2;
  111. border = (mode->hdisplay - width + 1) / 2;
  112. border += border & 1; /* make the border even */
  113. mode->crtc_hdisplay = width;
  114. mode->crtc_hblank_start = width + border;
  115. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  116. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  117. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  118. }
  119. static void
  120. centre_vertically(struct drm_display_mode *mode,
  121. int height)
  122. {
  123. u32 border, sync_pos, blank_width, sync_width;
  124. /* keep the vsync and vblank widths constant */
  125. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  126. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  127. sync_pos = (blank_width - sync_width + 1) / 2;
  128. border = (mode->vdisplay - height + 1) / 2;
  129. mode->crtc_vdisplay = height;
  130. mode->crtc_vblank_start = height + border;
  131. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  132. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  133. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  134. }
  135. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  136. {
  137. /*
  138. * Floating point operation is not supported. So the FACTOR
  139. * is defined, which can avoid the floating point computation
  140. * when calculating the panel ratio.
  141. */
  142. #define ACCURACY 12
  143. #define FACTOR (1 << ACCURACY)
  144. u32 ratio = source * FACTOR / target;
  145. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  146. }
  147. void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
  148. struct intel_crtc_config *pipe_config,
  149. int fitting_mode)
  150. {
  151. struct drm_device *dev = intel_crtc->base.dev;
  152. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  153. struct drm_display_mode *mode, *adjusted_mode;
  154. mode = &pipe_config->requested_mode;
  155. adjusted_mode = &pipe_config->adjusted_mode;
  156. /* Native modes don't need fitting */
  157. if (adjusted_mode->hdisplay == mode->hdisplay &&
  158. adjusted_mode->vdisplay == mode->vdisplay)
  159. goto out;
  160. switch (fitting_mode) {
  161. case DRM_MODE_SCALE_CENTER:
  162. /*
  163. * For centered modes, we have to calculate border widths &
  164. * heights and modify the values programmed into the CRTC.
  165. */
  166. centre_horizontally(adjusted_mode, mode->hdisplay);
  167. centre_vertically(adjusted_mode, mode->vdisplay);
  168. border = LVDS_BORDER_ENABLE;
  169. break;
  170. case DRM_MODE_SCALE_ASPECT:
  171. /* Scale but preserve the aspect ratio */
  172. if (INTEL_INFO(dev)->gen >= 4) {
  173. u32 scaled_width = adjusted_mode->hdisplay *
  174. mode->vdisplay;
  175. u32 scaled_height = mode->hdisplay *
  176. adjusted_mode->vdisplay;
  177. /* 965+ is easy, it does everything in hw */
  178. if (scaled_width > scaled_height)
  179. pfit_control |= PFIT_ENABLE |
  180. PFIT_SCALING_PILLAR;
  181. else if (scaled_width < scaled_height)
  182. pfit_control |= PFIT_ENABLE |
  183. PFIT_SCALING_LETTER;
  184. else if (adjusted_mode->hdisplay != mode->hdisplay)
  185. pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
  186. } else {
  187. u32 scaled_width = adjusted_mode->hdisplay *
  188. mode->vdisplay;
  189. u32 scaled_height = mode->hdisplay *
  190. adjusted_mode->vdisplay;
  191. /*
  192. * For earlier chips we have to calculate the scaling
  193. * ratio by hand and program it into the
  194. * PFIT_PGM_RATIO register
  195. */
  196. if (scaled_width > scaled_height) { /* pillar */
  197. centre_horizontally(adjusted_mode,
  198. scaled_height /
  199. mode->vdisplay);
  200. border = LVDS_BORDER_ENABLE;
  201. if (mode->vdisplay != adjusted_mode->vdisplay) {
  202. u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
  203. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  204. bits << PFIT_VERT_SCALE_SHIFT);
  205. pfit_control |= (PFIT_ENABLE |
  206. VERT_INTERP_BILINEAR |
  207. HORIZ_INTERP_BILINEAR);
  208. }
  209. } else if (scaled_width < scaled_height) { /* letter */
  210. centre_vertically(adjusted_mode,
  211. scaled_width /
  212. mode->hdisplay);
  213. border = LVDS_BORDER_ENABLE;
  214. if (mode->hdisplay != adjusted_mode->hdisplay) {
  215. u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
  216. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  217. bits << PFIT_VERT_SCALE_SHIFT);
  218. pfit_control |= (PFIT_ENABLE |
  219. VERT_INTERP_BILINEAR |
  220. HORIZ_INTERP_BILINEAR);
  221. }
  222. } else {
  223. /* Aspects match, Let hw scale both directions */
  224. pfit_control |= (PFIT_ENABLE |
  225. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  226. VERT_INTERP_BILINEAR |
  227. HORIZ_INTERP_BILINEAR);
  228. }
  229. }
  230. break;
  231. case DRM_MODE_SCALE_FULLSCREEN:
  232. /*
  233. * Full scaling, even if it changes the aspect ratio.
  234. * Fortunately this is all done for us in hw.
  235. */
  236. if (mode->vdisplay != adjusted_mode->vdisplay ||
  237. mode->hdisplay != adjusted_mode->hdisplay) {
  238. pfit_control |= PFIT_ENABLE;
  239. if (INTEL_INFO(dev)->gen >= 4)
  240. pfit_control |= PFIT_SCALING_AUTO;
  241. else
  242. pfit_control |= (VERT_AUTO_SCALE |
  243. VERT_INTERP_BILINEAR |
  244. HORIZ_AUTO_SCALE |
  245. HORIZ_INTERP_BILINEAR);
  246. }
  247. break;
  248. default:
  249. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  250. return;
  251. }
  252. /* 965+ wants fuzzy fitting */
  253. /* FIXME: handle multiple panels by failing gracefully */
  254. if (INTEL_INFO(dev)->gen >= 4)
  255. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  256. PFIT_FILTER_FUZZY);
  257. out:
  258. if ((pfit_control & PFIT_ENABLE) == 0) {
  259. pfit_control = 0;
  260. pfit_pgm_ratios = 0;
  261. }
  262. /* Make sure pre-965 set dither correctly for 18bpp panels. */
  263. if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
  264. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  265. pipe_config->gmch_pfit.control = pfit_control;
  266. pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
  267. pipe_config->gmch_pfit.lvds_border_bits = border;
  268. }
  269. static int is_backlight_combination_mode(struct drm_device *dev)
  270. {
  271. struct drm_i915_private *dev_priv = dev->dev_private;
  272. if (INTEL_INFO(dev)->gen >= 4)
  273. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  274. if (IS_GEN2(dev))
  275. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  276. return 0;
  277. }
  278. /* XXX: query mode clock or hardware clock and program max PWM appropriately
  279. * when it's 0.
  280. */
  281. static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
  282. {
  283. struct drm_i915_private *dev_priv = dev->dev_private;
  284. u32 val;
  285. WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
  286. /* Restore the CTL value if it lost, e.g. GPU reset */
  287. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  288. val = I915_READ(BLC_PWM_PCH_CTL2);
  289. if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
  290. dev_priv->regfile.saveBLC_PWM_CTL2 = val;
  291. } else if (val == 0) {
  292. val = dev_priv->regfile.saveBLC_PWM_CTL2;
  293. I915_WRITE(BLC_PWM_PCH_CTL2, val);
  294. }
  295. } else {
  296. val = I915_READ(BLC_PWM_CTL);
  297. if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
  298. dev_priv->regfile.saveBLC_PWM_CTL = val;
  299. if (INTEL_INFO(dev)->gen >= 4)
  300. dev_priv->regfile.saveBLC_PWM_CTL2 =
  301. I915_READ(BLC_PWM_CTL2);
  302. } else if (val == 0) {
  303. val = dev_priv->regfile.saveBLC_PWM_CTL;
  304. I915_WRITE(BLC_PWM_CTL, val);
  305. if (INTEL_INFO(dev)->gen >= 4)
  306. I915_WRITE(BLC_PWM_CTL2,
  307. dev_priv->regfile.saveBLC_PWM_CTL2);
  308. }
  309. }
  310. return val;
  311. }
  312. static u32 intel_panel_get_max_backlight(struct drm_device *dev)
  313. {
  314. u32 max;
  315. max = i915_read_blc_pwm_ctl(dev);
  316. if (HAS_PCH_SPLIT(dev)) {
  317. max >>= 16;
  318. } else {
  319. if (INTEL_INFO(dev)->gen < 4)
  320. max >>= 17;
  321. else
  322. max >>= 16;
  323. if (is_backlight_combination_mode(dev))
  324. max *= 0xff;
  325. }
  326. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  327. return max;
  328. }
  329. static int i915_panel_invert_brightness;
  330. MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
  331. "(-1 force normal, 0 machine defaults, 1 force inversion), please "
  332. "report PCI device ID, subsystem vendor and subsystem device ID "
  333. "to dri-devel@lists.freedesktop.org, if your machine needs it. "
  334. "It will then be included in an upcoming module version.");
  335. module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
  336. static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
  337. {
  338. struct drm_i915_private *dev_priv = dev->dev_private;
  339. if (i915_panel_invert_brightness < 0)
  340. return val;
  341. if (i915_panel_invert_brightness > 0 ||
  342. dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
  343. u32 max = intel_panel_get_max_backlight(dev);
  344. if (max)
  345. return max - val;
  346. }
  347. return val;
  348. }
  349. static u32 intel_panel_get_backlight(struct drm_device *dev)
  350. {
  351. struct drm_i915_private *dev_priv = dev->dev_private;
  352. u32 val;
  353. unsigned long flags;
  354. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  355. if (HAS_PCH_SPLIT(dev)) {
  356. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  357. } else {
  358. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  359. if (INTEL_INFO(dev)->gen < 4)
  360. val >>= 1;
  361. if (is_backlight_combination_mode(dev)) {
  362. u8 lbpc;
  363. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  364. val *= lbpc;
  365. }
  366. }
  367. val = intel_panel_compute_brightness(dev, val);
  368. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  369. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  370. return val;
  371. }
  372. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  373. {
  374. struct drm_i915_private *dev_priv = dev->dev_private;
  375. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  376. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  377. }
  378. static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
  379. {
  380. struct drm_i915_private *dev_priv = dev->dev_private;
  381. u32 tmp;
  382. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  383. level = intel_panel_compute_brightness(dev, level);
  384. if (HAS_PCH_SPLIT(dev))
  385. return intel_pch_panel_set_backlight(dev, level);
  386. if (is_backlight_combination_mode(dev)) {
  387. u32 max = intel_panel_get_max_backlight(dev);
  388. u8 lbpc;
  389. /* we're screwed, but keep behaviour backwards compatible */
  390. if (!max)
  391. max = 1;
  392. lbpc = level * 0xfe / max + 1;
  393. level /= lbpc;
  394. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  395. }
  396. tmp = I915_READ(BLC_PWM_CTL);
  397. if (INTEL_INFO(dev)->gen < 4)
  398. level <<= 1;
  399. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  400. I915_WRITE(BLC_PWM_CTL, tmp | level);
  401. }
  402. /* set backlight brightness to level in range [0..max] */
  403. void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
  404. {
  405. struct drm_i915_private *dev_priv = dev->dev_private;
  406. u32 freq;
  407. unsigned long flags;
  408. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  409. freq = intel_panel_get_max_backlight(dev);
  410. if (!freq) {
  411. /* we are screwed, bail out */
  412. goto out;
  413. }
  414. /* scale to hardware, but be careful to not overflow */
  415. if (freq < max)
  416. level = level * freq / max;
  417. else
  418. level = freq / max * level;
  419. dev_priv->backlight.level = level;
  420. if (dev_priv->backlight.device)
  421. dev_priv->backlight.device->props.brightness = level;
  422. if (dev_priv->backlight.enabled)
  423. intel_panel_actually_set_backlight(dev, level);
  424. out:
  425. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  426. }
  427. void intel_panel_disable_backlight(struct drm_device *dev)
  428. {
  429. struct drm_i915_private *dev_priv = dev->dev_private;
  430. unsigned long flags;
  431. /*
  432. * Do not disable backlight on the vgaswitcheroo path. When switching
  433. * away from i915, the other client may depend on i915 to handle the
  434. * backlight. This will leave the backlight on unnecessarily when
  435. * another client is not activated.
  436. */
  437. if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
  438. DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
  439. return;
  440. }
  441. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  442. dev_priv->backlight.enabled = false;
  443. intel_panel_actually_set_backlight(dev, 0);
  444. if (INTEL_INFO(dev)->gen >= 4) {
  445. uint32_t reg, tmp;
  446. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  447. I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
  448. if (HAS_PCH_SPLIT(dev)) {
  449. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  450. tmp &= ~BLM_PCH_PWM_ENABLE;
  451. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  452. }
  453. }
  454. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  455. }
  456. void intel_panel_enable_backlight(struct drm_device *dev,
  457. enum pipe pipe)
  458. {
  459. struct drm_i915_private *dev_priv = dev->dev_private;
  460. enum transcoder cpu_transcoder =
  461. intel_pipe_to_cpu_transcoder(dev_priv, pipe);
  462. unsigned long flags;
  463. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  464. if (dev_priv->backlight.level == 0) {
  465. dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
  466. if (dev_priv->backlight.device)
  467. dev_priv->backlight.device->props.brightness =
  468. dev_priv->backlight.level;
  469. }
  470. if (INTEL_INFO(dev)->gen >= 4) {
  471. uint32_t reg, tmp;
  472. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  473. tmp = I915_READ(reg);
  474. /* Note that this can also get called through dpms changes. And
  475. * we don't track the backlight dpms state, hence check whether
  476. * we have to do anything first. */
  477. if (tmp & BLM_PWM_ENABLE)
  478. goto set_level;
  479. if (INTEL_INFO(dev)->num_pipes == 3)
  480. tmp &= ~BLM_PIPE_SELECT_IVB;
  481. else
  482. tmp &= ~BLM_PIPE_SELECT;
  483. if (cpu_transcoder == TRANSCODER_EDP)
  484. tmp |= BLM_TRANSCODER_EDP;
  485. else
  486. tmp |= BLM_PIPE(cpu_transcoder);
  487. tmp &= ~BLM_PWM_ENABLE;
  488. I915_WRITE(reg, tmp);
  489. POSTING_READ(reg);
  490. I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
  491. if (HAS_PCH_SPLIT(dev) &&
  492. !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
  493. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  494. tmp |= BLM_PCH_PWM_ENABLE;
  495. tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
  496. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  497. }
  498. }
  499. set_level:
  500. /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
  501. * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
  502. * registers are set.
  503. */
  504. dev_priv->backlight.enabled = true;
  505. intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  506. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  507. }
  508. static void intel_panel_init_backlight(struct drm_device *dev)
  509. {
  510. struct drm_i915_private *dev_priv = dev->dev_private;
  511. dev_priv->backlight.level = intel_panel_get_backlight(dev);
  512. dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
  513. }
  514. enum drm_connector_status
  515. intel_panel_detect(struct drm_device *dev)
  516. {
  517. struct drm_i915_private *dev_priv = dev->dev_private;
  518. /* Assume that the BIOS does not lie through the OpRegion... */
  519. if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
  520. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  521. connector_status_connected :
  522. connector_status_disconnected;
  523. }
  524. switch (i915_panel_ignore_lid) {
  525. case -2:
  526. return connector_status_connected;
  527. case -1:
  528. return connector_status_disconnected;
  529. default:
  530. return connector_status_unknown;
  531. }
  532. }
  533. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  534. static int intel_panel_update_status(struct backlight_device *bd)
  535. {
  536. struct drm_device *dev = bl_get_data(bd);
  537. intel_panel_set_backlight(dev, bd->props.brightness,
  538. bd->props.max_brightness);
  539. return 0;
  540. }
  541. static int intel_panel_get_brightness(struct backlight_device *bd)
  542. {
  543. struct drm_device *dev = bl_get_data(bd);
  544. return intel_panel_get_backlight(dev);
  545. }
  546. static const struct backlight_ops intel_panel_bl_ops = {
  547. .update_status = intel_panel_update_status,
  548. .get_brightness = intel_panel_get_brightness,
  549. };
  550. int intel_panel_setup_backlight(struct drm_connector *connector)
  551. {
  552. struct drm_device *dev = connector->dev;
  553. struct drm_i915_private *dev_priv = dev->dev_private;
  554. struct backlight_properties props;
  555. unsigned long flags;
  556. intel_panel_init_backlight(dev);
  557. if (WARN_ON(dev_priv->backlight.device))
  558. return -ENODEV;
  559. memset(&props, 0, sizeof(props));
  560. props.type = BACKLIGHT_RAW;
  561. props.brightness = dev_priv->backlight.level;
  562. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  563. props.max_brightness = intel_panel_get_max_backlight(dev);
  564. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  565. if (props.max_brightness == 0) {
  566. DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
  567. return -ENODEV;
  568. }
  569. dev_priv->backlight.device =
  570. backlight_device_register("intel_backlight",
  571. &connector->kdev, dev,
  572. &intel_panel_bl_ops, &props);
  573. if (IS_ERR(dev_priv->backlight.device)) {
  574. DRM_ERROR("Failed to register backlight: %ld\n",
  575. PTR_ERR(dev_priv->backlight.device));
  576. dev_priv->backlight.device = NULL;
  577. return -ENODEV;
  578. }
  579. return 0;
  580. }
  581. void intel_panel_destroy_backlight(struct drm_device *dev)
  582. {
  583. struct drm_i915_private *dev_priv = dev->dev_private;
  584. if (dev_priv->backlight.device) {
  585. backlight_device_unregister(dev_priv->backlight.device);
  586. dev_priv->backlight.device = NULL;
  587. }
  588. }
  589. #else
  590. int intel_panel_setup_backlight(struct drm_connector *connector)
  591. {
  592. intel_panel_init_backlight(connector->dev);
  593. return 0;
  594. }
  595. void intel_panel_destroy_backlight(struct drm_device *dev)
  596. {
  597. return;
  598. }
  599. #endif
  600. int intel_panel_init(struct intel_panel *panel,
  601. struct drm_display_mode *fixed_mode)
  602. {
  603. panel->fixed_mode = fixed_mode;
  604. return 0;
  605. }
  606. void intel_panel_fini(struct intel_panel *panel)
  607. {
  608. struct intel_connector *intel_connector =
  609. container_of(panel, struct intel_connector, panel);
  610. if (panel->fixed_mode)
  611. drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
  612. }