edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012-2013 - Mauro Carvalho Chehab <mchehab@redhat.com>
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = kstrtol(val, 0, &l);
  52. if (ret)
  53. return ret;
  54. if ((int)l != l)
  55. return -EINVAL;
  56. *((int *)kp->arg) = l;
  57. /* notify edac_mc engine to reset the poll period */
  58. edac_mc_reset_delay_period(l);
  59. return 0;
  60. }
  61. /* Parameter declarations for above */
  62. module_param(edac_mc_panic_on_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  64. module_param(edac_mc_log_ue, int, 0644);
  65. MODULE_PARM_DESC(edac_mc_log_ue,
  66. "Log uncorrectable error to console: 0=off 1=on");
  67. module_param(edac_mc_log_ce, int, 0644);
  68. MODULE_PARM_DESC(edac_mc_log_ce,
  69. "Log correctable error to console: 0=off 1=on");
  70. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  71. &edac_mc_poll_msec, 0644);
  72. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  73. static struct device *mci_pdev;
  74. /*
  75. * various constants for Memory Controllers
  76. */
  77. static const char * const mem_types[] = {
  78. [MEM_EMPTY] = "Empty",
  79. [MEM_RESERVED] = "Reserved",
  80. [MEM_UNKNOWN] = "Unknown",
  81. [MEM_FPM] = "FPM",
  82. [MEM_EDO] = "EDO",
  83. [MEM_BEDO] = "BEDO",
  84. [MEM_SDR] = "Unbuffered-SDR",
  85. [MEM_RDR] = "Registered-SDR",
  86. [MEM_DDR] = "Unbuffered-DDR",
  87. [MEM_RDDR] = "Registered-DDR",
  88. [MEM_RMBS] = "RMBS",
  89. [MEM_DDR2] = "Unbuffered-DDR2",
  90. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  91. [MEM_RDDR2] = "Registered-DDR2",
  92. [MEM_XDR] = "XDR",
  93. [MEM_DDR3] = "Unbuffered-DDR3",
  94. [MEM_RDDR3] = "Registered-DDR3"
  95. };
  96. static const char * const dev_types[] = {
  97. [DEV_UNKNOWN] = "Unknown",
  98. [DEV_X1] = "x1",
  99. [DEV_X2] = "x2",
  100. [DEV_X4] = "x4",
  101. [DEV_X8] = "x8",
  102. [DEV_X16] = "x16",
  103. [DEV_X32] = "x32",
  104. [DEV_X64] = "x64"
  105. };
  106. static const char * const edac_caps[] = {
  107. [EDAC_UNKNOWN] = "Unknown",
  108. [EDAC_NONE] = "None",
  109. [EDAC_RESERVED] = "Reserved",
  110. [EDAC_PARITY] = "PARITY",
  111. [EDAC_EC] = "EC",
  112. [EDAC_SECDED] = "SECDED",
  113. [EDAC_S2ECD2ED] = "S2ECD2ED",
  114. [EDAC_S4ECD4ED] = "S4ECD4ED",
  115. [EDAC_S8ECD8ED] = "S8ECD8ED",
  116. [EDAC_S16ECD16ED] = "S16ECD16ED"
  117. };
  118. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  119. /*
  120. * EDAC sysfs CSROW data structures and methods
  121. */
  122. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  123. /*
  124. * We need it to avoid namespace conflicts between the legacy API
  125. * and the per-dimm/per-rank one
  126. */
  127. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  128. static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  129. struct dev_ch_attribute {
  130. struct device_attribute attr;
  131. int channel;
  132. };
  133. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  134. struct dev_ch_attribute dev_attr_legacy_##_name = \
  135. { __ATTR(_name, _mode, _show, _store), (_var) }
  136. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  137. /* Set of more default csrow<id> attribute show/store functions */
  138. static ssize_t csrow_ue_count_show(struct device *dev,
  139. struct device_attribute *mattr, char *data)
  140. {
  141. struct csrow_info *csrow = to_csrow(dev);
  142. return sprintf(data, "%u\n", csrow->ue_count);
  143. }
  144. static ssize_t csrow_ce_count_show(struct device *dev,
  145. struct device_attribute *mattr, char *data)
  146. {
  147. struct csrow_info *csrow = to_csrow(dev);
  148. return sprintf(data, "%u\n", csrow->ce_count);
  149. }
  150. static ssize_t csrow_size_show(struct device *dev,
  151. struct device_attribute *mattr, char *data)
  152. {
  153. struct csrow_info *csrow = to_csrow(dev);
  154. int i;
  155. u32 nr_pages = 0;
  156. for (i = 0; i < csrow->nr_channels; i++)
  157. nr_pages += csrow->channels[i]->dimm->nr_pages;
  158. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  159. }
  160. static ssize_t csrow_mem_type_show(struct device *dev,
  161. struct device_attribute *mattr, char *data)
  162. {
  163. struct csrow_info *csrow = to_csrow(dev);
  164. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  165. }
  166. static ssize_t csrow_dev_type_show(struct device *dev,
  167. struct device_attribute *mattr, char *data)
  168. {
  169. struct csrow_info *csrow = to_csrow(dev);
  170. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  171. }
  172. static ssize_t csrow_edac_mode_show(struct device *dev,
  173. struct device_attribute *mattr,
  174. char *data)
  175. {
  176. struct csrow_info *csrow = to_csrow(dev);
  177. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  178. }
  179. /* show/store functions for DIMM Label attributes */
  180. static ssize_t channel_dimm_label_show(struct device *dev,
  181. struct device_attribute *mattr,
  182. char *data)
  183. {
  184. struct csrow_info *csrow = to_csrow(dev);
  185. unsigned chan = to_channel(mattr);
  186. struct rank_info *rank = csrow->channels[chan];
  187. /* if field has not been initialized, there is nothing to send */
  188. if (!rank->dimm->label[0])
  189. return 0;
  190. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  191. rank->dimm->label);
  192. }
  193. static ssize_t channel_dimm_label_store(struct device *dev,
  194. struct device_attribute *mattr,
  195. const char *data, size_t count)
  196. {
  197. struct csrow_info *csrow = to_csrow(dev);
  198. unsigned chan = to_channel(mattr);
  199. struct rank_info *rank = csrow->channels[chan];
  200. ssize_t max_size = 0;
  201. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  202. strncpy(rank->dimm->label, data, max_size);
  203. rank->dimm->label[max_size] = '\0';
  204. return max_size;
  205. }
  206. /* show function for dynamic chX_ce_count attribute */
  207. static ssize_t channel_ce_count_show(struct device *dev,
  208. struct device_attribute *mattr, char *data)
  209. {
  210. struct csrow_info *csrow = to_csrow(dev);
  211. unsigned chan = to_channel(mattr);
  212. struct rank_info *rank = csrow->channels[chan];
  213. return sprintf(data, "%u\n", rank->ce_count);
  214. }
  215. /* cwrow<id>/attribute files */
  216. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  217. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  218. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  219. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  220. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  221. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  222. /* default attributes of the CSROW<id> object */
  223. static struct attribute *csrow_attrs[] = {
  224. &dev_attr_legacy_dev_type.attr,
  225. &dev_attr_legacy_mem_type.attr,
  226. &dev_attr_legacy_edac_mode.attr,
  227. &dev_attr_legacy_size_mb.attr,
  228. &dev_attr_legacy_ue_count.attr,
  229. &dev_attr_legacy_ce_count.attr,
  230. NULL,
  231. };
  232. static struct attribute_group csrow_attr_grp = {
  233. .attrs = csrow_attrs,
  234. };
  235. static const struct attribute_group *csrow_attr_groups[] = {
  236. &csrow_attr_grp,
  237. NULL
  238. };
  239. static void csrow_attr_release(struct device *dev)
  240. {
  241. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  242. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  243. kfree(csrow);
  244. }
  245. static struct device_type csrow_attr_type = {
  246. .groups = csrow_attr_groups,
  247. .release = csrow_attr_release,
  248. };
  249. /*
  250. * possible dynamic channel DIMM Label attribute files
  251. *
  252. */
  253. #define EDAC_NR_CHANNELS 6
  254. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  255. channel_dimm_label_show, channel_dimm_label_store, 0);
  256. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 1);
  258. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 2);
  260. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 3);
  262. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 4);
  264. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 5);
  266. /* Total possible dynamic DIMM Label attribute file table */
  267. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  268. &dev_attr_legacy_ch0_dimm_label.attr,
  269. &dev_attr_legacy_ch1_dimm_label.attr,
  270. &dev_attr_legacy_ch2_dimm_label.attr,
  271. &dev_attr_legacy_ch3_dimm_label.attr,
  272. &dev_attr_legacy_ch4_dimm_label.attr,
  273. &dev_attr_legacy_ch5_dimm_label.attr
  274. };
  275. /* possible dynamic channel ce_count attribute files */
  276. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
  277. channel_ce_count_show, NULL, 0);
  278. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
  279. channel_ce_count_show, NULL, 1);
  280. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
  281. channel_ce_count_show, NULL, 2);
  282. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
  283. channel_ce_count_show, NULL, 3);
  284. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
  285. channel_ce_count_show, NULL, 4);
  286. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
  287. channel_ce_count_show, NULL, 5);
  288. /* Total possible dynamic ce_count attribute file table */
  289. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  290. &dev_attr_legacy_ch0_ce_count.attr,
  291. &dev_attr_legacy_ch1_ce_count.attr,
  292. &dev_attr_legacy_ch2_ce_count.attr,
  293. &dev_attr_legacy_ch3_ce_count.attr,
  294. &dev_attr_legacy_ch4_ce_count.attr,
  295. &dev_attr_legacy_ch5_ce_count.attr
  296. };
  297. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  298. {
  299. int chan, nr_pages = 0;
  300. for (chan = 0; chan < csrow->nr_channels; chan++)
  301. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  302. return nr_pages;
  303. }
  304. /* Create a CSROW object under specifed edac_mc_device */
  305. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  306. struct csrow_info *csrow, int index)
  307. {
  308. int err, chan;
  309. if (csrow->nr_channels >= EDAC_NR_CHANNELS)
  310. return -ENODEV;
  311. csrow->dev.type = &csrow_attr_type;
  312. csrow->dev.bus = mci->bus;
  313. device_initialize(&csrow->dev);
  314. csrow->dev.parent = &mci->dev;
  315. csrow->mci = mci;
  316. dev_set_name(&csrow->dev, "csrow%d", index);
  317. dev_set_drvdata(&csrow->dev, csrow);
  318. edac_dbg(0, "creating (virtual) csrow node %s\n",
  319. dev_name(&csrow->dev));
  320. err = device_add(&csrow->dev);
  321. if (err < 0)
  322. return err;
  323. for (chan = 0; chan < csrow->nr_channels; chan++) {
  324. /* Only expose populated DIMMs */
  325. if (!csrow->channels[chan]->dimm->nr_pages)
  326. continue;
  327. err = device_create_file(&csrow->dev,
  328. dynamic_csrow_dimm_attr[chan]);
  329. if (err < 0)
  330. goto error;
  331. err = device_create_file(&csrow->dev,
  332. dynamic_csrow_ce_count_attr[chan]);
  333. if (err < 0) {
  334. device_remove_file(&csrow->dev,
  335. dynamic_csrow_dimm_attr[chan]);
  336. goto error;
  337. }
  338. }
  339. return 0;
  340. error:
  341. for (--chan; chan >= 0; chan--) {
  342. device_remove_file(&csrow->dev,
  343. dynamic_csrow_dimm_attr[chan]);
  344. device_remove_file(&csrow->dev,
  345. dynamic_csrow_ce_count_attr[chan]);
  346. }
  347. put_device(&csrow->dev);
  348. return err;
  349. }
  350. /* Create a CSROW object under specifed edac_mc_device */
  351. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  352. {
  353. int err, i, chan;
  354. struct csrow_info *csrow;
  355. for (i = 0; i < mci->nr_csrows; i++) {
  356. csrow = mci->csrows[i];
  357. if (!nr_pages_per_csrow(csrow))
  358. continue;
  359. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  360. if (err < 0) {
  361. edac_dbg(1,
  362. "failure: create csrow objects for csrow %d\n",
  363. i);
  364. goto error;
  365. }
  366. }
  367. return 0;
  368. error:
  369. for (--i; i >= 0; i--) {
  370. csrow = mci->csrows[i];
  371. if (!nr_pages_per_csrow(csrow))
  372. continue;
  373. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  374. if (!csrow->channels[chan]->dimm->nr_pages)
  375. continue;
  376. device_remove_file(&csrow->dev,
  377. dynamic_csrow_dimm_attr[chan]);
  378. device_remove_file(&csrow->dev,
  379. dynamic_csrow_ce_count_attr[chan]);
  380. }
  381. put_device(&mci->csrows[i]->dev);
  382. }
  383. return err;
  384. }
  385. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  386. {
  387. int i, chan;
  388. struct csrow_info *csrow;
  389. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  390. csrow = mci->csrows[i];
  391. if (!nr_pages_per_csrow(csrow))
  392. continue;
  393. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  394. if (!csrow->channels[chan]->dimm->nr_pages)
  395. continue;
  396. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  397. i, chan);
  398. device_remove_file(&csrow->dev,
  399. dynamic_csrow_dimm_attr[chan]);
  400. device_remove_file(&csrow->dev,
  401. dynamic_csrow_ce_count_attr[chan]);
  402. }
  403. device_unregister(&mci->csrows[i]->dev);
  404. }
  405. }
  406. #endif
  407. /*
  408. * Per-dimm (or per-rank) devices
  409. */
  410. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  411. /* show/store functions for DIMM Label attributes */
  412. static ssize_t dimmdev_location_show(struct device *dev,
  413. struct device_attribute *mattr, char *data)
  414. {
  415. struct dimm_info *dimm = to_dimm(dev);
  416. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  417. }
  418. static ssize_t dimmdev_label_show(struct device *dev,
  419. struct device_attribute *mattr, char *data)
  420. {
  421. struct dimm_info *dimm = to_dimm(dev);
  422. /* if field has not been initialized, there is nothing to send */
  423. if (!dimm->label[0])
  424. return 0;
  425. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  426. }
  427. static ssize_t dimmdev_label_store(struct device *dev,
  428. struct device_attribute *mattr,
  429. const char *data,
  430. size_t count)
  431. {
  432. struct dimm_info *dimm = to_dimm(dev);
  433. ssize_t max_size = 0;
  434. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  435. strncpy(dimm->label, data, max_size);
  436. dimm->label[max_size] = '\0';
  437. return max_size;
  438. }
  439. static ssize_t dimmdev_size_show(struct device *dev,
  440. struct device_attribute *mattr, char *data)
  441. {
  442. struct dimm_info *dimm = to_dimm(dev);
  443. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  444. }
  445. static ssize_t dimmdev_mem_type_show(struct device *dev,
  446. struct device_attribute *mattr, char *data)
  447. {
  448. struct dimm_info *dimm = to_dimm(dev);
  449. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  450. }
  451. static ssize_t dimmdev_dev_type_show(struct device *dev,
  452. struct device_attribute *mattr, char *data)
  453. {
  454. struct dimm_info *dimm = to_dimm(dev);
  455. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  456. }
  457. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  458. struct device_attribute *mattr,
  459. char *data)
  460. {
  461. struct dimm_info *dimm = to_dimm(dev);
  462. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  463. }
  464. /* dimm/rank attribute files */
  465. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  466. dimmdev_label_show, dimmdev_label_store);
  467. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  468. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  469. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  470. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  471. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  472. /* attributes of the dimm<id>/rank<id> object */
  473. static struct attribute *dimm_attrs[] = {
  474. &dev_attr_dimm_label.attr,
  475. &dev_attr_dimm_location.attr,
  476. &dev_attr_size.attr,
  477. &dev_attr_dimm_mem_type.attr,
  478. &dev_attr_dimm_dev_type.attr,
  479. &dev_attr_dimm_edac_mode.attr,
  480. NULL,
  481. };
  482. static struct attribute_group dimm_attr_grp = {
  483. .attrs = dimm_attrs,
  484. };
  485. static const struct attribute_group *dimm_attr_groups[] = {
  486. &dimm_attr_grp,
  487. NULL
  488. };
  489. static void dimm_attr_release(struct device *dev)
  490. {
  491. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  492. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  493. kfree(dimm);
  494. }
  495. static struct device_type dimm_attr_type = {
  496. .groups = dimm_attr_groups,
  497. .release = dimm_attr_release,
  498. };
  499. /* Create a DIMM object under specifed memory controller device */
  500. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  501. struct dimm_info *dimm,
  502. int index)
  503. {
  504. int err;
  505. dimm->mci = mci;
  506. dimm->dev.type = &dimm_attr_type;
  507. dimm->dev.bus = mci->bus;
  508. device_initialize(&dimm->dev);
  509. dimm->dev.parent = &mci->dev;
  510. if (mci->csbased)
  511. dev_set_name(&dimm->dev, "rank%d", index);
  512. else
  513. dev_set_name(&dimm->dev, "dimm%d", index);
  514. dev_set_drvdata(&dimm->dev, dimm);
  515. pm_runtime_forbid(&mci->dev);
  516. err = device_add(&dimm->dev);
  517. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  518. return err;
  519. }
  520. /*
  521. * Memory controller device
  522. */
  523. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  524. static ssize_t mci_reset_counters_store(struct device *dev,
  525. struct device_attribute *mattr,
  526. const char *data, size_t count)
  527. {
  528. struct mem_ctl_info *mci = to_mci(dev);
  529. int cnt, row, chan, i;
  530. mci->ue_mc = 0;
  531. mci->ce_mc = 0;
  532. mci->ue_noinfo_count = 0;
  533. mci->ce_noinfo_count = 0;
  534. for (row = 0; row < mci->nr_csrows; row++) {
  535. struct csrow_info *ri = mci->csrows[row];
  536. ri->ue_count = 0;
  537. ri->ce_count = 0;
  538. for (chan = 0; chan < ri->nr_channels; chan++)
  539. ri->channels[chan]->ce_count = 0;
  540. }
  541. cnt = 1;
  542. for (i = 0; i < mci->n_layers; i++) {
  543. cnt *= mci->layers[i].size;
  544. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  545. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  546. }
  547. mci->start_time = jiffies;
  548. return count;
  549. }
  550. /* Memory scrubbing interface:
  551. *
  552. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  553. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  554. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  555. *
  556. * Negative value still means that an error has occurred while setting
  557. * the scrub rate.
  558. */
  559. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  560. struct device_attribute *mattr,
  561. const char *data, size_t count)
  562. {
  563. struct mem_ctl_info *mci = to_mci(dev);
  564. unsigned long bandwidth = 0;
  565. int new_bw = 0;
  566. if (kstrtoul(data, 10, &bandwidth) < 0)
  567. return -EINVAL;
  568. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  569. if (new_bw < 0) {
  570. edac_printk(KERN_WARNING, EDAC_MC,
  571. "Error setting scrub rate to: %lu\n", bandwidth);
  572. return -EINVAL;
  573. }
  574. return count;
  575. }
  576. /*
  577. * ->get_sdram_scrub_rate() return value semantics same as above.
  578. */
  579. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  580. struct device_attribute *mattr,
  581. char *data)
  582. {
  583. struct mem_ctl_info *mci = to_mci(dev);
  584. int bandwidth = 0;
  585. bandwidth = mci->get_sdram_scrub_rate(mci);
  586. if (bandwidth < 0) {
  587. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  588. return bandwidth;
  589. }
  590. return sprintf(data, "%d\n", bandwidth);
  591. }
  592. /* default attribute files for the MCI object */
  593. static ssize_t mci_ue_count_show(struct device *dev,
  594. struct device_attribute *mattr,
  595. char *data)
  596. {
  597. struct mem_ctl_info *mci = to_mci(dev);
  598. return sprintf(data, "%d\n", mci->ue_mc);
  599. }
  600. static ssize_t mci_ce_count_show(struct device *dev,
  601. struct device_attribute *mattr,
  602. char *data)
  603. {
  604. struct mem_ctl_info *mci = to_mci(dev);
  605. return sprintf(data, "%d\n", mci->ce_mc);
  606. }
  607. static ssize_t mci_ce_noinfo_show(struct device *dev,
  608. struct device_attribute *mattr,
  609. char *data)
  610. {
  611. struct mem_ctl_info *mci = to_mci(dev);
  612. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  613. }
  614. static ssize_t mci_ue_noinfo_show(struct device *dev,
  615. struct device_attribute *mattr,
  616. char *data)
  617. {
  618. struct mem_ctl_info *mci = to_mci(dev);
  619. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  620. }
  621. static ssize_t mci_seconds_show(struct device *dev,
  622. struct device_attribute *mattr,
  623. char *data)
  624. {
  625. struct mem_ctl_info *mci = to_mci(dev);
  626. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  627. }
  628. static ssize_t mci_ctl_name_show(struct device *dev,
  629. struct device_attribute *mattr,
  630. char *data)
  631. {
  632. struct mem_ctl_info *mci = to_mci(dev);
  633. return sprintf(data, "%s\n", mci->ctl_name);
  634. }
  635. static ssize_t mci_size_mb_show(struct device *dev,
  636. struct device_attribute *mattr,
  637. char *data)
  638. {
  639. struct mem_ctl_info *mci = to_mci(dev);
  640. int total_pages = 0, csrow_idx, j;
  641. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  642. struct csrow_info *csrow = mci->csrows[csrow_idx];
  643. for (j = 0; j < csrow->nr_channels; j++) {
  644. struct dimm_info *dimm = csrow->channels[j]->dimm;
  645. total_pages += dimm->nr_pages;
  646. }
  647. }
  648. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  649. }
  650. static ssize_t mci_max_location_show(struct device *dev,
  651. struct device_attribute *mattr,
  652. char *data)
  653. {
  654. struct mem_ctl_info *mci = to_mci(dev);
  655. int i;
  656. char *p = data;
  657. for (i = 0; i < mci->n_layers; i++) {
  658. p += sprintf(p, "%s %d ",
  659. edac_layer_name[mci->layers[i].type],
  660. mci->layers[i].size - 1);
  661. }
  662. return p - data;
  663. }
  664. #ifdef CONFIG_EDAC_DEBUG
  665. static ssize_t edac_fake_inject_write(struct file *file,
  666. const char __user *data,
  667. size_t count, loff_t *ppos)
  668. {
  669. struct device *dev = file->private_data;
  670. struct mem_ctl_info *mci = to_mci(dev);
  671. static enum hw_event_mc_err_type type;
  672. u16 errcount = mci->fake_inject_count;
  673. if (!errcount)
  674. errcount = 1;
  675. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  676. : HW_EVENT_ERR_CORRECTED;
  677. printk(KERN_DEBUG
  678. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  679. errcount,
  680. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  681. errcount > 1 ? "s" : "",
  682. mci->fake_inject_layer[0],
  683. mci->fake_inject_layer[1],
  684. mci->fake_inject_layer[2]
  685. );
  686. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  687. mci->fake_inject_layer[0],
  688. mci->fake_inject_layer[1],
  689. mci->fake_inject_layer[2],
  690. "FAKE ERROR", "for EDAC testing only");
  691. return count;
  692. }
  693. static const struct file_operations debug_fake_inject_fops = {
  694. .open = simple_open,
  695. .write = edac_fake_inject_write,
  696. .llseek = generic_file_llseek,
  697. };
  698. #endif
  699. /* default Control file */
  700. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  701. /* default Attribute files */
  702. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  703. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  704. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  705. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  706. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  707. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  708. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  709. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  710. /* memory scrubber attribute file */
  711. DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
  712. static struct attribute *mci_attrs[] = {
  713. &dev_attr_reset_counters.attr,
  714. &dev_attr_mc_name.attr,
  715. &dev_attr_size_mb.attr,
  716. &dev_attr_seconds_since_reset.attr,
  717. &dev_attr_ue_noinfo_count.attr,
  718. &dev_attr_ce_noinfo_count.attr,
  719. &dev_attr_ue_count.attr,
  720. &dev_attr_ce_count.attr,
  721. &dev_attr_max_location.attr,
  722. NULL
  723. };
  724. static struct attribute_group mci_attr_grp = {
  725. .attrs = mci_attrs,
  726. };
  727. static const struct attribute_group *mci_attr_groups[] = {
  728. &mci_attr_grp,
  729. NULL
  730. };
  731. static void mci_attr_release(struct device *dev)
  732. {
  733. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  734. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  735. kfree(mci);
  736. }
  737. static struct device_type mci_attr_type = {
  738. .groups = mci_attr_groups,
  739. .release = mci_attr_release,
  740. };
  741. #ifdef CONFIG_EDAC_DEBUG
  742. static struct dentry *edac_debugfs;
  743. int __init edac_debugfs_init(void)
  744. {
  745. edac_debugfs = debugfs_create_dir("edac", NULL);
  746. if (IS_ERR(edac_debugfs)) {
  747. edac_debugfs = NULL;
  748. return -ENOMEM;
  749. }
  750. return 0;
  751. }
  752. void __exit edac_debugfs_exit(void)
  753. {
  754. debugfs_remove(edac_debugfs);
  755. }
  756. int edac_create_debug_nodes(struct mem_ctl_info *mci)
  757. {
  758. struct dentry *d, *parent;
  759. char name[80];
  760. int i;
  761. if (!edac_debugfs)
  762. return -ENODEV;
  763. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  764. if (!d)
  765. return -ENOMEM;
  766. parent = d;
  767. for (i = 0; i < mci->n_layers; i++) {
  768. sprintf(name, "fake_inject_%s",
  769. edac_layer_name[mci->layers[i].type]);
  770. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  771. &mci->fake_inject_layer[i]);
  772. if (!d)
  773. goto nomem;
  774. }
  775. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  776. &mci->fake_inject_ue);
  777. if (!d)
  778. goto nomem;
  779. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  780. &mci->fake_inject_count);
  781. if (!d)
  782. goto nomem;
  783. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  784. &mci->dev,
  785. &debug_fake_inject_fops);
  786. if (!d)
  787. goto nomem;
  788. mci->debugfs = parent;
  789. return 0;
  790. nomem:
  791. debugfs_remove(mci->debugfs);
  792. return -ENOMEM;
  793. }
  794. #endif
  795. /*
  796. * Create a new Memory Controller kobject instance,
  797. * mc<id> under the 'mc' directory
  798. *
  799. * Return:
  800. * 0 Success
  801. * !0 Failure
  802. */
  803. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  804. {
  805. int i, err;
  806. /*
  807. * The memory controller needs its own bus, in order to avoid
  808. * namespace conflicts at /sys/bus/edac.
  809. */
  810. mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  811. if (!mci->bus->name)
  812. return -ENOMEM;
  813. edac_dbg(0, "creating bus %s\n", mci->bus->name);
  814. err = bus_register(mci->bus);
  815. if (err < 0)
  816. return err;
  817. /* get the /sys/devices/system/edac subsys reference */
  818. mci->dev.type = &mci_attr_type;
  819. device_initialize(&mci->dev);
  820. mci->dev.parent = mci_pdev;
  821. mci->dev.bus = mci->bus;
  822. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  823. dev_set_drvdata(&mci->dev, mci);
  824. pm_runtime_forbid(&mci->dev);
  825. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  826. err = device_add(&mci->dev);
  827. if (err < 0) {
  828. edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
  829. bus_unregister(mci->bus);
  830. kfree(mci->bus->name);
  831. return err;
  832. }
  833. if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
  834. if (mci->get_sdram_scrub_rate) {
  835. dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
  836. dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
  837. }
  838. if (mci->set_sdram_scrub_rate) {
  839. dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
  840. dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
  841. }
  842. err = device_create_file(&mci->dev,
  843. &dev_attr_sdram_scrub_rate);
  844. if (err) {
  845. edac_dbg(1, "failure: create sdram_scrub_rate\n");
  846. goto fail2;
  847. }
  848. }
  849. /*
  850. * Create the dimm/rank devices
  851. */
  852. for (i = 0; i < mci->tot_dimms; i++) {
  853. struct dimm_info *dimm = mci->dimms[i];
  854. /* Only expose populated DIMMs */
  855. if (dimm->nr_pages == 0)
  856. continue;
  857. #ifdef CONFIG_EDAC_DEBUG
  858. edac_dbg(1, "creating dimm%d, located at ", i);
  859. if (edac_debug_level >= 1) {
  860. int lay;
  861. for (lay = 0; lay < mci->n_layers; lay++)
  862. printk(KERN_CONT "%s %d ",
  863. edac_layer_name[mci->layers[lay].type],
  864. dimm->location[lay]);
  865. printk(KERN_CONT "\n");
  866. }
  867. #endif
  868. err = edac_create_dimm_object(mci, dimm, i);
  869. if (err) {
  870. edac_dbg(1, "failure: create dimm %d obj\n", i);
  871. goto fail;
  872. }
  873. }
  874. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  875. err = edac_create_csrow_objects(mci);
  876. if (err < 0)
  877. goto fail;
  878. #endif
  879. #ifdef CONFIG_EDAC_DEBUG
  880. edac_create_debug_nodes(mci);
  881. #endif
  882. return 0;
  883. fail:
  884. for (i--; i >= 0; i--) {
  885. struct dimm_info *dimm = mci->dimms[i];
  886. if (dimm->nr_pages == 0)
  887. continue;
  888. device_unregister(&dimm->dev);
  889. }
  890. fail2:
  891. device_unregister(&mci->dev);
  892. bus_unregister(mci->bus);
  893. kfree(mci->bus->name);
  894. return err;
  895. }
  896. /*
  897. * remove a Memory Controller instance
  898. */
  899. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  900. {
  901. int i;
  902. edac_dbg(0, "\n");
  903. #ifdef CONFIG_EDAC_DEBUG
  904. debugfs_remove(mci->debugfs);
  905. #endif
  906. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  907. edac_delete_csrow_objects(mci);
  908. #endif
  909. for (i = 0; i < mci->tot_dimms; i++) {
  910. struct dimm_info *dimm = mci->dimms[i];
  911. if (dimm->nr_pages == 0)
  912. continue;
  913. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  914. device_unregister(&dimm->dev);
  915. }
  916. }
  917. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  918. {
  919. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  920. device_unregister(&mci->dev);
  921. bus_unregister(mci->bus);
  922. kfree(mci->bus->name);
  923. }
  924. static void mc_attr_release(struct device *dev)
  925. {
  926. /*
  927. * There's no container structure here, as this is just the mci
  928. * parent device, used to create the /sys/devices/mc sysfs node.
  929. * So, there are no attributes on it.
  930. */
  931. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  932. kfree(dev);
  933. }
  934. static struct device_type mc_attr_type = {
  935. .release = mc_attr_release,
  936. };
  937. /*
  938. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  939. */
  940. int __init edac_mc_sysfs_init(void)
  941. {
  942. struct bus_type *edac_subsys;
  943. int err;
  944. /* get the /sys/devices/system/edac subsys reference */
  945. edac_subsys = edac_get_sysfs_subsys();
  946. if (edac_subsys == NULL) {
  947. edac_dbg(1, "no edac_subsys\n");
  948. err = -EINVAL;
  949. goto out;
  950. }
  951. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  952. if (!mci_pdev) {
  953. err = -ENOMEM;
  954. goto out_put_sysfs;
  955. }
  956. mci_pdev->bus = edac_subsys;
  957. mci_pdev->type = &mc_attr_type;
  958. device_initialize(mci_pdev);
  959. dev_set_name(mci_pdev, "mc");
  960. err = device_add(mci_pdev);
  961. if (err < 0)
  962. goto out_dev_free;
  963. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  964. return 0;
  965. out_dev_free:
  966. kfree(mci_pdev);
  967. out_put_sysfs:
  968. edac_put_sysfs_subsys();
  969. out:
  970. return err;
  971. }
  972. void __exit edac_mc_sysfs_exit(void)
  973. {
  974. device_unregister(mci_pdev);
  975. edac_put_sysfs_subsys();
  976. }