clk.h 10.0 KB

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  1. /*
  2. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  3. * Copyright (c) 2013 Linaro Ltd.
  4. * Author: Thomas Abraham <thomas.ab@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Common Clock Framework support for all Samsung platforms
  11. */
  12. #ifndef __SAMSUNG_CLK_H
  13. #define __SAMSUNG_CLK_H
  14. #include <linux/clk.h>
  15. #include <linux/clkdev.h>
  16. #include <linux/io.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include "clk-pll.h"
  21. /**
  22. * struct samsung_clock_alias: information about mux clock
  23. * @id: platform specific id of the clock.
  24. * @dev_name: name of the device to which this clock belongs.
  25. * @alias: optional clock alias name to be assigned to this clock.
  26. */
  27. struct samsung_clock_alias {
  28. unsigned int id;
  29. const char *dev_name;
  30. const char *alias;
  31. };
  32. #define ALIAS(_id, dname, a) \
  33. { \
  34. .id = _id, \
  35. .dev_name = dname, \
  36. .alias = a, \
  37. }
  38. #define MHZ (1000 * 1000)
  39. /**
  40. * struct samsung_fixed_rate_clock: information about fixed-rate clock
  41. * @id: platform specific id of the clock.
  42. * @name: name of this fixed-rate clock.
  43. * @parent_name: optional parent clock name.
  44. * @flags: optional fixed-rate clock flags.
  45. * @fixed-rate: fixed clock rate of this clock.
  46. */
  47. struct samsung_fixed_rate_clock {
  48. unsigned int id;
  49. char *name;
  50. const char *parent_name;
  51. unsigned long flags;
  52. unsigned long fixed_rate;
  53. };
  54. #define FRATE(_id, cname, pname, f, frate) \
  55. { \
  56. .id = _id, \
  57. .name = cname, \
  58. .parent_name = pname, \
  59. .flags = f, \
  60. .fixed_rate = frate, \
  61. }
  62. /*
  63. * struct samsung_fixed_factor_clock: information about fixed-factor clock
  64. * @id: platform specific id of the clock.
  65. * @name: name of this fixed-factor clock.
  66. * @parent_name: parent clock name.
  67. * @mult: fixed multiplication factor.
  68. * @div: fixed division factor.
  69. * @flags: optional fixed-factor clock flags.
  70. */
  71. struct samsung_fixed_factor_clock {
  72. unsigned int id;
  73. char *name;
  74. const char *parent_name;
  75. unsigned long mult;
  76. unsigned long div;
  77. unsigned long flags;
  78. };
  79. #define FFACTOR(_id, cname, pname, m, d, f) \
  80. { \
  81. .id = _id, \
  82. .name = cname, \
  83. .parent_name = pname, \
  84. .mult = m, \
  85. .div = d, \
  86. .flags = f, \
  87. }
  88. /**
  89. * struct samsung_mux_clock: information about mux clock
  90. * @id: platform specific id of the clock.
  91. * @dev_name: name of the device to which this clock belongs.
  92. * @name: name of this mux clock.
  93. * @parent_names: array of pointer to parent clock names.
  94. * @num_parents: number of parents listed in @parent_names.
  95. * @flags: optional flags for basic clock.
  96. * @offset: offset of the register for configuring the mux.
  97. * @shift: starting bit location of the mux control bit-field in @reg.
  98. * @width: width of the mux control bit-field in @reg.
  99. * @mux_flags: flags for mux-type clock.
  100. * @alias: optional clock alias name to be assigned to this clock.
  101. */
  102. struct samsung_mux_clock {
  103. unsigned int id;
  104. const char *dev_name;
  105. const char *name;
  106. const char **parent_names;
  107. u8 num_parents;
  108. unsigned long flags;
  109. unsigned long offset;
  110. u8 shift;
  111. u8 width;
  112. u8 mux_flags;
  113. const char *alias;
  114. };
  115. #define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \
  116. { \
  117. .id = _id, \
  118. .dev_name = dname, \
  119. .name = cname, \
  120. .parent_names = pnames, \
  121. .num_parents = ARRAY_SIZE(pnames), \
  122. .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
  123. .offset = o, \
  124. .shift = s, \
  125. .width = w, \
  126. .mux_flags = mf, \
  127. .alias = a, \
  128. }
  129. #define MUX(_id, cname, pnames, o, s, w) \
  130. __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL)
  131. #define MUX_A(_id, cname, pnames, o, s, w, a) \
  132. __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
  133. #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
  134. __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL)
  135. #define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a) \
  136. __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
  137. /**
  138. * @id: platform specific id of the clock.
  139. * struct samsung_div_clock: information about div clock
  140. * @dev_name: name of the device to which this clock belongs.
  141. * @name: name of this div clock.
  142. * @parent_name: name of the parent clock.
  143. * @flags: optional flags for basic clock.
  144. * @offset: offset of the register for configuring the div.
  145. * @shift: starting bit location of the div control bit-field in @reg.
  146. * @div_flags: flags for div-type clock.
  147. * @alias: optional clock alias name to be assigned to this clock.
  148. */
  149. struct samsung_div_clock {
  150. unsigned int id;
  151. const char *dev_name;
  152. const char *name;
  153. const char *parent_name;
  154. unsigned long flags;
  155. unsigned long offset;
  156. u8 shift;
  157. u8 width;
  158. u8 div_flags;
  159. const char *alias;
  160. struct clk_div_table *table;
  161. };
  162. #define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \
  163. { \
  164. .id = _id, \
  165. .dev_name = dname, \
  166. .name = cname, \
  167. .parent_name = pname, \
  168. .flags = f, \
  169. .offset = o, \
  170. .shift = s, \
  171. .width = w, \
  172. .div_flags = df, \
  173. .alias = a, \
  174. .table = t, \
  175. }
  176. #define DIV(_id, cname, pname, o, s, w) \
  177. __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL)
  178. #define DIV_A(_id, cname, pname, o, s, w, a) \
  179. __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
  180. #define DIV_F(_id, cname, pname, o, s, w, f, df) \
  181. __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL)
  182. #define DIV_T(_id, cname, pname, o, s, w, t) \
  183. __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t)
  184. /**
  185. * struct samsung_gate_clock: information about gate clock
  186. * @id: platform specific id of the clock.
  187. * @dev_name: name of the device to which this clock belongs.
  188. * @name: name of this gate clock.
  189. * @parent_name: name of the parent clock.
  190. * @flags: optional flags for basic clock.
  191. * @offset: offset of the register for configuring the gate.
  192. * @bit_idx: bit index of the gate control bit-field in @reg.
  193. * @gate_flags: flags for gate-type clock.
  194. * @alias: optional clock alias name to be assigned to this clock.
  195. */
  196. struct samsung_gate_clock {
  197. unsigned int id;
  198. const char *dev_name;
  199. const char *name;
  200. const char *parent_name;
  201. unsigned long flags;
  202. unsigned long offset;
  203. u8 bit_idx;
  204. u8 gate_flags;
  205. const char *alias;
  206. };
  207. #define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \
  208. { \
  209. .id = _id, \
  210. .dev_name = dname, \
  211. .name = cname, \
  212. .parent_name = pname, \
  213. .flags = f, \
  214. .offset = o, \
  215. .bit_idx = b, \
  216. .gate_flags = gf, \
  217. .alias = a, \
  218. }
  219. #define GATE(_id, cname, pname, o, b, f, gf) \
  220. __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL)
  221. #define GATE_A(_id, cname, pname, o, b, f, gf, a) \
  222. __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
  223. #define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
  224. __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
  225. #define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
  226. __GATE(_id, dname, cname, pname, o, b, f, gf, a)
  227. #define PNAME(x) static const char *x[] __initdata
  228. /**
  229. * struct samsung_clk_reg_dump: register dump of clock controller registers.
  230. * @offset: clock register offset from the controller base address.
  231. * @value: the value to be register at offset.
  232. */
  233. struct samsung_clk_reg_dump {
  234. u32 offset;
  235. u32 value;
  236. };
  237. /**
  238. * struct samsung_pll_clock: information about pll clock
  239. * @id: platform specific id of the clock.
  240. * @dev_name: name of the device to which this clock belongs.
  241. * @name: name of this pll clock.
  242. * @parent_name: name of the parent clock.
  243. * @flags: optional flags for basic clock.
  244. * @con_offset: offset of the register for configuring the PLL.
  245. * @lock_offset: offset of the register for locking the PLL.
  246. * @type: Type of PLL to be registered.
  247. * @alias: optional clock alias name to be assigned to this clock.
  248. */
  249. struct samsung_pll_clock {
  250. unsigned int id;
  251. const char *dev_name;
  252. const char *name;
  253. const char *parent_name;
  254. unsigned long flags;
  255. int con_offset;
  256. int lock_offset;
  257. enum samsung_pll_type type;
  258. const struct samsung_pll_rate_table *rate_table;
  259. const char *alias;
  260. };
  261. #define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \
  262. _rtable, _alias) \
  263. { \
  264. .id = _id, \
  265. .type = _typ, \
  266. .dev_name = _dname, \
  267. .name = _name, \
  268. .parent_name = _pname, \
  269. .flags = CLK_GET_RATE_NOCACHE, \
  270. .con_offset = _con, \
  271. .lock_offset = _lock, \
  272. .rate_table = _rtable, \
  273. .alias = _alias, \
  274. }
  275. #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
  276. __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
  277. _lock, _con, _rtable, _name)
  278. #define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
  279. __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
  280. _lock, _con, _rtable, _alias)
  281. extern void __init samsung_clk_init(struct device_node *np, void __iomem *base,
  282. unsigned long nr_clks, unsigned long *rdump,
  283. unsigned long nr_rdump, unsigned long *soc_rdump,
  284. unsigned long nr_soc_rdump);
  285. extern void __init samsung_clk_of_register_fixed_ext(
  286. struct samsung_fixed_rate_clock *fixed_rate_clk,
  287. unsigned int nr_fixed_rate_clk,
  288. struct of_device_id *clk_matches);
  289. extern void samsung_clk_add_lookup(struct clk *clk, unsigned int id);
  290. extern void samsung_clk_register_alias(struct samsung_clock_alias *list,
  291. unsigned int nr_clk);
  292. extern void __init samsung_clk_register_fixed_rate(
  293. struct samsung_fixed_rate_clock *clk_list, unsigned int nr_clk);
  294. extern void __init samsung_clk_register_fixed_factor(
  295. struct samsung_fixed_factor_clock *list, unsigned int nr_clk);
  296. extern void __init samsung_clk_register_mux(struct samsung_mux_clock *clk_list,
  297. unsigned int nr_clk);
  298. extern void __init samsung_clk_register_div(struct samsung_div_clock *clk_list,
  299. unsigned int nr_clk);
  300. extern void __init samsung_clk_register_gate(
  301. struct samsung_gate_clock *clk_list, unsigned int nr_clk);
  302. extern void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
  303. unsigned int nr_clk, void __iomem *base);
  304. extern unsigned long _get_rate(const char *clk_name);
  305. #endif /* __SAMSUNG_CLK_H */