clk-imx28.c 10 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clk/mxs.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/err.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include <linux/of_address.h>
  19. #include "clk.h"
  20. static void __iomem *clkctrl;
  21. #define CLKCTRL clkctrl
  22. #define PLL0CTRL0 (CLKCTRL + 0x0000)
  23. #define PLL1CTRL0 (CLKCTRL + 0x0020)
  24. #define PLL2CTRL0 (CLKCTRL + 0x0040)
  25. #define CPU (CLKCTRL + 0x0050)
  26. #define HBUS (CLKCTRL + 0x0060)
  27. #define XBUS (CLKCTRL + 0x0070)
  28. #define XTAL (CLKCTRL + 0x0080)
  29. #define SSP0 (CLKCTRL + 0x0090)
  30. #define SSP1 (CLKCTRL + 0x00a0)
  31. #define SSP2 (CLKCTRL + 0x00b0)
  32. #define SSP3 (CLKCTRL + 0x00c0)
  33. #define GPMI (CLKCTRL + 0x00d0)
  34. #define SPDIF (CLKCTRL + 0x00e0)
  35. #define EMI (CLKCTRL + 0x00f0)
  36. #define SAIF0 (CLKCTRL + 0x0100)
  37. #define SAIF1 (CLKCTRL + 0x0110)
  38. #define LCDIF (CLKCTRL + 0x0120)
  39. #define ETM (CLKCTRL + 0x0130)
  40. #define ENET (CLKCTRL + 0x0140)
  41. #define FLEXCAN (CLKCTRL + 0x0160)
  42. #define FRAC0 (CLKCTRL + 0x01b0)
  43. #define FRAC1 (CLKCTRL + 0x01c0)
  44. #define CLKSEQ (CLKCTRL + 0x01d0)
  45. #define BP_CPU_INTERRUPT_WAIT 12
  46. #define BP_SAIF_DIV_FRAC_EN 16
  47. #define BP_ENET_DIV_TIME 21
  48. #define BP_ENET_SLEEP 31
  49. #define BP_CLKSEQ_BYPASS_SAIF0 0
  50. #define BP_CLKSEQ_BYPASS_SSP0 3
  51. #define BP_FRAC0_IO1FRAC 16
  52. #define BP_FRAC0_IO0FRAC 24
  53. static void __iomem *digctrl;
  54. #define DIGCTRL digctrl
  55. #define BP_SAIF_CLKMUX 10
  56. /*
  57. * HW_SAIF_CLKMUX_SEL:
  58. * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
  59. * clock pins selected for SAIF1 input clocks.
  60. * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
  61. * SAIF0 clock inputs selected for SAIF1 input clocks.
  62. * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
  63. * clocks.
  64. * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
  65. * clocks.
  66. */
  67. int mxs_saif_clkmux_select(unsigned int clkmux)
  68. {
  69. if (clkmux > 0x3)
  70. return -EINVAL;
  71. writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
  72. writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
  73. return 0;
  74. }
  75. static void __init clk_misc_init(void)
  76. {
  77. u32 val;
  78. /* Gate off cpu clock in WFI for power saving */
  79. writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
  80. /* 0 is a bad default value for a divider */
  81. writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
  82. /* Clear BYPASS for SAIF */
  83. writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
  84. /* SAIF has to use frac div for functional operation */
  85. val = readl_relaxed(SAIF0);
  86. val |= 1 << BP_SAIF_DIV_FRAC_EN;
  87. writel_relaxed(val, SAIF0);
  88. val = readl_relaxed(SAIF1);
  89. val |= 1 << BP_SAIF_DIV_FRAC_EN;
  90. writel_relaxed(val, SAIF1);
  91. /* Extra fec clock setting */
  92. val = readl_relaxed(ENET);
  93. val &= ~(1 << BP_ENET_SLEEP);
  94. writel_relaxed(val, ENET);
  95. /*
  96. * Source ssp clock from ref_io than ref_xtal,
  97. * as ref_xtal only provides 24 MHz as maximum.
  98. */
  99. writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
  100. /*
  101. * 480 MHz seems too high to be ssp clock source directly,
  102. * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
  103. */
  104. val = readl_relaxed(FRAC0);
  105. val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
  106. val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
  107. writel_relaxed(val, FRAC0);
  108. }
  109. static const char *sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", };
  110. static const char *sel_io0[] __initconst = { "ref_io0", "ref_xtal", };
  111. static const char *sel_io1[] __initconst = { "ref_io1", "ref_xtal", };
  112. static const char *sel_pix[] __initconst = { "ref_pix", "ref_xtal", };
  113. static const char *sel_gpmi[] __initconst = { "ref_gpmi", "ref_xtal", };
  114. static const char *sel_pll0[] __initconst = { "pll0", "ref_xtal", };
  115. static const char *cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", };
  116. static const char *emi_sels[] __initconst = { "emi_pll", "emi_xtal", };
  117. static const char *ptp_sels[] __initconst = { "ref_xtal", "pll0", };
  118. enum imx28_clk {
  119. ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1,
  120. ref_pix, ref_hsadc, ref_gpmi, saif0_sel, saif1_sel, gpmi_sel,
  121. ssp0_sel, ssp1_sel, ssp2_sel, ssp3_sel, emi_sel, etm_sel,
  122. lcdif_sel, cpu, ptp_sel, cpu_pll, cpu_xtal, hbus, xbus,
  123. ssp0_div, ssp1_div, ssp2_div, ssp3_div, gpmi_div, emi_pll,
  124. emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
  125. clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
  126. ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
  127. fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
  128. clk_max
  129. };
  130. static struct clk *clks[clk_max];
  131. static struct clk_onecell_data clk_data;
  132. static enum imx28_clk clks_init_on[] __initdata = {
  133. cpu, hbus, xbus, emi, uart,
  134. };
  135. int __init mx28_clocks_init(void)
  136. {
  137. struct device_node *np;
  138. u32 i;
  139. np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
  140. digctrl = of_iomap(np, 0);
  141. WARN_ON(!digctrl);
  142. np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
  143. clkctrl = of_iomap(np, 0);
  144. WARN_ON(!clkctrl);
  145. clk_misc_init();
  146. clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
  147. clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000);
  148. clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000);
  149. clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000);
  150. clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0);
  151. clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1);
  152. clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2);
  153. clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3);
  154. clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0);
  155. clks[ref_hsadc] = mxs_clk_ref("ref_hsadc", "pll0", FRAC1, 1);
  156. clks[ref_gpmi] = mxs_clk_ref("ref_gpmi", "pll0", FRAC1, 2);
  157. clks[saif0_sel] = mxs_clk_mux("saif0_sel", CLKSEQ, 0, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
  158. clks[saif1_sel] = mxs_clk_mux("saif1_sel", CLKSEQ, 1, 1, sel_pll0, ARRAY_SIZE(sel_pll0));
  159. clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 2, 1, sel_gpmi, ARRAY_SIZE(sel_gpmi));
  160. clks[ssp0_sel] = mxs_clk_mux("ssp0_sel", CLKSEQ, 3, 1, sel_io0, ARRAY_SIZE(sel_io0));
  161. clks[ssp1_sel] = mxs_clk_mux("ssp1_sel", CLKSEQ, 4, 1, sel_io0, ARRAY_SIZE(sel_io0));
  162. clks[ssp2_sel] = mxs_clk_mux("ssp2_sel", CLKSEQ, 5, 1, sel_io1, ARRAY_SIZE(sel_io1));
  163. clks[ssp3_sel] = mxs_clk_mux("ssp3_sel", CLKSEQ, 6, 1, sel_io1, ARRAY_SIZE(sel_io1));
  164. clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 7, 1, emi_sels, ARRAY_SIZE(emi_sels));
  165. clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
  166. clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 14, 1, sel_pix, ARRAY_SIZE(sel_pix));
  167. clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 18, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
  168. clks[ptp_sel] = mxs_clk_mux("ptp_sel", ENET, 19, 1, ptp_sels, ARRAY_SIZE(ptp_sels));
  169. clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
  170. clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
  171. clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 31);
  172. clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
  173. clks[ssp0_div] = mxs_clk_div("ssp0_div", "ssp0_sel", SSP0, 0, 9, 29);
  174. clks[ssp1_div] = mxs_clk_div("ssp1_div", "ssp1_sel", SSP1, 0, 9, 29);
  175. clks[ssp2_div] = mxs_clk_div("ssp2_div", "ssp2_sel", SSP2, 0, 9, 29);
  176. clks[ssp3_div] = mxs_clk_div("ssp3_div", "ssp3_sel", SSP3, 0, 9, 29);
  177. clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
  178. clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
  179. clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
  180. clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", LCDIF, 0, 13, 29);
  181. clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 7, 29);
  182. clks[ptp] = mxs_clk_div("ptp", "ptp_sel", ENET, 21, 6, 27);
  183. clks[saif0_div] = mxs_clk_frac("saif0_div", "saif0_sel", SAIF0, 0, 16, 29);
  184. clks[saif1_div] = mxs_clk_frac("saif1_div", "saif1_sel", SAIF1, 0, 16, 29);
  185. clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
  186. clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
  187. clks[lradc] = mxs_clk_fixed_factor("lradc", "clk32k", 1, 16);
  188. clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll0", 1, 4);
  189. clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
  190. clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
  191. clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
  192. clks[ssp0] = mxs_clk_gate("ssp0", "ssp0_div", SSP0, 31);
  193. clks[ssp1] = mxs_clk_gate("ssp1", "ssp1_div", SSP1, 31);
  194. clks[ssp2] = mxs_clk_gate("ssp2", "ssp2_div", SSP2, 31);
  195. clks[ssp3] = mxs_clk_gate("ssp3", "ssp3_div", SSP3, 31);
  196. clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
  197. clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
  198. clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
  199. clks[saif0] = mxs_clk_gate("saif0", "saif0_div", SAIF0, 31);
  200. clks[saif1] = mxs_clk_gate("saif1", "saif1_div", SAIF1, 31);
  201. clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", LCDIF, 31);
  202. clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
  203. clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
  204. clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
  205. clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
  206. clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
  207. clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
  208. clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
  209. clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
  210. clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
  211. for (i = 0; i < ARRAY_SIZE(clks); i++)
  212. if (IS_ERR(clks[i])) {
  213. pr_err("i.MX28 clk %d: register failed with %ld\n",
  214. i, PTR_ERR(clks[i]));
  215. return PTR_ERR(clks[i]);
  216. }
  217. clk_data.clks = clks;
  218. clk_data.clk_num = ARRAY_SIZE(clks);
  219. of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
  220. clk_register_clkdev(clks[enet_out], NULL, "enet_out");
  221. for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
  222. clk_prepare_enable(clks[clks_init_on[i]]);
  223. return 0;
  224. }