kirkwood.c 6.1 KB

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  1. /*
  2. * Marvell Kirkwood SoC clocks
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  7. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  8. * Andrew Lunn <andrew@lunn.ch>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include "common.h"
  19. /*
  20. * Core Clocks
  21. *
  22. * Kirkwood PLL sample-at-reset configuration
  23. * (6180 has different SAR layout than other Kirkwood SoCs)
  24. *
  25. * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
  26. * 4 = 600 MHz
  27. * 6 = 800 MHz
  28. * 7 = 1000 MHz
  29. * 9 = 1200 MHz
  30. * 12 = 1500 MHz
  31. * 13 = 1600 MHz
  32. * 14 = 1800 MHz
  33. * 15 = 2000 MHz
  34. * others reserved.
  35. *
  36. * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
  37. * 1 = (1/2) * CPU
  38. * 3 = (1/3) * CPU
  39. * 5 = (1/4) * CPU
  40. * others reserved.
  41. *
  42. * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
  43. * 2 = (1/2) * CPU
  44. * 4 = (1/3) * CPU
  45. * 6 = (1/4) * CPU
  46. * 7 = (2/9) * CPU
  47. * 8 = (1/5) * CPU
  48. * 9 = (1/6) * CPU
  49. * others reserved.
  50. *
  51. * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
  52. * 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
  53. * 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
  54. * 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
  55. * others reserved.
  56. *
  57. * SAR0[21] : TCLK frequency
  58. * 0 = 200 MHz
  59. * 1 = 166 MHz
  60. * others reserved.
  61. */
  62. #define SAR_KIRKWOOD_CPU_FREQ(x) \
  63. (((x & (1 << 1)) >> 1) | \
  64. ((x & (1 << 22)) >> 21) | \
  65. ((x & (3 << 3)) >> 1))
  66. #define SAR_KIRKWOOD_L2_RATIO(x) \
  67. (((x & (3 << 9)) >> 9) | \
  68. (((x & (1 << 19)) >> 17)))
  69. #define SAR_KIRKWOOD_DDR_RATIO 5
  70. #define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf
  71. #define SAR_MV88F6180_CLK 2
  72. #define SAR_MV88F6180_CLK_MASK 0x7
  73. #define SAR_KIRKWOOD_TCLK_FREQ 21
  74. #define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1
  75. enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
  76. static const struct coreclk_ratio kirkwood_coreclk_ratios[] __initconst = {
  77. { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
  78. { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
  79. };
  80. static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
  81. {
  82. u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
  83. SAR_KIRKWOOD_TCLK_FREQ_MASK;
  84. return (opt) ? 166666667 : 200000000;
  85. }
  86. static const u32 kirkwood_cpu_freqs[] __initconst = {
  87. 0, 0, 0, 0,
  88. 600000000,
  89. 0,
  90. 800000000,
  91. 1000000000,
  92. 0,
  93. 1200000000,
  94. 0, 0,
  95. 1500000000,
  96. 1600000000,
  97. 1800000000,
  98. 2000000000
  99. };
  100. static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
  101. {
  102. u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
  103. return kirkwood_cpu_freqs[opt];
  104. }
  105. static const int kirkwood_cpu_l2_ratios[8][2] __initconst = {
  106. { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
  107. { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
  108. };
  109. static const int kirkwood_cpu_ddr_ratios[16][2] __initconst = {
  110. { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
  111. { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
  112. { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
  113. { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
  114. };
  115. static void __init kirkwood_get_clk_ratio(
  116. void __iomem *sar, int id, int *mult, int *div)
  117. {
  118. switch (id) {
  119. case KIRKWOOD_CPU_TO_L2:
  120. {
  121. u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
  122. *mult = kirkwood_cpu_l2_ratios[opt][0];
  123. *div = kirkwood_cpu_l2_ratios[opt][1];
  124. break;
  125. }
  126. case KIRKWOOD_CPU_TO_DDR:
  127. {
  128. u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
  129. SAR_KIRKWOOD_DDR_RATIO_MASK;
  130. *mult = kirkwood_cpu_ddr_ratios[opt][0];
  131. *div = kirkwood_cpu_ddr_ratios[opt][1];
  132. break;
  133. }
  134. }
  135. }
  136. static const u32 mv88f6180_cpu_freqs[] __initconst = {
  137. 0, 0, 0, 0, 0,
  138. 600000000,
  139. 800000000,
  140. 1000000000
  141. };
  142. static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
  143. {
  144. u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
  145. return mv88f6180_cpu_freqs[opt];
  146. }
  147. static const int mv88f6180_cpu_ddr_ratios[8][2] __initconst = {
  148. { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
  149. { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
  150. };
  151. static void __init mv88f6180_get_clk_ratio(
  152. void __iomem *sar, int id, int *mult, int *div)
  153. {
  154. switch (id) {
  155. case KIRKWOOD_CPU_TO_L2:
  156. {
  157. /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
  158. *mult = 1;
  159. *div = 2;
  160. break;
  161. }
  162. case KIRKWOOD_CPU_TO_DDR:
  163. {
  164. u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
  165. SAR_MV88F6180_CLK_MASK;
  166. *mult = mv88f6180_cpu_ddr_ratios[opt][0];
  167. *div = mv88f6180_cpu_ddr_ratios[opt][1];
  168. break;
  169. }
  170. }
  171. }
  172. static const struct coreclk_soc_desc kirkwood_coreclks = {
  173. .get_tclk_freq = kirkwood_get_tclk_freq,
  174. .get_cpu_freq = kirkwood_get_cpu_freq,
  175. .get_clk_ratio = kirkwood_get_clk_ratio,
  176. .ratios = kirkwood_coreclk_ratios,
  177. .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
  178. };
  179. static void __init kirkwood_coreclk_init(struct device_node *np)
  180. {
  181. mvebu_coreclk_setup(np, &kirkwood_coreclks);
  182. }
  183. CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
  184. kirkwood_coreclk_init);
  185. static const struct coreclk_soc_desc mv88f6180_coreclks = {
  186. .get_tclk_freq = kirkwood_get_tclk_freq,
  187. .get_cpu_freq = mv88f6180_get_cpu_freq,
  188. .get_clk_ratio = mv88f6180_get_clk_ratio,
  189. .ratios = kirkwood_coreclk_ratios,
  190. .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
  191. };
  192. static void __init mv88f6180_coreclk_init(struct device_node *np)
  193. {
  194. mvebu_coreclk_setup(np, &mv88f6180_coreclks);
  195. }
  196. CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
  197. mv88f6180_coreclk_init);
  198. /*
  199. * Clock Gating Control
  200. */
  201. static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = {
  202. { "ge0", NULL, 0, 0 },
  203. { "pex0", NULL, 2, 0 },
  204. { "usb0", NULL, 3, 0 },
  205. { "sdio", NULL, 4, 0 },
  206. { "tsu", NULL, 5, 0 },
  207. { "runit", NULL, 7, 0 },
  208. { "xor0", NULL, 8, 0 },
  209. { "audio", NULL, 9, 0 },
  210. { "powersave", "cpuclk", 11, 0 },
  211. { "sata0", NULL, 14, 0 },
  212. { "sata1", NULL, 15, 0 },
  213. { "xor1", NULL, 16, 0 },
  214. { "crypto", NULL, 17, 0 },
  215. { "pex1", NULL, 18, 0 },
  216. { "ge1", NULL, 19, 0 },
  217. { "tdm", NULL, 20, 0 },
  218. { }
  219. };
  220. static void __init kirkwood_clk_gating_init(struct device_node *np)
  221. {
  222. mvebu_clk_gating_setup(np, kirkwood_gating_desc);
  223. }
  224. CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
  225. kirkwood_clk_gating_init);