scan.c 15 KB

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  1. /*
  2. * Broadcom specific AMBA
  3. * Bus scanning
  4. *
  5. * Licensed under the GNU/GPL. See COPYING for details.
  6. */
  7. #include "scan.h"
  8. #include "bcma_private.h"
  9. #include <linux/bcma/bcma.h>
  10. #include <linux/bcma/bcma_regs.h>
  11. #include <linux/pci.h>
  12. #include <linux/io.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/slab.h>
  15. struct bcma_device_id_name {
  16. u16 id;
  17. const char *name;
  18. };
  19. static const struct bcma_device_id_name bcma_arm_device_names[] = {
  20. { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
  21. { BCMA_CORE_ARM_1176, "ARM 1176" },
  22. { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
  23. { BCMA_CORE_ARM_CM3, "ARM CM3" },
  24. };
  25. static const struct bcma_device_id_name bcma_bcm_device_names[] = {
  26. { BCMA_CORE_OOB_ROUTER, "OOB Router" },
  27. { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
  28. { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
  29. { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
  30. { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
  31. { BCMA_CORE_DMA, "DMA" },
  32. { BCMA_CORE_SDIO3, "SDIO3" },
  33. { BCMA_CORE_USB20, "USB 2.0" },
  34. { BCMA_CORE_USB30, "USB 3.0" },
  35. { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
  36. { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
  37. { BCMA_CORE_ROM, "ROM" },
  38. { BCMA_CORE_NAND, "NAND flash controller" },
  39. { BCMA_CORE_QSPI, "SPI flash controller" },
  40. { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
  41. { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
  42. { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
  43. { BCMA_CORE_ALTA, "ALTA (I2S)" },
  44. { BCMA_CORE_INVALID, "Invalid" },
  45. { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
  46. { BCMA_CORE_ILINE20, "ILine 20" },
  47. { BCMA_CORE_SRAM, "SRAM" },
  48. { BCMA_CORE_SDRAM, "SDRAM" },
  49. { BCMA_CORE_PCI, "PCI" },
  50. { BCMA_CORE_ETHERNET, "Fast Ethernet" },
  51. { BCMA_CORE_V90, "V90" },
  52. { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
  53. { BCMA_CORE_ADSL, "ADSL" },
  54. { BCMA_CORE_ILINE100, "ILine 100" },
  55. { BCMA_CORE_IPSEC, "IPSEC" },
  56. { BCMA_CORE_UTOPIA, "UTOPIA" },
  57. { BCMA_CORE_PCMCIA, "PCMCIA" },
  58. { BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
  59. { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
  60. { BCMA_CORE_OFDM, "OFDM" },
  61. { BCMA_CORE_EXTIF, "EXTIF" },
  62. { BCMA_CORE_80211, "IEEE 802.11" },
  63. { BCMA_CORE_PHY_A, "PHY A" },
  64. { BCMA_CORE_PHY_B, "PHY B" },
  65. { BCMA_CORE_PHY_G, "PHY G" },
  66. { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
  67. { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
  68. { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
  69. { BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
  70. { BCMA_CORE_SDIO_HOST, "SDIO Host" },
  71. { BCMA_CORE_ROBOSWITCH, "Roboswitch" },
  72. { BCMA_CORE_PARA_ATA, "PATA" },
  73. { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
  74. { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
  75. { BCMA_CORE_PCIE, "PCIe" },
  76. { BCMA_CORE_PHY_N, "PHY N" },
  77. { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
  78. { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
  79. { BCMA_CORE_PHY_LP, "PHY LP" },
  80. { BCMA_CORE_PMU, "PMU" },
  81. { BCMA_CORE_PHY_SSN, "PHY SSN" },
  82. { BCMA_CORE_SDIO_DEV, "SDIO Device" },
  83. { BCMA_CORE_PHY_HT, "PHY HT" },
  84. { BCMA_CORE_MAC_GBIT, "GBit MAC" },
  85. { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
  86. { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
  87. { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
  88. { BCMA_CORE_SHARED_COMMON, "Common Shared" },
  89. { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
  90. { BCMA_CORE_SPI_HOST, "SPI Host" },
  91. { BCMA_CORE_I2S, "I2S" },
  92. { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
  93. { BCMA_CORE_SHIM, "SHIM" },
  94. { BCMA_CORE_PCIE2, "PCIe Gen2" },
  95. { BCMA_CORE_ARM_CR4, "ARM CR4" },
  96. { BCMA_CORE_DEFAULT, "Default" },
  97. };
  98. static const struct bcma_device_id_name bcma_mips_device_names[] = {
  99. { BCMA_CORE_MIPS, "MIPS" },
  100. { BCMA_CORE_MIPS_3302, "MIPS 3302" },
  101. { BCMA_CORE_MIPS_74K, "MIPS 74K" },
  102. };
  103. static const char *bcma_device_name(const struct bcma_device_id *id)
  104. {
  105. const struct bcma_device_id_name *names;
  106. int size, i;
  107. /* search manufacturer specific names */
  108. switch (id->manuf) {
  109. case BCMA_MANUF_ARM:
  110. names = bcma_arm_device_names;
  111. size = ARRAY_SIZE(bcma_arm_device_names);
  112. break;
  113. case BCMA_MANUF_BCM:
  114. names = bcma_bcm_device_names;
  115. size = ARRAY_SIZE(bcma_bcm_device_names);
  116. break;
  117. case BCMA_MANUF_MIPS:
  118. names = bcma_mips_device_names;
  119. size = ARRAY_SIZE(bcma_mips_device_names);
  120. break;
  121. default:
  122. return "UNKNOWN";
  123. }
  124. for (i = 0; i < size; i++) {
  125. if (names[i].id == id->id)
  126. return names[i].name;
  127. }
  128. return "UNKNOWN";
  129. }
  130. static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
  131. u16 offset)
  132. {
  133. return readl(bus->mmio + offset);
  134. }
  135. static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
  136. {
  137. if (bus->hosttype == BCMA_HOSTTYPE_PCI)
  138. pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
  139. addr);
  140. }
  141. static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
  142. {
  143. u32 ent = readl(*eromptr);
  144. (*eromptr)++;
  145. return ent;
  146. }
  147. static void bcma_erom_push_ent(u32 __iomem **eromptr)
  148. {
  149. (*eromptr)--;
  150. }
  151. static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
  152. {
  153. u32 ent = bcma_erom_get_ent(bus, eromptr);
  154. if (!(ent & SCAN_ER_VALID))
  155. return -ENOENT;
  156. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
  157. return -ENOENT;
  158. return ent;
  159. }
  160. static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
  161. {
  162. u32 ent = bcma_erom_get_ent(bus, eromptr);
  163. bcma_erom_push_ent(eromptr);
  164. return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
  165. }
  166. static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
  167. {
  168. u32 ent = bcma_erom_get_ent(bus, eromptr);
  169. bcma_erom_push_ent(eromptr);
  170. return (((ent & SCAN_ER_VALID)) &&
  171. ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
  172. ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
  173. }
  174. static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
  175. {
  176. u32 ent;
  177. while (1) {
  178. ent = bcma_erom_get_ent(bus, eromptr);
  179. if ((ent & SCAN_ER_VALID) &&
  180. ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
  181. break;
  182. if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
  183. break;
  184. }
  185. bcma_erom_push_ent(eromptr);
  186. }
  187. static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
  188. {
  189. u32 ent = bcma_erom_get_ent(bus, eromptr);
  190. if (!(ent & SCAN_ER_VALID))
  191. return -ENOENT;
  192. if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
  193. return -ENOENT;
  194. return ent;
  195. }
  196. static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
  197. u32 type, u8 port)
  198. {
  199. u32 addrl, addrh, sizel, sizeh = 0;
  200. u32 size;
  201. u32 ent = bcma_erom_get_ent(bus, eromptr);
  202. if ((!(ent & SCAN_ER_VALID)) ||
  203. ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
  204. ((ent & SCAN_ADDR_TYPE) != type) ||
  205. (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
  206. bcma_erom_push_ent(eromptr);
  207. return (u32)-EINVAL;
  208. }
  209. addrl = ent & SCAN_ADDR_ADDR;
  210. if (ent & SCAN_ADDR_AG32)
  211. addrh = bcma_erom_get_ent(bus, eromptr);
  212. else
  213. addrh = 0;
  214. if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
  215. size = bcma_erom_get_ent(bus, eromptr);
  216. sizel = size & SCAN_SIZE_SZ;
  217. if (size & SCAN_SIZE_SG32)
  218. sizeh = bcma_erom_get_ent(bus, eromptr);
  219. } else
  220. sizel = SCAN_ADDR_SZ_BASE <<
  221. ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
  222. return addrl;
  223. }
  224. static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
  225. u16 index)
  226. {
  227. struct bcma_device *core;
  228. list_for_each_entry(core, &bus->cores, list) {
  229. if (core->core_index == index)
  230. return core;
  231. }
  232. return NULL;
  233. }
  234. static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
  235. {
  236. struct bcma_device *core;
  237. list_for_each_entry_reverse(core, &bus->cores, list) {
  238. if (core->id.id == coreid)
  239. return core;
  240. }
  241. return NULL;
  242. }
  243. static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
  244. struct bcma_device_id *match, int core_num,
  245. struct bcma_device *core)
  246. {
  247. u32 tmp;
  248. u8 i, j;
  249. s32 cia, cib;
  250. u8 ports[2], wrappers[2];
  251. /* get CIs */
  252. cia = bcma_erom_get_ci(bus, eromptr);
  253. if (cia < 0) {
  254. bcma_erom_push_ent(eromptr);
  255. if (bcma_erom_is_end(bus, eromptr))
  256. return -ESPIPE;
  257. return -EILSEQ;
  258. }
  259. cib = bcma_erom_get_ci(bus, eromptr);
  260. if (cib < 0)
  261. return -EILSEQ;
  262. /* parse CIs */
  263. core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
  264. core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
  265. core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
  266. ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
  267. ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
  268. wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
  269. wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
  270. core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
  271. if (((core->id.manuf == BCMA_MANUF_ARM) &&
  272. (core->id.id == 0xFFF)) ||
  273. (ports[1] == 0)) {
  274. bcma_erom_skip_component(bus, eromptr);
  275. return -ENXIO;
  276. }
  277. /* check if component is a core at all */
  278. if (wrappers[0] + wrappers[1] == 0) {
  279. /* Some specific cores don't need wrappers */
  280. switch (core->id.id) {
  281. case BCMA_CORE_4706_MAC_GBIT_COMMON:
  282. /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
  283. break;
  284. default:
  285. bcma_erom_skip_component(bus, eromptr);
  286. return -ENXIO;
  287. }
  288. }
  289. if (bcma_erom_is_bridge(bus, eromptr)) {
  290. bcma_erom_skip_component(bus, eromptr);
  291. return -ENXIO;
  292. }
  293. if (bcma_find_core_by_index(bus, core_num)) {
  294. bcma_erom_skip_component(bus, eromptr);
  295. return -ENODEV;
  296. }
  297. if (match && ((match->manuf != BCMA_ANY_MANUF &&
  298. match->manuf != core->id.manuf) ||
  299. (match->id != BCMA_ANY_ID && match->id != core->id.id) ||
  300. (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
  301. (match->class != BCMA_ANY_CLASS && match->class != core->id.class)
  302. )) {
  303. bcma_erom_skip_component(bus, eromptr);
  304. return -ENODEV;
  305. }
  306. /* get & parse master ports */
  307. for (i = 0; i < ports[0]; i++) {
  308. s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
  309. if (mst_port_d < 0)
  310. return -EILSEQ;
  311. }
  312. /* First Slave Address Descriptor should be port 0:
  313. * the main register space for the core
  314. */
  315. tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
  316. if (tmp == 0 || IS_ERR_VALUE(tmp)) {
  317. /* Try again to see if it is a bridge */
  318. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  319. SCAN_ADDR_TYPE_BRIDGE, 0);
  320. if (tmp == 0 || IS_ERR_VALUE(tmp)) {
  321. return -EILSEQ;
  322. } else {
  323. bcma_info(bus, "Bridge found\n");
  324. return -ENXIO;
  325. }
  326. }
  327. core->addr = tmp;
  328. /* get & parse slave ports */
  329. for (i = 0; i < ports[1]; i++) {
  330. for (j = 0; ; j++) {
  331. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  332. SCAN_ADDR_TYPE_SLAVE, i);
  333. if (IS_ERR_VALUE(tmp)) {
  334. /* no more entries for port _i_ */
  335. /* pr_debug("erom: slave port %d "
  336. * "has %d descriptors\n", i, j); */
  337. break;
  338. } else {
  339. if (i == 0 && j == 0)
  340. core->addr1 = tmp;
  341. }
  342. }
  343. }
  344. /* get & parse master wrappers */
  345. for (i = 0; i < wrappers[0]; i++) {
  346. for (j = 0; ; j++) {
  347. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  348. SCAN_ADDR_TYPE_MWRAP, i);
  349. if (IS_ERR_VALUE(tmp)) {
  350. /* no more entries for port _i_ */
  351. /* pr_debug("erom: master wrapper %d "
  352. * "has %d descriptors\n", i, j); */
  353. break;
  354. } else {
  355. if (i == 0 && j == 0)
  356. core->wrap = tmp;
  357. }
  358. }
  359. }
  360. /* get & parse slave wrappers */
  361. for (i = 0; i < wrappers[1]; i++) {
  362. u8 hack = (ports[1] == 1) ? 0 : 1;
  363. for (j = 0; ; j++) {
  364. tmp = bcma_erom_get_addr_desc(bus, eromptr,
  365. SCAN_ADDR_TYPE_SWRAP, i + hack);
  366. if (IS_ERR_VALUE(tmp)) {
  367. /* no more entries for port _i_ */
  368. /* pr_debug("erom: master wrapper %d "
  369. * has %d descriptors\n", i, j); */
  370. break;
  371. } else {
  372. if (wrappers[0] == 0 && !i && !j)
  373. core->wrap = tmp;
  374. }
  375. }
  376. }
  377. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  378. core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
  379. if (!core->io_addr)
  380. return -ENOMEM;
  381. core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
  382. if (!core->io_wrap) {
  383. iounmap(core->io_addr);
  384. return -ENOMEM;
  385. }
  386. }
  387. return 0;
  388. }
  389. void bcma_init_bus(struct bcma_bus *bus)
  390. {
  391. s32 tmp;
  392. struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
  393. if (bus->init_done)
  394. return;
  395. INIT_LIST_HEAD(&bus->cores);
  396. bus->nr_cores = 0;
  397. bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
  398. tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
  399. chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
  400. chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
  401. chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
  402. bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
  403. chipinfo->id, chipinfo->rev, chipinfo->pkg);
  404. bus->init_done = true;
  405. }
  406. int bcma_bus_scan(struct bcma_bus *bus)
  407. {
  408. u32 erombase;
  409. u32 __iomem *eromptr, *eromend;
  410. int err, core_num = 0;
  411. bcma_init_bus(bus);
  412. erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
  413. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  414. eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
  415. if (!eromptr)
  416. return -ENOMEM;
  417. } else {
  418. eromptr = bus->mmio;
  419. }
  420. eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
  421. bcma_scan_switch_core(bus, erombase);
  422. while (eromptr < eromend) {
  423. struct bcma_device *other_core;
  424. struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
  425. if (!core) {
  426. err = -ENOMEM;
  427. goto out;
  428. }
  429. INIT_LIST_HEAD(&core->list);
  430. core->bus = bus;
  431. err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
  432. if (err < 0) {
  433. kfree(core);
  434. if (err == -ENODEV) {
  435. core_num++;
  436. continue;
  437. } else if (err == -ENXIO) {
  438. continue;
  439. } else if (err == -ESPIPE) {
  440. break;
  441. }
  442. goto out;
  443. }
  444. core->core_index = core_num++;
  445. bus->nr_cores++;
  446. other_core = bcma_find_core_reverse(bus, core->id.id);
  447. core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
  448. bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
  449. core->core_index, bcma_device_name(&core->id),
  450. core->id.manuf, core->id.id, core->id.rev,
  451. core->id.class);
  452. list_add_tail(&core->list, &bus->cores);
  453. }
  454. err = 0;
  455. out:
  456. if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  457. iounmap(eromptr);
  458. return err;
  459. }
  460. int __init bcma_bus_scan_early(struct bcma_bus *bus,
  461. struct bcma_device_id *match,
  462. struct bcma_device *core)
  463. {
  464. u32 erombase;
  465. u32 __iomem *eromptr, *eromend;
  466. int err = -ENODEV;
  467. int core_num = 0;
  468. erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
  469. if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
  470. eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
  471. if (!eromptr)
  472. return -ENOMEM;
  473. } else {
  474. eromptr = bus->mmio;
  475. }
  476. eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
  477. bcma_scan_switch_core(bus, erombase);
  478. while (eromptr < eromend) {
  479. memset(core, 0, sizeof(*core));
  480. INIT_LIST_HEAD(&core->list);
  481. core->bus = bus;
  482. err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
  483. if (err == -ENODEV) {
  484. core_num++;
  485. continue;
  486. } else if (err == -ENXIO)
  487. continue;
  488. else if (err == -ESPIPE)
  489. break;
  490. else if (err < 0)
  491. goto out;
  492. core->core_index = core_num++;
  493. bus->nr_cores++;
  494. bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
  495. core->core_index, bcma_device_name(&core->id),
  496. core->id.manuf, core->id.id, core->id.rev,
  497. core->id.class);
  498. list_add_tail(&core->list, &bus->cores);
  499. err = 0;
  500. break;
  501. }
  502. out:
  503. if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  504. iounmap(eromptr);
  505. return err;
  506. }