setup.c 23 KB

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  1. /*
  2. * linux/arch/sh/boards/se/7724/setup.c
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. *
  6. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mmc/host.h>
  17. #include <linux/mmc/sh_mobile_sdhi.h>
  18. #include <linux/mtd/physmap.h>
  19. #include <linux/delay.h>
  20. #include <linux/regulator/fixed.h>
  21. #include <linux/regulator/machine.h>
  22. #include <linux/smc91x.h>
  23. #include <linux/gpio.h>
  24. #include <linux/input.h>
  25. #include <linux/input/sh_keysc.h>
  26. #include <linux/usb/r8a66597.h>
  27. #include <linux/sh_eth.h>
  28. #include <linux/sh_intc.h>
  29. #include <linux/videodev2.h>
  30. #include <video/sh_mobile_lcdc.h>
  31. #include <media/sh_mobile_ceu.h>
  32. #include <sound/sh_fsi.h>
  33. #include <sound/simple_card.h>
  34. #include <asm/io.h>
  35. #include <asm/heartbeat.h>
  36. #include <asm/clock.h>
  37. #include <asm/suspend.h>
  38. #include <cpu/sh7724.h>
  39. #include <mach-se/mach/se7724.h>
  40. /*
  41. * SWx 1234 5678
  42. * ------------------------------------
  43. * SW31 : 1001 1100 : default
  44. * SW32 : 0111 1111 : use on board flash
  45. *
  46. * SW41 : abxx xxxx -> a = 0 : Analog monitor
  47. * 1 : Digital monitor
  48. * b = 0 : VGA
  49. * 1 : 720p
  50. */
  51. /*
  52. * about 720p
  53. *
  54. * When you use 1280 x 720 lcdc output,
  55. * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
  56. * and change SW41 to use 720p
  57. */
  58. /*
  59. * about sound
  60. *
  61. * This setup.c supports FSI slave mode.
  62. * Please change J20, J21, J22 pin to 1-2 connection.
  63. */
  64. /* Heartbeat */
  65. static struct resource heartbeat_resource = {
  66. .start = PA_LED,
  67. .end = PA_LED,
  68. .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
  69. };
  70. static struct platform_device heartbeat_device = {
  71. .name = "heartbeat",
  72. .id = -1,
  73. .num_resources = 1,
  74. .resource = &heartbeat_resource,
  75. };
  76. /* LAN91C111 */
  77. static struct smc91x_platdata smc91x_info = {
  78. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  79. };
  80. static struct resource smc91x_eth_resources[] = {
  81. [0] = {
  82. .name = "SMC91C111" ,
  83. .start = 0x1a300300,
  84. .end = 0x1a30030f,
  85. .flags = IORESOURCE_MEM,
  86. },
  87. [1] = {
  88. .start = IRQ0_SMC,
  89. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  90. },
  91. };
  92. static struct platform_device smc91x_eth_device = {
  93. .name = "smc91x",
  94. .num_resources = ARRAY_SIZE(smc91x_eth_resources),
  95. .resource = smc91x_eth_resources,
  96. .dev = {
  97. .platform_data = &smc91x_info,
  98. },
  99. };
  100. /* MTD */
  101. static struct mtd_partition nor_flash_partitions[] = {
  102. {
  103. .name = "uboot",
  104. .offset = 0,
  105. .size = (1 * 1024 * 1024),
  106. .mask_flags = MTD_WRITEABLE, /* Read-only */
  107. }, {
  108. .name = "kernel",
  109. .offset = MTDPART_OFS_APPEND,
  110. .size = (2 * 1024 * 1024),
  111. }, {
  112. .name = "free-area",
  113. .offset = MTDPART_OFS_APPEND,
  114. .size = MTDPART_SIZ_FULL,
  115. },
  116. };
  117. static struct physmap_flash_data nor_flash_data = {
  118. .width = 2,
  119. .parts = nor_flash_partitions,
  120. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  121. };
  122. static struct resource nor_flash_resources[] = {
  123. [0] = {
  124. .name = "NOR Flash",
  125. .start = 0x00000000,
  126. .end = 0x01ffffff,
  127. .flags = IORESOURCE_MEM,
  128. }
  129. };
  130. static struct platform_device nor_flash_device = {
  131. .name = "physmap-flash",
  132. .resource = nor_flash_resources,
  133. .num_resources = ARRAY_SIZE(nor_flash_resources),
  134. .dev = {
  135. .platform_data = &nor_flash_data,
  136. },
  137. };
  138. /* LCDC */
  139. static const struct fb_videomode lcdc_720p_modes[] = {
  140. {
  141. .name = "LB070WV1",
  142. .sync = 0, /* hsync and vsync are active low */
  143. .xres = 1280,
  144. .yres = 720,
  145. .left_margin = 220,
  146. .right_margin = 110,
  147. .hsync_len = 40,
  148. .upper_margin = 20,
  149. .lower_margin = 5,
  150. .vsync_len = 5,
  151. },
  152. };
  153. static const struct fb_videomode lcdc_vga_modes[] = {
  154. {
  155. .name = "LB070WV1",
  156. .sync = 0, /* hsync and vsync are active low */
  157. .xres = 640,
  158. .yres = 480,
  159. .left_margin = 105,
  160. .right_margin = 50,
  161. .hsync_len = 96,
  162. .upper_margin = 33,
  163. .lower_margin = 10,
  164. .vsync_len = 2,
  165. },
  166. };
  167. static struct sh_mobile_lcdc_info lcdc_info = {
  168. .clock_source = LCDC_CLK_EXTERNAL,
  169. .ch[0] = {
  170. .chan = LCDC_CHAN_MAINLCD,
  171. .fourcc = V4L2_PIX_FMT_RGB565,
  172. .clock_divider = 1,
  173. .panel_cfg = { /* 7.0 inch */
  174. .width = 152,
  175. .height = 91,
  176. },
  177. }
  178. };
  179. static struct resource lcdc_resources[] = {
  180. [0] = {
  181. .name = "LCDC",
  182. .start = 0xfe940000,
  183. .end = 0xfe942fff,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. [1] = {
  187. .start = evt2irq(0xf40),
  188. .flags = IORESOURCE_IRQ,
  189. },
  190. };
  191. static struct platform_device lcdc_device = {
  192. .name = "sh_mobile_lcdc_fb",
  193. .num_resources = ARRAY_SIZE(lcdc_resources),
  194. .resource = lcdc_resources,
  195. .dev = {
  196. .platform_data = &lcdc_info,
  197. },
  198. };
  199. /* CEU0 */
  200. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  201. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  202. };
  203. static struct resource ceu0_resources[] = {
  204. [0] = {
  205. .name = "CEU0",
  206. .start = 0xfe910000,
  207. .end = 0xfe91009f,
  208. .flags = IORESOURCE_MEM,
  209. },
  210. [1] = {
  211. .start = evt2irq(0x880),
  212. .flags = IORESOURCE_IRQ,
  213. },
  214. [2] = {
  215. /* place holder for contiguous memory */
  216. },
  217. };
  218. static struct platform_device ceu0_device = {
  219. .name = "sh_mobile_ceu",
  220. .id = 0, /* "ceu0" clock */
  221. .num_resources = ARRAY_SIZE(ceu0_resources),
  222. .resource = ceu0_resources,
  223. .dev = {
  224. .platform_data = &sh_mobile_ceu0_info,
  225. },
  226. };
  227. /* CEU1 */
  228. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  229. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  230. };
  231. static struct resource ceu1_resources[] = {
  232. [0] = {
  233. .name = "CEU1",
  234. .start = 0xfe914000,
  235. .end = 0xfe91409f,
  236. .flags = IORESOURCE_MEM,
  237. },
  238. [1] = {
  239. .start = evt2irq(0x9e0),
  240. .flags = IORESOURCE_IRQ,
  241. },
  242. [2] = {
  243. /* place holder for contiguous memory */
  244. },
  245. };
  246. static struct platform_device ceu1_device = {
  247. .name = "sh_mobile_ceu",
  248. .id = 1, /* "ceu1" clock */
  249. .num_resources = ARRAY_SIZE(ceu1_resources),
  250. .resource = ceu1_resources,
  251. .dev = {
  252. .platform_data = &sh_mobile_ceu1_info,
  253. },
  254. };
  255. /* FSI */
  256. /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
  257. static struct resource fsi_resources[] = {
  258. [0] = {
  259. .name = "FSI",
  260. .start = 0xFE3C0000,
  261. .end = 0xFE3C021d,
  262. .flags = IORESOURCE_MEM,
  263. },
  264. [1] = {
  265. .start = evt2irq(0xf80),
  266. .flags = IORESOURCE_IRQ,
  267. },
  268. };
  269. static struct platform_device fsi_device = {
  270. .name = "sh_fsi",
  271. .id = 0,
  272. .num_resources = ARRAY_SIZE(fsi_resources),
  273. .resource = fsi_resources,
  274. };
  275. static struct asoc_simple_card_info fsi_ak4642_info = {
  276. .name = "AK4642",
  277. .card = "FSIA-AK4642",
  278. .codec = "ak4642-codec.0-0012",
  279. .platform = "sh_fsi.0",
  280. .daifmt = SND_SOC_DAIFMT_LEFT_J,
  281. .cpu_dai = {
  282. .name = "fsia-dai",
  283. .fmt = SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_IB_NF,
  284. },
  285. .codec_dai = {
  286. .name = "ak4642-hifi",
  287. .fmt = SND_SOC_DAIFMT_CBM_CFM,
  288. .sysclk = 11289600,
  289. },
  290. };
  291. static struct platform_device fsi_ak4642_device = {
  292. .name = "asoc-simple-card",
  293. .dev = {
  294. .platform_data = &fsi_ak4642_info,
  295. },
  296. };
  297. /* KEYSC in SoC (Needs SW33-2 set to ON) */
  298. static struct sh_keysc_info keysc_info = {
  299. .mode = SH_KEYSC_MODE_1,
  300. .scan_timing = 3,
  301. .delay = 50,
  302. .keycodes = {
  303. KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
  304. KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
  305. KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
  306. KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
  307. KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
  308. KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
  309. },
  310. };
  311. static struct resource keysc_resources[] = {
  312. [0] = {
  313. .name = "KEYSC",
  314. .start = 0x044b0000,
  315. .end = 0x044b000f,
  316. .flags = IORESOURCE_MEM,
  317. },
  318. [1] = {
  319. .start = evt2irq(0xbe0),
  320. .flags = IORESOURCE_IRQ,
  321. },
  322. };
  323. static struct platform_device keysc_device = {
  324. .name = "sh_keysc",
  325. .id = 0, /* "keysc0" clock */
  326. .num_resources = ARRAY_SIZE(keysc_resources),
  327. .resource = keysc_resources,
  328. .dev = {
  329. .platform_data = &keysc_info,
  330. },
  331. };
  332. /* SH Eth */
  333. static struct resource sh_eth_resources[] = {
  334. [0] = {
  335. .start = SH_ETH_ADDR,
  336. .end = SH_ETH_ADDR + 0x1FC - 1,
  337. .flags = IORESOURCE_MEM,
  338. },
  339. [1] = {
  340. .start = evt2irq(0xd60),
  341. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  342. },
  343. };
  344. static struct sh_eth_plat_data sh_eth_plat = {
  345. .phy = 0x1f, /* SMSC LAN8187 */
  346. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  347. .phy_interface = PHY_INTERFACE_MODE_MII,
  348. };
  349. static struct platform_device sh_eth_device = {
  350. .name = "sh7724-ether",
  351. .id = 0,
  352. .dev = {
  353. .platform_data = &sh_eth_plat,
  354. },
  355. .num_resources = ARRAY_SIZE(sh_eth_resources),
  356. .resource = sh_eth_resources,
  357. };
  358. static struct r8a66597_platdata sh7724_usb0_host_data = {
  359. .on_chip = 1,
  360. };
  361. static struct resource sh7724_usb0_host_resources[] = {
  362. [0] = {
  363. .start = 0xa4d80000,
  364. .end = 0xa4d80124 - 1,
  365. .flags = IORESOURCE_MEM,
  366. },
  367. [1] = {
  368. .start = evt2irq(0xa20),
  369. .end = evt2irq(0xa20),
  370. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  371. },
  372. };
  373. static struct platform_device sh7724_usb0_host_device = {
  374. .name = "r8a66597_hcd",
  375. .id = 0,
  376. .dev = {
  377. .dma_mask = NULL, /* not use dma */
  378. .coherent_dma_mask = 0xffffffff,
  379. .platform_data = &sh7724_usb0_host_data,
  380. },
  381. .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
  382. .resource = sh7724_usb0_host_resources,
  383. };
  384. static struct r8a66597_platdata sh7724_usb1_gadget_data = {
  385. .on_chip = 1,
  386. };
  387. static struct resource sh7724_usb1_gadget_resources[] = {
  388. [0] = {
  389. .start = 0xa4d90000,
  390. .end = 0xa4d90123,
  391. .flags = IORESOURCE_MEM,
  392. },
  393. [1] = {
  394. .start = evt2irq(0xa40),
  395. .end = evt2irq(0xa40),
  396. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  397. },
  398. };
  399. static struct platform_device sh7724_usb1_gadget_device = {
  400. .name = "r8a66597_udc",
  401. .id = 1, /* USB1 */
  402. .dev = {
  403. .dma_mask = NULL, /* not use dma */
  404. .coherent_dma_mask = 0xffffffff,
  405. .platform_data = &sh7724_usb1_gadget_data,
  406. },
  407. .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
  408. .resource = sh7724_usb1_gadget_resources,
  409. };
  410. /* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
  411. static struct regulator_consumer_supply fixed3v3_power_consumers[] =
  412. {
  413. REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
  414. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
  415. REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
  416. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
  417. };
  418. static struct resource sdhi0_cn7_resources[] = {
  419. [0] = {
  420. .name = "SDHI0",
  421. .start = 0x04ce0000,
  422. .end = 0x04ce00ff,
  423. .flags = IORESOURCE_MEM,
  424. },
  425. [1] = {
  426. .start = evt2irq(0xe80),
  427. .flags = IORESOURCE_IRQ,
  428. },
  429. };
  430. static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
  431. .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
  432. .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
  433. .tmio_caps = MMC_CAP_SDIO_IRQ,
  434. };
  435. static struct platform_device sdhi0_cn7_device = {
  436. .name = "sh_mobile_sdhi",
  437. .id = 0,
  438. .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
  439. .resource = sdhi0_cn7_resources,
  440. .dev = {
  441. .platform_data = &sh7724_sdhi0_data,
  442. },
  443. };
  444. static struct resource sdhi1_cn8_resources[] = {
  445. [0] = {
  446. .name = "SDHI1",
  447. .start = 0x04cf0000,
  448. .end = 0x04cf00ff,
  449. .flags = IORESOURCE_MEM,
  450. },
  451. [1] = {
  452. .start = evt2irq(0x4e0),
  453. .flags = IORESOURCE_IRQ,
  454. },
  455. };
  456. static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
  457. .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
  458. .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
  459. .tmio_caps = MMC_CAP_SDIO_IRQ,
  460. };
  461. static struct platform_device sdhi1_cn8_device = {
  462. .name = "sh_mobile_sdhi",
  463. .id = 1,
  464. .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
  465. .resource = sdhi1_cn8_resources,
  466. .dev = {
  467. .platform_data = &sh7724_sdhi1_data,
  468. },
  469. };
  470. /* IrDA */
  471. static struct resource irda_resources[] = {
  472. [0] = {
  473. .name = "IrDA",
  474. .start = 0xA45D0000,
  475. .end = 0xA45D0049,
  476. .flags = IORESOURCE_MEM,
  477. },
  478. [1] = {
  479. .start = evt2irq(0x480),
  480. .flags = IORESOURCE_IRQ,
  481. },
  482. };
  483. static struct platform_device irda_device = {
  484. .name = "sh_sir",
  485. .num_resources = ARRAY_SIZE(irda_resources),
  486. .resource = irda_resources,
  487. };
  488. #include <media/ak881x.h>
  489. #include <media/sh_vou.h>
  490. static struct ak881x_pdata ak881x_pdata = {
  491. .flags = AK881X_IF_MODE_SLAVE,
  492. };
  493. static struct i2c_board_info ak8813 = {
  494. /* With open J18 jumper address is 0x21 */
  495. I2C_BOARD_INFO("ak8813", 0x20),
  496. .platform_data = &ak881x_pdata,
  497. };
  498. static struct sh_vou_pdata sh_vou_pdata = {
  499. .bus_fmt = SH_VOU_BUS_8BIT,
  500. .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
  501. .board_info = &ak8813,
  502. .i2c_adap = 0,
  503. };
  504. static struct resource sh_vou_resources[] = {
  505. [0] = {
  506. .start = 0xfe960000,
  507. .end = 0xfe962043,
  508. .flags = IORESOURCE_MEM,
  509. },
  510. [1] = {
  511. .start = evt2irq(0x8e0),
  512. .flags = IORESOURCE_IRQ,
  513. },
  514. };
  515. static struct platform_device vou_device = {
  516. .name = "sh-vou",
  517. .id = -1,
  518. .num_resources = ARRAY_SIZE(sh_vou_resources),
  519. .resource = sh_vou_resources,
  520. .dev = {
  521. .platform_data = &sh_vou_pdata,
  522. },
  523. };
  524. static struct platform_device *ms7724se_devices[] __initdata = {
  525. &heartbeat_device,
  526. &smc91x_eth_device,
  527. &lcdc_device,
  528. &nor_flash_device,
  529. &ceu0_device,
  530. &ceu1_device,
  531. &keysc_device,
  532. &sh_eth_device,
  533. &sh7724_usb0_host_device,
  534. &sh7724_usb1_gadget_device,
  535. &fsi_device,
  536. &fsi_ak4642_device,
  537. &sdhi0_cn7_device,
  538. &sdhi1_cn8_device,
  539. &irda_device,
  540. &vou_device,
  541. };
  542. /* I2C device */
  543. static struct i2c_board_info i2c0_devices[] = {
  544. {
  545. I2C_BOARD_INFO("ak4642", 0x12),
  546. },
  547. };
  548. #define EEPROM_OP 0xBA206000
  549. #define EEPROM_ADR 0xBA206004
  550. #define EEPROM_DATA 0xBA20600C
  551. #define EEPROM_STAT 0xBA206010
  552. #define EEPROM_STRT 0xBA206014
  553. static int __init sh_eth_is_eeprom_ready(void)
  554. {
  555. int t = 10000;
  556. while (t--) {
  557. if (!__raw_readw(EEPROM_STAT))
  558. return 1;
  559. udelay(1);
  560. }
  561. printk(KERN_ERR "ms7724se can not access to eeprom\n");
  562. return 0;
  563. }
  564. static void __init sh_eth_init(void)
  565. {
  566. int i;
  567. u16 mac;
  568. /* check EEPROM status */
  569. if (!sh_eth_is_eeprom_ready())
  570. return;
  571. /* read MAC addr from EEPROM */
  572. for (i = 0 ; i < 3 ; i++) {
  573. __raw_writew(0x0, EEPROM_OP); /* read */
  574. __raw_writew(i*2, EEPROM_ADR);
  575. __raw_writew(0x1, EEPROM_STRT);
  576. if (!sh_eth_is_eeprom_ready())
  577. return;
  578. mac = __raw_readw(EEPROM_DATA);
  579. sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
  580. sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
  581. }
  582. }
  583. #define SW4140 0xBA201000
  584. #define FPGA_OUT 0xBA200400
  585. #define PORT_HIZA 0xA4050158
  586. #define PORT_MSELCRB 0xA4050182
  587. #define SW41_A 0x0100
  588. #define SW41_B 0x0200
  589. #define SW41_C 0x0400
  590. #define SW41_D 0x0800
  591. #define SW41_E 0x1000
  592. #define SW41_F 0x2000
  593. #define SW41_G 0x4000
  594. #define SW41_H 0x8000
  595. extern char ms7724se_sdram_enter_start;
  596. extern char ms7724se_sdram_enter_end;
  597. extern char ms7724se_sdram_leave_start;
  598. extern char ms7724se_sdram_leave_end;
  599. static int __init arch_setup(void)
  600. {
  601. /* enable I2C device */
  602. i2c_register_board_info(0, i2c0_devices,
  603. ARRAY_SIZE(i2c0_devices));
  604. return 0;
  605. }
  606. arch_initcall(arch_setup);
  607. static int __init devices_setup(void)
  608. {
  609. u16 sw = __raw_readw(SW4140); /* select camera, monitor */
  610. struct clk *clk;
  611. u16 fpga_out;
  612. /* register board specific self-refresh code */
  613. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
  614. SUSP_SH_RSTANDBY,
  615. &ms7724se_sdram_enter_start,
  616. &ms7724se_sdram_enter_end,
  617. &ms7724se_sdram_leave_start,
  618. &ms7724se_sdram_leave_end);
  619. regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
  620. ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
  621. /* Reset Release */
  622. fpga_out = __raw_readw(FPGA_OUT);
  623. /* bit4: NTSC_PDN, bit5: NTSC_RESET */
  624. fpga_out &= ~((1 << 1) | /* LAN */
  625. (1 << 4) | /* AK8813 PDN */
  626. (1 << 5) | /* AK8813 RESET */
  627. (1 << 6) | /* VIDEO DAC */
  628. (1 << 7) | /* AK4643 */
  629. (1 << 8) | /* IrDA */
  630. (1 << 12) | /* USB0 */
  631. (1 << 14)); /* RMII */
  632. __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
  633. udelay(10);
  634. /* AK8813 RESET */
  635. __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
  636. udelay(10);
  637. __raw_writew(fpga_out, FPGA_OUT);
  638. /* turn on USB clocks, use external clock */
  639. __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
  640. /* Let LED9 show STATUS2 */
  641. gpio_request(GPIO_FN_STATUS2, NULL);
  642. /* Lit LED10 show STATUS0 */
  643. gpio_request(GPIO_FN_STATUS0, NULL);
  644. /* Lit LED11 show PDSTATUS */
  645. gpio_request(GPIO_FN_PDSTATUS, NULL);
  646. /* enable USB0 port */
  647. __raw_writew(0x0600, 0xa40501d4);
  648. /* enable USB1 port */
  649. __raw_writew(0x0600, 0xa4050192);
  650. /* enable IRQ 0,1,2 */
  651. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  652. gpio_request(GPIO_FN_INTC_IRQ1, NULL);
  653. gpio_request(GPIO_FN_INTC_IRQ2, NULL);
  654. /* enable SCIFA3 */
  655. gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
  656. gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
  657. gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
  658. gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
  659. gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
  660. /* enable LCDC */
  661. gpio_request(GPIO_FN_LCDD23, NULL);
  662. gpio_request(GPIO_FN_LCDD22, NULL);
  663. gpio_request(GPIO_FN_LCDD21, NULL);
  664. gpio_request(GPIO_FN_LCDD20, NULL);
  665. gpio_request(GPIO_FN_LCDD19, NULL);
  666. gpio_request(GPIO_FN_LCDD18, NULL);
  667. gpio_request(GPIO_FN_LCDD17, NULL);
  668. gpio_request(GPIO_FN_LCDD16, NULL);
  669. gpio_request(GPIO_FN_LCDD15, NULL);
  670. gpio_request(GPIO_FN_LCDD14, NULL);
  671. gpio_request(GPIO_FN_LCDD13, NULL);
  672. gpio_request(GPIO_FN_LCDD12, NULL);
  673. gpio_request(GPIO_FN_LCDD11, NULL);
  674. gpio_request(GPIO_FN_LCDD10, NULL);
  675. gpio_request(GPIO_FN_LCDD9, NULL);
  676. gpio_request(GPIO_FN_LCDD8, NULL);
  677. gpio_request(GPIO_FN_LCDD7, NULL);
  678. gpio_request(GPIO_FN_LCDD6, NULL);
  679. gpio_request(GPIO_FN_LCDD5, NULL);
  680. gpio_request(GPIO_FN_LCDD4, NULL);
  681. gpio_request(GPIO_FN_LCDD3, NULL);
  682. gpio_request(GPIO_FN_LCDD2, NULL);
  683. gpio_request(GPIO_FN_LCDD1, NULL);
  684. gpio_request(GPIO_FN_LCDD0, NULL);
  685. gpio_request(GPIO_FN_LCDDISP, NULL);
  686. gpio_request(GPIO_FN_LCDHSYN, NULL);
  687. gpio_request(GPIO_FN_LCDDCK, NULL);
  688. gpio_request(GPIO_FN_LCDVSYN, NULL);
  689. gpio_request(GPIO_FN_LCDDON, NULL);
  690. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  691. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  692. gpio_request(GPIO_FN_LCDRD, NULL);
  693. gpio_request(GPIO_FN_LCDLCLK, NULL);
  694. __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  695. /* enable CEU0 */
  696. gpio_request(GPIO_FN_VIO0_D15, NULL);
  697. gpio_request(GPIO_FN_VIO0_D14, NULL);
  698. gpio_request(GPIO_FN_VIO0_D13, NULL);
  699. gpio_request(GPIO_FN_VIO0_D12, NULL);
  700. gpio_request(GPIO_FN_VIO0_D11, NULL);
  701. gpio_request(GPIO_FN_VIO0_D10, NULL);
  702. gpio_request(GPIO_FN_VIO0_D9, NULL);
  703. gpio_request(GPIO_FN_VIO0_D8, NULL);
  704. gpio_request(GPIO_FN_VIO0_D7, NULL);
  705. gpio_request(GPIO_FN_VIO0_D6, NULL);
  706. gpio_request(GPIO_FN_VIO0_D5, NULL);
  707. gpio_request(GPIO_FN_VIO0_D4, NULL);
  708. gpio_request(GPIO_FN_VIO0_D3, NULL);
  709. gpio_request(GPIO_FN_VIO0_D2, NULL);
  710. gpio_request(GPIO_FN_VIO0_D1, NULL);
  711. gpio_request(GPIO_FN_VIO0_D0, NULL);
  712. gpio_request(GPIO_FN_VIO0_VD, NULL);
  713. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  714. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  715. gpio_request(GPIO_FN_VIO0_HD, NULL);
  716. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  717. /* enable CEU1 */
  718. gpio_request(GPIO_FN_VIO1_D7, NULL);
  719. gpio_request(GPIO_FN_VIO1_D6, NULL);
  720. gpio_request(GPIO_FN_VIO1_D5, NULL);
  721. gpio_request(GPIO_FN_VIO1_D4, NULL);
  722. gpio_request(GPIO_FN_VIO1_D3, NULL);
  723. gpio_request(GPIO_FN_VIO1_D2, NULL);
  724. gpio_request(GPIO_FN_VIO1_D1, NULL);
  725. gpio_request(GPIO_FN_VIO1_D0, NULL);
  726. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  727. gpio_request(GPIO_FN_VIO1_HD, NULL);
  728. gpio_request(GPIO_FN_VIO1_VD, NULL);
  729. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  730. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  731. /* KEYSC */
  732. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  733. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  734. gpio_request(GPIO_FN_KEYIN4, NULL);
  735. gpio_request(GPIO_FN_KEYIN3, NULL);
  736. gpio_request(GPIO_FN_KEYIN2, NULL);
  737. gpio_request(GPIO_FN_KEYIN1, NULL);
  738. gpio_request(GPIO_FN_KEYIN0, NULL);
  739. gpio_request(GPIO_FN_KEYOUT3, NULL);
  740. gpio_request(GPIO_FN_KEYOUT2, NULL);
  741. gpio_request(GPIO_FN_KEYOUT1, NULL);
  742. gpio_request(GPIO_FN_KEYOUT0, NULL);
  743. /* enable FSI */
  744. gpio_request(GPIO_FN_FSIMCKA, NULL);
  745. gpio_request(GPIO_FN_FSIIASD, NULL);
  746. gpio_request(GPIO_FN_FSIOASD, NULL);
  747. gpio_request(GPIO_FN_FSIIABCK, NULL);
  748. gpio_request(GPIO_FN_FSIIALRCK, NULL);
  749. gpio_request(GPIO_FN_FSIOABCK, NULL);
  750. gpio_request(GPIO_FN_FSIOALRCK, NULL);
  751. gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
  752. /* set SPU2 clock to 83.4 MHz */
  753. clk = clk_get(NULL, "spu_clk");
  754. if (!IS_ERR(clk)) {
  755. clk_set_rate(clk, clk_round_rate(clk, 83333333));
  756. clk_put(clk);
  757. }
  758. /* change parent of FSI A */
  759. clk = clk_get(NULL, "fsia_clk");
  760. if (!IS_ERR(clk)) {
  761. /* 48kHz dummy clock was used to make sure 1/1 divide */
  762. clk_set_rate(&sh7724_fsimcka_clk, 48000);
  763. clk_set_parent(clk, &sh7724_fsimcka_clk);
  764. clk_set_rate(clk, 48000);
  765. clk_put(clk);
  766. }
  767. /* SDHI0 connected to cn7 */
  768. gpio_request(GPIO_FN_SDHI0CD, NULL);
  769. gpio_request(GPIO_FN_SDHI0WP, NULL);
  770. gpio_request(GPIO_FN_SDHI0D3, NULL);
  771. gpio_request(GPIO_FN_SDHI0D2, NULL);
  772. gpio_request(GPIO_FN_SDHI0D1, NULL);
  773. gpio_request(GPIO_FN_SDHI0D0, NULL);
  774. gpio_request(GPIO_FN_SDHI0CMD, NULL);
  775. gpio_request(GPIO_FN_SDHI0CLK, NULL);
  776. /* SDHI1 connected to cn8 */
  777. gpio_request(GPIO_FN_SDHI1CD, NULL);
  778. gpio_request(GPIO_FN_SDHI1WP, NULL);
  779. gpio_request(GPIO_FN_SDHI1D3, NULL);
  780. gpio_request(GPIO_FN_SDHI1D2, NULL);
  781. gpio_request(GPIO_FN_SDHI1D1, NULL);
  782. gpio_request(GPIO_FN_SDHI1D0, NULL);
  783. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  784. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  785. /* enable IrDA */
  786. gpio_request(GPIO_FN_IRDA_OUT, NULL);
  787. gpio_request(GPIO_FN_IRDA_IN, NULL);
  788. /*
  789. * enable SH-Eth
  790. *
  791. * please remove J33 pin from your board !!
  792. *
  793. * ms7724 board should not use GPIO_FN_LNKSTA pin
  794. * So, This time PTX5 is set to input pin
  795. */
  796. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  797. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  798. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  799. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  800. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  801. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  802. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  803. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  804. gpio_request(GPIO_FN_MDIO, NULL);
  805. gpio_request(GPIO_FN_MDC, NULL);
  806. gpio_request(GPIO_PTX5, NULL);
  807. gpio_direction_input(GPIO_PTX5);
  808. sh_eth_init();
  809. if (sw & SW41_B) {
  810. /* 720p */
  811. lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
  812. lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
  813. } else {
  814. /* VGA */
  815. lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
  816. lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
  817. }
  818. if (sw & SW41_A) {
  819. /* Digital monitor */
  820. lcdc_info.ch[0].interface_type = RGB18;
  821. lcdc_info.ch[0].flags = 0;
  822. } else {
  823. /* Analog monitor */
  824. lcdc_info.ch[0].interface_type = RGB24;
  825. lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
  826. }
  827. /* VOU */
  828. gpio_request(GPIO_FN_DV_D15, NULL);
  829. gpio_request(GPIO_FN_DV_D14, NULL);
  830. gpio_request(GPIO_FN_DV_D13, NULL);
  831. gpio_request(GPIO_FN_DV_D12, NULL);
  832. gpio_request(GPIO_FN_DV_D11, NULL);
  833. gpio_request(GPIO_FN_DV_D10, NULL);
  834. gpio_request(GPIO_FN_DV_D9, NULL);
  835. gpio_request(GPIO_FN_DV_D8, NULL);
  836. gpio_request(GPIO_FN_DV_CLKI, NULL);
  837. gpio_request(GPIO_FN_DV_CLK, NULL);
  838. gpio_request(GPIO_FN_DV_VSYNC, NULL);
  839. gpio_request(GPIO_FN_DV_HSYNC, NULL);
  840. return platform_add_devices(ms7724se_devices,
  841. ARRAY_SIZE(ms7724se_devices));
  842. }
  843. device_initcall(devices_setup);
  844. static struct sh_machine_vector mv_ms7724se __initmv = {
  845. .mv_name = "ms7724se",
  846. .mv_init_irq = init_se7724_IRQ,
  847. };