Kconfig 9.7 KB

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  1. menu "Platform support"
  2. source "arch/powerpc/platforms/powernv/Kconfig"
  3. source "arch/powerpc/platforms/pseries/Kconfig"
  4. source "arch/powerpc/platforms/chrp/Kconfig"
  5. source "arch/powerpc/platforms/512x/Kconfig"
  6. source "arch/powerpc/platforms/52xx/Kconfig"
  7. source "arch/powerpc/platforms/powermac/Kconfig"
  8. source "arch/powerpc/platforms/maple/Kconfig"
  9. source "arch/powerpc/platforms/pasemi/Kconfig"
  10. source "arch/powerpc/platforms/ps3/Kconfig"
  11. source "arch/powerpc/platforms/cell/Kconfig"
  12. source "arch/powerpc/platforms/8xx/Kconfig"
  13. source "arch/powerpc/platforms/82xx/Kconfig"
  14. source "arch/powerpc/platforms/83xx/Kconfig"
  15. source "arch/powerpc/platforms/85xx/Kconfig"
  16. source "arch/powerpc/platforms/86xx/Kconfig"
  17. source "arch/powerpc/platforms/embedded6xx/Kconfig"
  18. source "arch/powerpc/platforms/44x/Kconfig"
  19. source "arch/powerpc/platforms/40x/Kconfig"
  20. source "arch/powerpc/platforms/amigaone/Kconfig"
  21. source "arch/powerpc/platforms/wsp/Kconfig"
  22. config KVM_GUEST
  23. bool "KVM Guest support"
  24. default n
  25. select EPAPR_PARAVIRT
  26. ---help---
  27. This option enables various optimizations for running under the KVM
  28. hypervisor. Overhead for the kernel when not running inside KVM should
  29. be minimal.
  30. In case of doubt, say Y
  31. config EPAPR_PARAVIRT
  32. bool "ePAPR para-virtualization support"
  33. default n
  34. help
  35. Enables ePAPR para-virtualization support for guests.
  36. In case of doubt, say Y
  37. config PPC_NATIVE
  38. bool
  39. depends on 6xx || PPC64
  40. help
  41. Support for running natively on the hardware, i.e. without
  42. a hypervisor. This option is not user-selectable but should
  43. be selected by all platforms that need it.
  44. config PPC_OF_BOOT_TRAMPOLINE
  45. bool "Support booting from Open Firmware or yaboot"
  46. depends on 6xx || PPC64
  47. default y
  48. help
  49. Support from booting from Open Firmware or yaboot using an
  50. Open Firmware client interface. This enables the kernel to
  51. communicate with open firmware to retrieve system information
  52. such as the device tree.
  53. In case of doubt, say Y
  54. config UDBG_RTAS_CONSOLE
  55. bool "RTAS based debug console"
  56. depends on PPC_RTAS
  57. default n
  58. config PPC_SMP_MUXED_IPI
  59. bool
  60. help
  61. Select this opton if your platform supports SMP and your
  62. interrupt controller provides less than 4 interrupts to each
  63. cpu. This will enable the generic code to multiplex the 4
  64. messages on to one ipi.
  65. config PPC_UDBG_BEAT
  66. bool "BEAT based debug console"
  67. depends on PPC_CELLEB
  68. default n
  69. config IPIC
  70. bool
  71. default n
  72. config MPIC
  73. bool
  74. default n
  75. config MPIC_TIMER
  76. bool "MPIC Global Timer"
  77. depends on MPIC && FSL_SOC
  78. default n
  79. help
  80. The MPIC global timer is a hardware timer inside the
  81. Freescale PIC complying with OpenPIC standard. When the
  82. specified interval times out, the hardware timer generates
  83. an interrupt. The driver currently is only tested on fsl
  84. chip, but it can potentially support other global timers
  85. complying with the OpenPIC standard.
  86. config FSL_MPIC_TIMER_WAKEUP
  87. tristate "Freescale MPIC global timer wakeup driver"
  88. depends on FSL_SOC && MPIC_TIMER && PM
  89. default n
  90. help
  91. The driver provides a way to wake up the system by MPIC
  92. timer.
  93. e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
  94. config PPC_EPAPR_HV_PIC
  95. bool
  96. default n
  97. select EPAPR_PARAVIRT
  98. config MPIC_WEIRD
  99. bool
  100. default n
  101. config MPIC_MSGR
  102. bool "MPIC message register support"
  103. depends on MPIC
  104. default n
  105. help
  106. Enables support for the MPIC message registers. These
  107. registers are used for inter-processor communication.
  108. config PPC_I8259
  109. bool
  110. default n
  111. config U3_DART
  112. bool
  113. depends on PPC64
  114. default n
  115. config PPC_RTAS
  116. bool
  117. default n
  118. config RTAS_ERROR_LOGGING
  119. bool
  120. depends on PPC_RTAS
  121. default n
  122. config PPC_RTAS_DAEMON
  123. bool
  124. depends on PPC_RTAS
  125. default n
  126. config RTAS_PROC
  127. bool "Proc interface to RTAS"
  128. depends on PPC_RTAS && PROC_FS
  129. default y
  130. config RTAS_FLASH
  131. tristate "Firmware flash interface"
  132. depends on PPC64 && RTAS_PROC
  133. config MMIO_NVRAM
  134. bool
  135. default n
  136. config MPIC_U3_HT_IRQS
  137. bool
  138. default n
  139. config MPIC_BROKEN_REGREAD
  140. bool
  141. depends on MPIC
  142. help
  143. This option enables a MPIC driver workaround for some chips
  144. that have a bug that causes some interrupt source information
  145. to not read back properly. It is safe to use on other chips as
  146. well, but enabling it uses about 8KB of memory to keep copies
  147. of the register contents in software.
  148. config IBMVIO
  149. depends on PPC_PSERIES
  150. bool
  151. default y
  152. config IBMEBUS
  153. depends on PPC_PSERIES
  154. bool "Support for GX bus based adapters"
  155. help
  156. Bus device driver for GX bus based adapters.
  157. config EEH
  158. bool
  159. depends on (PPC_POWERNV || PPC_PSERIES) && PCI
  160. default y
  161. config PPC_MPC106
  162. bool
  163. default n
  164. config PPC_970_NAP
  165. bool
  166. default n
  167. config PPC_P7_NAP
  168. bool
  169. default n
  170. config PPC_INDIRECT_PIO
  171. bool
  172. select GENERIC_IOMAP
  173. config PPC_INDIRECT_MMIO
  174. bool
  175. config PPC_IO_WORKAROUNDS
  176. bool
  177. source "drivers/cpufreq/Kconfig"
  178. menu "CPUIdle driver"
  179. source "drivers/cpuidle/Kconfig"
  180. endmenu
  181. config PPC601_SYNC_FIX
  182. bool "Workarounds for PPC601 bugs"
  183. depends on 6xx && PPC_PMAC
  184. help
  185. Some versions of the PPC601 (the first PowerPC chip) have bugs which
  186. mean that extra synchronization instructions are required near
  187. certain instructions, typically those that make major changes to the
  188. CPU state. These extra instructions reduce performance slightly.
  189. If you say N here, these extra instructions will not be included,
  190. resulting in a kernel which will run faster but may not run at all
  191. on some systems with the PPC601 chip.
  192. If in doubt, say Y here.
  193. config TAU
  194. bool "On-chip CPU temperature sensor support"
  195. depends on 6xx
  196. help
  197. G3 and G4 processors have an on-chip temperature sensor called the
  198. 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
  199. temperature within 2-4 degrees Celsius. This option shows the current
  200. on-die temperature in /proc/cpuinfo if the cpu supports it.
  201. Unfortunately, on some chip revisions, this sensor is very inaccurate
  202. and in many cases, does not work at all, so don't assume the cpu
  203. temp is actually what /proc/cpuinfo says it is.
  204. config TAU_INT
  205. bool "Interrupt driven TAU driver (DANGEROUS)"
  206. depends on TAU
  207. ---help---
  208. The TAU supports an interrupt driven mode which causes an interrupt
  209. whenever the temperature goes out of range. This is the fastest way
  210. to get notified the temp has exceeded a range. With this option off,
  211. a timer is used to re-check the temperature periodically.
  212. However, on some cpus it appears that the TAU interrupt hardware
  213. is buggy and can cause a situation which would lead unexplained hard
  214. lockups.
  215. Unless you are extending the TAU driver, or enjoy kernel/hardware
  216. debugging, leave this option off.
  217. config TAU_AVERAGE
  218. bool "Average high and low temp"
  219. depends on TAU
  220. ---help---
  221. The TAU hardware can compare the temperature to an upper and lower
  222. bound. The default behavior is to show both the upper and lower
  223. bound in /proc/cpuinfo. If the range is large, the temperature is
  224. either changing a lot, or the TAU hardware is broken (likely on some
  225. G4's). If the range is small (around 4 degrees), the temperature is
  226. relatively stable. If you say Y here, a single temperature value,
  227. halfway between the upper and lower bounds, will be reported in
  228. /proc/cpuinfo.
  229. If in doubt, say N here.
  230. config QUICC_ENGINE
  231. bool "Freescale QUICC Engine (QE) Support"
  232. depends on FSL_SOC && PPC32
  233. select PPC_LIB_RHEAP
  234. select CRC32
  235. help
  236. The QUICC Engine (QE) is a new generation of communications
  237. coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
  238. Selecting this option means that you wish to build a kernel
  239. for a machine with a QE coprocessor.
  240. config QE_GPIO
  241. bool "QE GPIO support"
  242. depends on QUICC_ENGINE
  243. select ARCH_REQUIRE_GPIOLIB
  244. help
  245. Say Y here if you're going to use hardware that connects to the
  246. QE GPIOs.
  247. config CPM2
  248. bool "Enable support for the CPM2 (Communications Processor Module)"
  249. depends on (FSL_SOC_BOOKE && PPC32) || 8260
  250. select CPM
  251. select PPC_LIB_RHEAP
  252. select PPC_PCI_CHOICE
  253. select ARCH_REQUIRE_GPIOLIB
  254. help
  255. The CPM2 (Communications Processor Module) is a coprocessor on
  256. embedded CPUs made by Freescale. Selecting this option means that
  257. you wish to build a kernel for a machine with a CPM2 coprocessor
  258. on it (826x, 827x, 8560).
  259. config AXON_RAM
  260. tristate "Axon DDR2 memory device driver"
  261. depends on PPC_IBM_CELL_BLADE && BLOCK
  262. default m
  263. help
  264. It registers one block device per Axon's DDR2 memory bank found
  265. on a system. Block devices are called axonram?, their major and
  266. minor numbers are available in /proc/devices, /proc/partitions or
  267. in /sys/block/axonram?/dev.
  268. config FSL_ULI1575
  269. bool
  270. default n
  271. select GENERIC_ISA_DMA
  272. help
  273. Supports for the ULI1575 PCIe south bridge that exists on some
  274. Freescale reference boards. The boards all use the ULI in pretty
  275. much the same way.
  276. config CPM
  277. bool
  278. config OF_RTC
  279. bool
  280. help
  281. Uses information from the OF or flattened device tree to instantiate
  282. platform devices for direct mapped RTC chips like the DS1742 or DS1743.
  283. config SIMPLE_GPIO
  284. bool "Support for simple, memory-mapped GPIO controllers"
  285. depends on PPC
  286. select ARCH_REQUIRE_GPIOLIB
  287. help
  288. Say Y here to support simple, memory-mapped GPIO controllers.
  289. These are usually BCSRs used to control board's switches, LEDs,
  290. chip-selects, Ethernet/USB PHY's power and various other small
  291. on-board peripherals.
  292. config MCU_MPC8349EMITX
  293. bool "MPC8349E-mITX MCU driver"
  294. depends on I2C=y && PPC_83xx
  295. select ARCH_REQUIRE_GPIOLIB
  296. help
  297. Say Y here to enable soft power-off functionality on the Freescale
  298. boards with the MPC8349E-mITX-compatible MCU chips. This driver will
  299. also register MCU GPIOs with the generic GPIO API, so you'll able
  300. to use MCU pins as GPIOs.
  301. config XILINX_PCI
  302. bool "Xilinx PCI host bridge support"
  303. depends on PCI && XILINX_VIRTEX
  304. endmenu