t4240qds.dts 5.7 KB

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  1. /*
  2. * T4240QDS Device Tree Source
  3. *
  4. * Copyright 2012 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /include/ "fsl/t4240si-pre.dtsi"
  35. / {
  36. model = "fsl,T4240QDS";
  37. compatible = "fsl,T4240QDS";
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. interrupt-parent = <&mpic>;
  41. ifc: localbus@ffe124000 {
  42. reg = <0xf 0xfe124000 0 0x2000>;
  43. ranges = <0 0 0xf 0xe8000000 0x08000000
  44. 2 0 0xf 0xff800000 0x00010000
  45. 3 0 0xf 0xffdf0000 0x00008000>;
  46. nor@0,0 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. compatible = "cfi-flash";
  50. reg = <0x0 0x0 0x8000000>;
  51. bank-width = <2>;
  52. device-width = <1>;
  53. };
  54. nand@2,0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "fsl,ifc-nand";
  58. reg = <0x2 0x0 0x10000>;
  59. partition@0 {
  60. /* This location must not be altered */
  61. /* 1MB for u-boot Bootloader Image */
  62. reg = <0x0 0x00100000>;
  63. label = "NAND U-Boot Image";
  64. read-only;
  65. };
  66. partition@100000 {
  67. /* 1MB for DTB Image */
  68. reg = <0x00100000 0x00100000>;
  69. label = "NAND DTB Image";
  70. };
  71. partition@200000 {
  72. /* 10MB for Linux Kernel Image */
  73. reg = <0x00200000 0x00A00000>;
  74. label = "NAND Linux Kernel Image";
  75. };
  76. partition@C00000 {
  77. /* 500MB for Root file System Image */
  78. reg = <0x00c00000 0x1F400000>;
  79. label = "NAND RFS Image";
  80. };
  81. };
  82. board-control@3,0 {
  83. compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
  84. reg = <3 0 0x300>;
  85. };
  86. };
  87. memory {
  88. device_type = "memory";
  89. };
  90. dcsr: dcsr@f00000000 {
  91. ranges = <0x00000000 0xf 0x00000000 0x01072000>;
  92. };
  93. soc: soc@ffe000000 {
  94. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  95. reg = <0xf 0xfe000000 0 0x00001000>;
  96. spi@110000 {
  97. flash@0 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "sst,sst25wf040";
  101. reg = <0>;
  102. spi-max-frequency = <40000000>; /* input clock */
  103. };
  104. };
  105. i2c@118000 {
  106. eeprom@51 {
  107. compatible = "at24,24c256";
  108. reg = <0x51>;
  109. };
  110. eeprom@52 {
  111. compatible = "at24,24c256";
  112. reg = <0x52>;
  113. };
  114. eeprom@53 {
  115. compatible = "at24,24c256";
  116. reg = <0x53>;
  117. };
  118. eeprom@54 {
  119. compatible = "at24,24c256";
  120. reg = <0x54>;
  121. };
  122. eeprom@55 {
  123. compatible = "at24,24c256";
  124. reg = <0x55>;
  125. };
  126. eeprom@56 {
  127. compatible = "at24,24c256";
  128. reg = <0x56>;
  129. };
  130. rtc@68 {
  131. compatible = "dallas,ds3232";
  132. reg = <0x68>;
  133. interrupts = <0x1 0x1 0 0>;
  134. };
  135. };
  136. };
  137. pci0: pcie@ffe240000 {
  138. reg = <0xf 0xfe240000 0 0x10000>;
  139. ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
  140. 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
  141. pcie@0 {
  142. ranges = <0x02000000 0 0xe0000000
  143. 0x02000000 0 0xe0000000
  144. 0 0x20000000
  145. 0x01000000 0 0x00000000
  146. 0x01000000 0 0x00000000
  147. 0 0x00010000>;
  148. };
  149. };
  150. pci1: pcie@ffe250000 {
  151. reg = <0xf 0xfe250000 0 0x10000>;
  152. ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
  153. 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
  154. pcie@0 {
  155. ranges = <0x02000000 0 0xe0000000
  156. 0x02000000 0 0xe0000000
  157. 0 0x20000000
  158. 0x01000000 0 0x00000000
  159. 0x01000000 0 0x00000000
  160. 0 0x00010000>;
  161. };
  162. };
  163. pci2: pcie@ffe260000 {
  164. reg = <0xf 0xfe260000 0 0x1000>;
  165. ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
  166. 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
  167. pcie@0 {
  168. ranges = <0x02000000 0 0xe0000000
  169. 0x02000000 0 0xe0000000
  170. 0 0x20000000
  171. 0x01000000 0 0x00000000
  172. 0x01000000 0 0x00000000
  173. 0 0x00010000>;
  174. };
  175. };
  176. pci3: pcie@ffe270000 {
  177. reg = <0xf 0xfe270000 0 0x10000>;
  178. ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
  179. 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
  180. pcie@0 {
  181. ranges = <0x02000000 0 0xe0000000
  182. 0x02000000 0 0xe0000000
  183. 0 0x20000000
  184. 0x01000000 0 0x00000000
  185. 0x01000000 0 0x00000000
  186. 0 0x00010000>;
  187. };
  188. };
  189. rio: rapidio@ffe0c0000 {
  190. reg = <0xf 0xfe0c0000 0 0x11000>;
  191. port1 {
  192. ranges = <0 0 0xc 0x20000000 0 0x10000000>;
  193. };
  194. port2 {
  195. ranges = <0 0 0xc 0x30000000 0 0x10000000>;
  196. };
  197. };
  198. };
  199. /include/ "fsl/t4240si-post.dtsi"