b4si-post.dtsi 6.8 KB

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  1. /*
  2. * B4420 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 Freescale Semiconductor, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of
  32. * this software, even if advised of the possibility of such damage.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. interrupts = <25 2 0 0>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. interrupts = <20 2 0 0>;
  48. fsl,iommu-parent = <&pamu0>;
  49. pcie@0 {
  50. #interrupt-cells = <1>;
  51. #size-cells = <2>;
  52. #address-cells = <3>;
  53. device_type = "pci";
  54. reg = <0 0 0 0 0>;
  55. interrupts = <20 2 0 0>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. &dcsr {
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. compatible = "fsl,dcsr", "simple-bus";
  70. dcsr-epu@0 {
  71. compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
  72. interrupts = <52 2 0 0
  73. 84 2 0 0
  74. 85 2 0 0
  75. 94 2 0 0
  76. 95 2 0 0>;
  77. reg = <0x0 0x1000>;
  78. };
  79. dcsr-npc {
  80. compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
  81. reg = <0x1000 0x1000 0x1002000 0x10000>;
  82. };
  83. dcsr-nxc@2000 {
  84. compatible = "fsl,dcsr-nxc";
  85. reg = <0x2000 0x1000>;
  86. };
  87. dcsr-corenet {
  88. compatible = "fsl,dcsr-corenet";
  89. reg = <0x8000 0x1000 0x1A000 0x1000>;
  90. };
  91. dcsr-dpaa@9000 {
  92. compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
  93. reg = <0x9000 0x1000>;
  94. };
  95. dcsr-ocn@11000 {
  96. compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
  97. reg = <0x11000 0x1000>;
  98. };
  99. dcsr-ddr@12000 {
  100. compatible = "fsl,dcsr-ddr";
  101. dev-handle = <&ddr1>;
  102. reg = <0x12000 0x1000>;
  103. };
  104. dcsr-nal@18000 {
  105. compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
  106. reg = <0x18000 0x1000>;
  107. };
  108. dcsr-rcpm@22000 {
  109. compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
  110. reg = <0x22000 0x1000>;
  111. };
  112. dcsr-snpc@30000 {
  113. compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
  114. reg = <0x30000 0x1000 0x1022000 0x10000>;
  115. };
  116. dcsr-snpc@31000 {
  117. compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
  118. reg = <0x31000 0x1000 0x1042000 0x10000>;
  119. };
  120. dcsr-cpu-sb-proxy@100000 {
  121. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  122. cpu-handle = <&cpu0>;
  123. reg = <0x100000 0x1000 0x101000 0x1000>;
  124. };
  125. };
  126. &soc {
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. device_type = "soc";
  130. compatible = "simple-bus";
  131. soc-sram-error {
  132. compatible = "fsl,soc-sram-error";
  133. interrupts = <16 2 1 2>;
  134. };
  135. corenet-law@0 {
  136. compatible = "fsl,corenet-law";
  137. reg = <0x0 0x1000>;
  138. fsl,num-laws = <32>;
  139. };
  140. ddr1: memory-controller@8000 {
  141. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  142. reg = <0x8000 0x1000>;
  143. interrupts = <16 2 1 8>;
  144. };
  145. cpc: l3-cache-controller@10000 {
  146. compatible = "fsl,b4-l3-cache-controller", "cache";
  147. reg = <0x10000 0x1000>;
  148. interrupts = <16 2 1 4>;
  149. };
  150. corenet-cf@18000 {
  151. compatible = "fsl,b4-corenet-cf";
  152. reg = <0x18000 0x1000>;
  153. interrupts = <16 2 1 0>;
  154. fsl,ccf-num-csdids = <32>;
  155. fsl,ccf-num-snoopids = <32>;
  156. };
  157. iommu@20000 {
  158. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  159. reg = <0x20000 0x4000>;
  160. #address-cells = <1>;
  161. #size-cells = <1>;
  162. interrupts = <
  163. 24 2 0 0
  164. 16 2 1 1>;
  165. /* PCIe, DMA, SRIO */
  166. pamu0: pamu@0 {
  167. reg = <0 0x1000>;
  168. fsl,primary-cache-geometry = <8 1>;
  169. fsl,secondary-cache-geometry = <32 2>;
  170. };
  171. /* AXI2, Maple */
  172. pamu1: pamu@1000 {
  173. reg = <0x1000 0x1000>;
  174. fsl,primary-cache-geometry = <32 1>;
  175. fsl,secondary-cache-geometry = <32 2>;
  176. };
  177. /* Q/BMan */
  178. pamu2: pamu@2000 {
  179. reg = <0x2000 0x1000>;
  180. fsl,primary-cache-geometry = <32 1>;
  181. fsl,secondary-cache-geometry = <32 2>;
  182. };
  183. /* AXI1, FMAN */
  184. pamu3: pamu@3000 {
  185. reg = <0x3000 0x1000>;
  186. fsl,primary-cache-geometry = <32 1>;
  187. fsl,secondary-cache-geometry = <32 2>;
  188. };
  189. };
  190. /include/ "qoriq-mpic4.3.dtsi"
  191. guts: global-utilities@e0000 {
  192. compatible = "fsl,b4-device-config";
  193. reg = <0xe0000 0xe00>;
  194. fsl,has-rstcr;
  195. fsl,liodn-bits = <12>;
  196. };
  197. clockgen: global-utilities@e1000 {
  198. compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
  199. reg = <0xe1000 0x1000>;
  200. };
  201. rcpm: global-utilities@e2000 {
  202. compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
  203. reg = <0xe2000 0x1000>;
  204. };
  205. /include/ "qoriq-dma-0.dtsi"
  206. dma@100300 {
  207. fsl,iommu-parent = <&pamu0>;
  208. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  209. };
  210. /include/ "qoriq-dma-1.dtsi"
  211. dma@101300 {
  212. fsl,iommu-parent = <&pamu0>;
  213. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  214. };
  215. /include/ "qonverge-usb2-dr-0.dtsi"
  216. usb0: usb@210000 {
  217. compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
  218. fsl,iommu-parent = <&pamu1>;
  219. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  220. };
  221. /include/ "qoriq-espi-0.dtsi"
  222. spi@110000 {
  223. fsl,espi-num-chipselects = <4>;
  224. };
  225. /include/ "qoriq-esdhc-0.dtsi"
  226. sdhc@114000 {
  227. sdhci,auto-cmd12;
  228. fsl,iommu-parent = <&pamu1>;
  229. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  230. };
  231. /include/ "qoriq-i2c-0.dtsi"
  232. /include/ "qoriq-i2c-1.dtsi"
  233. /include/ "qoriq-duart-0.dtsi"
  234. /include/ "qoriq-duart-1.dtsi"
  235. /include/ "qoriq-sec5.3-0.dtsi"
  236. L2: l2-cache-controller@c20000 {
  237. compatible = "fsl,b4-l2-cache-controller";
  238. reg = <0xc20000 0x1000>;
  239. next-level-cache = <&cpc>;
  240. };
  241. };