spinlock.h 4.5 KB

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  1. /*
  2. * Copyright (C) 2012 ARM Ltd.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #ifndef __ASM_SPINLOCK_H
  17. #define __ASM_SPINLOCK_H
  18. #include <asm/spinlock_types.h>
  19. #include <asm/processor.h>
  20. /*
  21. * Spinlock implementation.
  22. *
  23. * The old value is read exclusively and the new one, if unlocked, is written
  24. * exclusively. In case of failure, the loop is restarted.
  25. *
  26. * The memory barriers are implicit with the load-acquire and store-release
  27. * instructions.
  28. *
  29. * Unlocked value: 0
  30. * Locked value: 1
  31. */
  32. #define arch_spin_is_locked(x) ((x)->lock != 0)
  33. #define arch_spin_unlock_wait(lock) \
  34. do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
  35. #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
  36. static inline void arch_spin_lock(arch_spinlock_t *lock)
  37. {
  38. unsigned int tmp;
  39. asm volatile(
  40. " sevl\n"
  41. "1: wfe\n"
  42. "2: ldaxr %w0, %1\n"
  43. " cbnz %w0, 1b\n"
  44. " stxr %w0, %w2, %1\n"
  45. " cbnz %w0, 2b\n"
  46. : "=&r" (tmp), "+Q" (lock->lock)
  47. : "r" (1)
  48. : "cc", "memory");
  49. }
  50. static inline int arch_spin_trylock(arch_spinlock_t *lock)
  51. {
  52. unsigned int tmp;
  53. asm volatile(
  54. "2: ldaxr %w0, %1\n"
  55. " cbnz %w0, 1f\n"
  56. " stxr %w0, %w2, %1\n"
  57. " cbnz %w0, 2b\n"
  58. "1:\n"
  59. : "=&r" (tmp), "+Q" (lock->lock)
  60. : "r" (1)
  61. : "cc", "memory");
  62. return !tmp;
  63. }
  64. static inline void arch_spin_unlock(arch_spinlock_t *lock)
  65. {
  66. asm volatile(
  67. " stlr %w1, %0\n"
  68. : "=Q" (lock->lock) : "r" (0) : "memory");
  69. }
  70. /*
  71. * Write lock implementation.
  72. *
  73. * Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
  74. * exclusively held.
  75. *
  76. * The memory barriers are implicit with the load-acquire and store-release
  77. * instructions.
  78. */
  79. static inline void arch_write_lock(arch_rwlock_t *rw)
  80. {
  81. unsigned int tmp;
  82. asm volatile(
  83. " sevl\n"
  84. "1: wfe\n"
  85. "2: ldaxr %w0, %1\n"
  86. " cbnz %w0, 1b\n"
  87. " stxr %w0, %w2, %1\n"
  88. " cbnz %w0, 2b\n"
  89. : "=&r" (tmp), "+Q" (rw->lock)
  90. : "r" (0x80000000)
  91. : "cc", "memory");
  92. }
  93. static inline int arch_write_trylock(arch_rwlock_t *rw)
  94. {
  95. unsigned int tmp;
  96. asm volatile(
  97. " ldaxr %w0, %1\n"
  98. " cbnz %w0, 1f\n"
  99. " stxr %w0, %w2, %1\n"
  100. "1:\n"
  101. : "=&r" (tmp), "+Q" (rw->lock)
  102. : "r" (0x80000000)
  103. : "cc", "memory");
  104. return !tmp;
  105. }
  106. static inline void arch_write_unlock(arch_rwlock_t *rw)
  107. {
  108. asm volatile(
  109. " stlr %w1, %0\n"
  110. : "=Q" (rw->lock) : "r" (0) : "memory");
  111. }
  112. /* write_can_lock - would write_trylock() succeed? */
  113. #define arch_write_can_lock(x) ((x)->lock == 0)
  114. /*
  115. * Read lock implementation.
  116. *
  117. * It exclusively loads the lock value, increments it and stores the new value
  118. * back if positive and the CPU still exclusively owns the location. If the
  119. * value is negative, the lock is already held.
  120. *
  121. * During unlocking there may be multiple active read locks but no write lock.
  122. *
  123. * The memory barriers are implicit with the load-acquire and store-release
  124. * instructions.
  125. */
  126. static inline void arch_read_lock(arch_rwlock_t *rw)
  127. {
  128. unsigned int tmp, tmp2;
  129. asm volatile(
  130. " sevl\n"
  131. "1: wfe\n"
  132. "2: ldaxr %w0, %2\n"
  133. " add %w0, %w0, #1\n"
  134. " tbnz %w0, #31, 1b\n"
  135. " stxr %w1, %w0, %2\n"
  136. " cbnz %w1, 2b\n"
  137. : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
  138. :
  139. : "cc", "memory");
  140. }
  141. static inline void arch_read_unlock(arch_rwlock_t *rw)
  142. {
  143. unsigned int tmp, tmp2;
  144. asm volatile(
  145. "1: ldxr %w0, %2\n"
  146. " sub %w0, %w0, #1\n"
  147. " stlxr %w1, %w0, %2\n"
  148. " cbnz %w1, 1b\n"
  149. : "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
  150. :
  151. : "cc", "memory");
  152. }
  153. static inline int arch_read_trylock(arch_rwlock_t *rw)
  154. {
  155. unsigned int tmp, tmp2 = 1;
  156. asm volatile(
  157. " ldaxr %w0, %2\n"
  158. " add %w0, %w0, #1\n"
  159. " tbnz %w0, #31, 1f\n"
  160. " stxr %w1, %w0, %2\n"
  161. "1:\n"
  162. : "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
  163. :
  164. : "cc", "memory");
  165. return !tmp2;
  166. }
  167. /* read_can_lock - would read_trylock() succeed? */
  168. #define arch_read_can_lock(x) ((x)->lock < 0x80000000)
  169. #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
  170. #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
  171. #define arch_spin_relax(lock) cpu_relax()
  172. #define arch_read_relax(lock) cpu_relax()
  173. #define arch_write_relax(lock) cpu_relax()
  174. #endif /* __ASM_SPINLOCK_H */