platsmp.c 2.6 KB

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  1. /*
  2. * arch/arm/mach-sti/platsmp.c
  3. *
  4. * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  5. * http://www.st.com
  6. *
  7. * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
  8. *
  9. * Copyright (C) 2002 ARM Ltd.
  10. * All Rights Reserved
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/errno.h>
  18. #include <linux/delay.h>
  19. #include <linux/smp.h>
  20. #include <linux/io.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <asm/cacheflush.h>
  24. #include <asm/smp_plat.h>
  25. #include <asm/smp_scu.h>
  26. #include "smp.h"
  27. static void write_pen_release(int val)
  28. {
  29. pen_release = val;
  30. smp_wmb();
  31. __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  32. outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  33. }
  34. static DEFINE_SPINLOCK(boot_lock);
  35. void sti_secondary_init(unsigned int cpu)
  36. {
  37. trace_hardirqs_off();
  38. /*
  39. * let the primary processor know we're out of the
  40. * pen, then head off into the C entry point
  41. */
  42. write_pen_release(-1);
  43. /*
  44. * Synchronise with the boot thread.
  45. */
  46. spin_lock(&boot_lock);
  47. spin_unlock(&boot_lock);
  48. }
  49. int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
  50. {
  51. unsigned long timeout;
  52. /*
  53. * set synchronisation state between this boot processor
  54. * and the secondary one
  55. */
  56. spin_lock(&boot_lock);
  57. /*
  58. * The secondary processor is waiting to be released from
  59. * the holding pen - release it, then wait for it to flag
  60. * that it has been released by resetting pen_release.
  61. *
  62. * Note that "pen_release" is the hardware CPU ID, whereas
  63. * "cpu" is Linux's internal ID.
  64. */
  65. write_pen_release(cpu_logical_map(cpu));
  66. /*
  67. * Send the secondary CPU a soft interrupt, thereby causing
  68. * it to jump to the secondary entrypoint.
  69. */
  70. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  71. timeout = jiffies + (1 * HZ);
  72. while (time_before(jiffies, timeout)) {
  73. smp_rmb();
  74. if (pen_release == -1)
  75. break;
  76. udelay(10);
  77. }
  78. /*
  79. * now the secondary core is starting up let it run its
  80. * calibrations, then wait for it to finish
  81. */
  82. spin_unlock(&boot_lock);
  83. return pen_release != -1 ? -ENOSYS : 0;
  84. }
  85. void __init sti_smp_prepare_cpus(unsigned int max_cpus)
  86. {
  87. void __iomem *scu_base = NULL;
  88. struct device_node *np = of_find_compatible_node(
  89. NULL, NULL, "arm,cortex-a9-scu");
  90. if (np) {
  91. scu_base = of_iomap(np, 0);
  92. scu_enable(scu_base);
  93. of_node_put(np);
  94. }
  95. }
  96. struct smp_operations __initdata sti_smp_ops = {
  97. .smp_prepare_cpus = sti_smp_prepare_cpus,
  98. .smp_secondary_init = sti_secondary_init,
  99. .smp_boot_secondary = sti_boot_secondary,
  100. };