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- config ARCH_SIRF
- bool "CSR SiRF" if ARCH_MULTI_V7
- select ARCH_REQUIRE_GPIOLIB
- select GENERIC_CLOCKEVENTS
- select GENERIC_IRQ_CHIP
- select MIGHT_HAVE_CACHE_L2X0
- select NO_IOPORT
- select PINCTRL
- select PINCTRL_SIRF
- help
- Support for CSR SiRFprimaII/Marco/Polo platforms
- if ARCH_SIRF
- menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
- config ARCH_ATLAS6
- bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
- default y
- select CPU_V7
- select SIRF_IRQ
- help
- Support for CSR SiRFSoC ARM Cortex A9 Platform
- config ARCH_PRIMA2
- bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
- default y
- select CPU_V7
- select SIRF_IRQ
- select ZONE_DMA
- help
- Support for CSR SiRFSoC ARM Cortex A9 Platform
- config ARCH_MARCO
- bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
- default y
- select ARM_GIC
- select CPU_V7
- select HAVE_ARM_SCU if SMP
- select HAVE_SMP
- select SMP_ON_UP if SMP
- help
- Support for CSR SiRFSoC ARM Cortex A9 Platform
- endmenu
- config SIRF_IRQ
- bool
- endif
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