platsmp.c 3.3 KB

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  1. /*
  2. * Symmetric Multi Processing (SMP) support for Armada XP
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Yehuda Yitschak <yehuday@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
  16. * This file implements the routines for preparing the SMP infrastructure
  17. * and waking up the secondary CPUs
  18. */
  19. #include <linux/init.h>
  20. #include <linux/smp.h>
  21. #include <linux/clk.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/mbus.h>
  25. #include <asm/cacheflush.h>
  26. #include <asm/smp_plat.h>
  27. #include "common.h"
  28. #include "armada-370-xp.h"
  29. #include "pmsu.h"
  30. #include "coherency.h"
  31. #define AXP_BOOTROM_BASE 0xfff00000
  32. #define AXP_BOOTROM_SIZE 0x100000
  33. static struct clk *__init get_cpu_clk(int cpu)
  34. {
  35. struct clk *cpu_clk;
  36. struct device_node *np = of_get_cpu_node(cpu, NULL);
  37. if (WARN(!np, "missing cpu node\n"))
  38. return NULL;
  39. cpu_clk = of_clk_get(np, 0);
  40. if (WARN_ON(IS_ERR(cpu_clk)))
  41. return NULL;
  42. return cpu_clk;
  43. }
  44. void __init set_secondary_cpus_clock(void)
  45. {
  46. int thiscpu, cpu;
  47. unsigned long rate;
  48. struct clk *cpu_clk;
  49. thiscpu = smp_processor_id();
  50. cpu_clk = get_cpu_clk(thiscpu);
  51. if (!cpu_clk)
  52. return;
  53. clk_prepare_enable(cpu_clk);
  54. rate = clk_get_rate(cpu_clk);
  55. /* set all the other CPU clk to the same rate than the boot CPU */
  56. for_each_possible_cpu(cpu) {
  57. if (cpu == thiscpu)
  58. continue;
  59. cpu_clk = get_cpu_clk(cpu);
  60. if (!cpu_clk)
  61. return;
  62. clk_set_rate(cpu_clk, rate);
  63. }
  64. }
  65. static void armada_xp_secondary_init(unsigned int cpu)
  66. {
  67. armada_xp_mpic_smp_cpu_init();
  68. }
  69. static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
  70. {
  71. pr_info("Booting CPU %d\n", cpu);
  72. armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
  73. return 0;
  74. }
  75. static void __init armada_xp_smp_init_cpus(void)
  76. {
  77. unsigned int ncores = num_possible_cpus();
  78. if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
  79. panic("Invalid number of CPUs in DT\n");
  80. set_smp_cross_call(armada_mpic_send_doorbell);
  81. }
  82. void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
  83. {
  84. struct device_node *node;
  85. struct resource res;
  86. int err;
  87. set_secondary_cpus_clock();
  88. flush_cache_all();
  89. set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
  90. /*
  91. * In order to boot the secondary CPUs we need to ensure
  92. * the bootROM is mapped at the correct address.
  93. */
  94. node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
  95. if (!node)
  96. panic("Cannot find 'marvell,bootrom' compatible node");
  97. err = of_address_to_resource(node, 0, &res);
  98. if (err < 0)
  99. panic("Cannot get 'bootrom' node address");
  100. if (res.start != AXP_BOOTROM_BASE ||
  101. resource_size(&res) != AXP_BOOTROM_SIZE)
  102. panic("The address for the BootROM is incorrect");
  103. }
  104. struct smp_operations armada_xp_smp_ops __initdata = {
  105. .smp_init_cpus = armada_xp_smp_init_cpus,
  106. .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
  107. .smp_secondary_init = armada_xp_secondary_init,
  108. .smp_boot_secondary = armada_xp_boot_secondary,
  109. #ifdef CONFIG_HOTPLUG_CPU
  110. .cpu_die = armada_xp_cpu_die,
  111. #endif
  112. };