tegra20-colibri-512.dtsi 13 KB

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  1. #include "tegra20.dtsi"
  2. / {
  3. model = "Toradex Colibri T20 512MB";
  4. compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
  5. memory {
  6. reg = <0x00000000 0x20000000>;
  7. };
  8. host1x {
  9. hdmi {
  10. vdd-supply = <&hdmi_vdd_reg>;
  11. pll-supply = <&hdmi_pll_reg>;
  12. nvidia,ddc-i2c-bus = <&i2c_ddc>;
  13. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  14. GPIO_ACTIVE_HIGH>;
  15. };
  16. };
  17. pinmux {
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&state_default>;
  20. state_default: pinmux {
  21. audio_refclk {
  22. nvidia,pins = "cdev1";
  23. nvidia,function = "plla_out";
  24. nvidia,pull = <0>;
  25. nvidia,tristate = <0>;
  26. };
  27. crt {
  28. nvidia,pins = "crtp";
  29. nvidia,function = "crt";
  30. nvidia,pull = <0>;
  31. nvidia,tristate = <1>;
  32. };
  33. dap3 {
  34. nvidia,pins = "dap3";
  35. nvidia,function = "dap3";
  36. nvidia,pull = <0>;
  37. nvidia,tristate = <0>;
  38. };
  39. displaya {
  40. nvidia,pins = "ld0", "ld1", "ld2", "ld3",
  41. "ld4", "ld5", "ld6", "ld7", "ld8",
  42. "ld9", "ld10", "ld11", "ld12", "ld13",
  43. "ld14", "ld15", "ld16", "ld17",
  44. "lhs", "lpw0", "lpw2", "lsc0",
  45. "lsc1", "lsck", "lsda", "lspi", "lvs";
  46. nvidia,function = "displaya";
  47. nvidia,tristate = <1>;
  48. };
  49. gpio_dte {
  50. nvidia,pins = "dte";
  51. nvidia,function = "rsvd1";
  52. nvidia,pull = <0>;
  53. nvidia,tristate = <0>;
  54. };
  55. gpio_gmi {
  56. nvidia,pins = "ata", "atc", "atd", "ate",
  57. "dap1", "dap2", "dap4", "gpu", "irrx",
  58. "irtx", "spia", "spib", "spic";
  59. nvidia,function = "gmi";
  60. nvidia,pull = <0>;
  61. nvidia,tristate = <0>;
  62. };
  63. gpio_pta {
  64. nvidia,pins = "pta";
  65. nvidia,function = "rsvd4";
  66. nvidia,pull = <0>;
  67. nvidia,tristate = <0>;
  68. };
  69. gpio_uac {
  70. nvidia,pins = "uac";
  71. nvidia,function = "rsvd2";
  72. nvidia,pull = <0>;
  73. nvidia,tristate = <0>;
  74. };
  75. hdint {
  76. nvidia,pins = "hdint";
  77. nvidia,function = "hdmi";
  78. nvidia,tristate = <1>;
  79. };
  80. i2c1 {
  81. nvidia,pins = "rm";
  82. nvidia,function = "i2c1";
  83. nvidia,pull = <0>;
  84. nvidia,tristate = <1>;
  85. };
  86. i2c3 {
  87. nvidia,pins = "dtf";
  88. nvidia,function = "i2c3";
  89. nvidia,pull = <0>;
  90. nvidia,tristate = <1>;
  91. };
  92. i2cddc {
  93. nvidia,pins = "ddc";
  94. nvidia,function = "i2c2";
  95. nvidia,pull = <2>;
  96. nvidia,tristate = <1>;
  97. };
  98. i2cp {
  99. nvidia,pins = "i2cp";
  100. nvidia,function = "i2cp";
  101. nvidia,pull = <0>;
  102. nvidia,tristate = <0>;
  103. };
  104. irda {
  105. nvidia,pins = "uad";
  106. nvidia,function = "irda";
  107. nvidia,pull = <0>;
  108. nvidia,tristate = <1>;
  109. };
  110. nand {
  111. nvidia,pins = "kbca", "kbcc", "kbcd",
  112. "kbce", "kbcf";
  113. nvidia,function = "nand";
  114. nvidia,pull = <0>;
  115. nvidia,tristate = <0>;
  116. };
  117. owc {
  118. nvidia,pins = "owc";
  119. nvidia,function = "owr";
  120. nvidia,pull = <0>;
  121. nvidia,tristate = <1>;
  122. };
  123. pmc {
  124. nvidia,pins = "pmc";
  125. nvidia,function = "pwr_on";
  126. nvidia,tristate = <0>;
  127. };
  128. pwm {
  129. nvidia,pins = "sdb", "sdc", "sdd";
  130. nvidia,function = "pwm";
  131. nvidia,tristate = <1>;
  132. };
  133. sdio4 {
  134. nvidia,pins = "atb", "gma", "gme";
  135. nvidia,function = "sdio4";
  136. nvidia,pull = <0>;
  137. nvidia,tristate = <1>;
  138. };
  139. spi1 {
  140. nvidia,pins = "spid", "spie", "spif";
  141. nvidia,function = "spi1";
  142. nvidia,pull = <0>;
  143. nvidia,tristate = <1>;
  144. };
  145. spi4 {
  146. nvidia,pins = "slxa", "slxc", "slxd", "slxk";
  147. nvidia,function = "spi4";
  148. nvidia,pull = <0>;
  149. nvidia,tristate = <1>;
  150. };
  151. uarta {
  152. nvidia,pins = "sdio1";
  153. nvidia,function = "uarta";
  154. nvidia,pull = <0>;
  155. nvidia,tristate = <1>;
  156. };
  157. uartd {
  158. nvidia,pins = "gmc";
  159. nvidia,function = "uartd";
  160. nvidia,pull = <0>;
  161. nvidia,tristate = <1>;
  162. };
  163. ulpi {
  164. nvidia,pins = "uaa", "uab", "uda";
  165. nvidia,function = "ulpi";
  166. nvidia,pull = <0>;
  167. nvidia,tristate = <0>;
  168. };
  169. ulpi_refclk {
  170. nvidia,pins = "cdev2";
  171. nvidia,function = "pllp_out4";
  172. nvidia,pull = <0>;
  173. nvidia,tristate = <0>;
  174. };
  175. usb_gpio {
  176. nvidia,pins = "spig", "spih";
  177. nvidia,function = "spi2_alt";
  178. nvidia,pull = <0>;
  179. nvidia,tristate = <0>;
  180. };
  181. vi {
  182. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  183. nvidia,function = "vi";
  184. nvidia,pull = <0>;
  185. nvidia,tristate = <1>;
  186. };
  187. vi_sc {
  188. nvidia,pins = "csus";
  189. nvidia,function = "vi_sensor_clk";
  190. nvidia,pull = <0>;
  191. nvidia,tristate = <1>;
  192. };
  193. };
  194. };
  195. i2c@7000c000 {
  196. clock-frequency = <400000>;
  197. };
  198. i2c_ddc: i2c@7000c400 {
  199. clock-frequency = <100000>;
  200. };
  201. i2c@7000c500 {
  202. clock-frequency = <400000>;
  203. };
  204. i2c@7000d000 {
  205. status = "okay";
  206. clock-frequency = <400000>;
  207. pmic: tps6586x@34 {
  208. compatible = "ti,tps6586x";
  209. reg = <0x34>;
  210. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  211. ti,system-power-controller;
  212. #gpio-cells = <2>;
  213. gpio-controller;
  214. sys-supply = <&vdd_5v0_reg>;
  215. vin-sm0-supply = <&sys_reg>;
  216. vin-sm1-supply = <&sys_reg>;
  217. vin-sm2-supply = <&sys_reg>;
  218. vinldo01-supply = <&sm2_reg>;
  219. vinldo23-supply = <&sm2_reg>;
  220. vinldo4-supply = <&sm2_reg>;
  221. vinldo678-supply = <&sm2_reg>;
  222. vinldo9-supply = <&sm2_reg>;
  223. regulators {
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. sys_reg: regulator@0 {
  227. reg = <0>;
  228. regulator-compatible = "sys";
  229. regulator-name = "vdd_sys";
  230. regulator-always-on;
  231. };
  232. regulator@1 {
  233. reg = <1>;
  234. regulator-compatible = "sm0";
  235. regulator-name = "vdd_sm0,vdd_core";
  236. regulator-min-microvolt = <1275000>;
  237. regulator-max-microvolt = <1275000>;
  238. regulator-always-on;
  239. };
  240. regulator@2 {
  241. reg = <2>;
  242. regulator-compatible = "sm1";
  243. regulator-name = "vdd_sm1,vdd_cpu";
  244. regulator-min-microvolt = <1100000>;
  245. regulator-max-microvolt = <1100000>;
  246. regulator-always-on;
  247. };
  248. sm2_reg: regulator@3 {
  249. reg = <3>;
  250. regulator-compatible = "sm2";
  251. regulator-name = "vdd_sm2,vin_ldo*";
  252. regulator-min-microvolt = <3700000>;
  253. regulator-max-microvolt = <3700000>;
  254. regulator-always-on;
  255. };
  256. /* LDO0 is not connected to anything */
  257. regulator@5 {
  258. reg = <5>;
  259. regulator-compatible = "ldo1";
  260. regulator-name = "vdd_ldo1,avdd_pll*";
  261. regulator-min-microvolt = <1100000>;
  262. regulator-max-microvolt = <1100000>;
  263. regulator-always-on;
  264. };
  265. regulator@6 {
  266. reg = <6>;
  267. regulator-compatible = "ldo2";
  268. regulator-name = "vdd_ldo2,vdd_rtc";
  269. regulator-min-microvolt = <1200000>;
  270. regulator-max-microvolt = <1200000>;
  271. };
  272. /* LDO3 is not connected to anything */
  273. regulator@8 {
  274. reg = <8>;
  275. regulator-compatible = "ldo4";
  276. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  277. regulator-min-microvolt = <1800000>;
  278. regulator-max-microvolt = <1800000>;
  279. regulator-always-on;
  280. };
  281. ldo5_reg: regulator@9 {
  282. reg = <9>;
  283. regulator-compatible = "ldo5";
  284. regulator-name = "vdd_ldo5,vdd_fuse";
  285. regulator-min-microvolt = <3300000>;
  286. regulator-max-microvolt = <3300000>;
  287. regulator-always-on;
  288. };
  289. regulator@10 {
  290. reg = <10>;
  291. regulator-compatible = "ldo6";
  292. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  293. regulator-min-microvolt = <1800000>;
  294. regulator-max-microvolt = <1800000>;
  295. };
  296. hdmi_vdd_reg: regulator@11 {
  297. reg = <11>;
  298. regulator-compatible = "ldo7";
  299. regulator-name = "vdd_ldo7,avdd_hdmi";
  300. regulator-min-microvolt = <3300000>;
  301. regulator-max-microvolt = <3300000>;
  302. };
  303. hdmi_pll_reg: regulator@12 {
  304. reg = <12>;
  305. regulator-compatible = "ldo8";
  306. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  307. regulator-min-microvolt = <1800000>;
  308. regulator-max-microvolt = <1800000>;
  309. };
  310. regulator@13 {
  311. reg = <13>;
  312. regulator-compatible = "ldo9";
  313. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  314. regulator-min-microvolt = <2850000>;
  315. regulator-max-microvolt = <2850000>;
  316. regulator-always-on;
  317. };
  318. regulator@14 {
  319. reg = <14>;
  320. regulator-compatible = "ldo_rtc";
  321. regulator-name = "vdd_rtc_out,vdd_cell";
  322. regulator-min-microvolt = <3300000>;
  323. regulator-max-microvolt = <3300000>;
  324. regulator-always-on;
  325. };
  326. };
  327. };
  328. temperature-sensor@4c {
  329. compatible = "national,lm95245";
  330. reg = <0x4c>;
  331. };
  332. };
  333. pmc {
  334. nvidia,suspend-mode = <1>;
  335. nvidia,cpu-pwr-good-time = <5000>;
  336. nvidia,cpu-pwr-off-time = <5000>;
  337. nvidia,core-pwr-good-time = <3845 3845>;
  338. nvidia,core-pwr-off-time = <3875>;
  339. nvidia,sys-clock-req-active-high;
  340. };
  341. memory-controller@7000f400 {
  342. emc-table@83250 {
  343. reg = <83250>;
  344. compatible = "nvidia,tegra20-emc-table";
  345. clock-frequency = <83250>;
  346. nvidia,emc-registers = <0x00000005 0x00000011
  347. 0x00000004 0x00000002 0x00000004 0x00000004
  348. 0x00000001 0x0000000a 0x00000002 0x00000002
  349. 0x00000001 0x00000001 0x00000003 0x00000004
  350. 0x00000003 0x00000009 0x0000000c 0x0000025f
  351. 0x00000000 0x00000003 0x00000003 0x00000002
  352. 0x00000002 0x00000001 0x00000008 0x000000c8
  353. 0x00000003 0x00000005 0x00000003 0x0000000c
  354. 0x00000002 0x00000000 0x00000000 0x00000002
  355. 0x00000000 0x00000000 0x00000083 0x00520006
  356. 0x00000010 0x00000008 0x00000000 0x00000000
  357. 0x00000000 0x00000000 0x00000000 0x00000000>;
  358. };
  359. emc-table@133200 {
  360. reg = <133200>;
  361. compatible = "nvidia,tegra20-emc-table";
  362. clock-frequency = <133200>;
  363. nvidia,emc-registers = <0x00000008 0x00000019
  364. 0x00000006 0x00000002 0x00000004 0x00000004
  365. 0x00000001 0x0000000a 0x00000002 0x00000002
  366. 0x00000002 0x00000001 0x00000003 0x00000004
  367. 0x00000003 0x00000009 0x0000000c 0x0000039f
  368. 0x00000000 0x00000003 0x00000003 0x00000002
  369. 0x00000002 0x00000001 0x00000008 0x000000c8
  370. 0x00000003 0x00000007 0x00000003 0x0000000c
  371. 0x00000002 0x00000000 0x00000000 0x00000002
  372. 0x00000000 0x00000000 0x00000083 0x00510006
  373. 0x00000010 0x00000008 0x00000000 0x00000000
  374. 0x00000000 0x00000000 0x00000000 0x00000000>;
  375. };
  376. emc-table@166500 {
  377. reg = <166500>;
  378. compatible = "nvidia,tegra20-emc-table";
  379. clock-frequency = <166500>;
  380. nvidia,emc-registers = <0x0000000a 0x00000021
  381. 0x00000008 0x00000003 0x00000004 0x00000004
  382. 0x00000002 0x0000000a 0x00000003 0x00000003
  383. 0x00000002 0x00000001 0x00000003 0x00000004
  384. 0x00000003 0x00000009 0x0000000c 0x000004df
  385. 0x00000000 0x00000003 0x00000003 0x00000003
  386. 0x00000003 0x00000001 0x00000009 0x000000c8
  387. 0x00000003 0x00000009 0x00000004 0x0000000c
  388. 0x00000002 0x00000000 0x00000000 0x00000002
  389. 0x00000000 0x00000000 0x00000083 0x004f0006
  390. 0x00000010 0x00000008 0x00000000 0x00000000
  391. 0x00000000 0x00000000 0x00000000 0x00000000>;
  392. };
  393. emc-table@333000 {
  394. reg = <333000>;
  395. compatible = "nvidia,tegra20-emc-table";
  396. clock-frequency = <333000>;
  397. nvidia,emc-registers = <0x00000014 0x00000041
  398. 0x0000000f 0x00000005 0x00000004 0x00000005
  399. 0x00000003 0x0000000a 0x00000005 0x00000005
  400. 0x00000004 0x00000001 0x00000003 0x00000004
  401. 0x00000003 0x00000009 0x0000000c 0x000009ff
  402. 0x00000000 0x00000003 0x00000003 0x00000005
  403. 0x00000005 0x00000001 0x0000000e 0x000000c8
  404. 0x00000003 0x00000011 0x00000006 0x0000000c
  405. 0x00000002 0x00000000 0x00000000 0x00000002
  406. 0x00000000 0x00000000 0x00000083 0x00380006
  407. 0x00000010 0x00000008 0x00000000 0x00000000
  408. 0x00000000 0x00000000 0x00000000 0x00000000>;
  409. };
  410. };
  411. ac97: ac97 {
  412. status = "okay";
  413. nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  414. GPIO_ACTIVE_HIGH>;
  415. nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
  416. GPIO_ACTIVE_HIGH>;
  417. };
  418. usb@c5004000 {
  419. status = "okay";
  420. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  421. GPIO_ACTIVE_LOW>;
  422. };
  423. usb-phy@c5004000 {
  424. status = "okay";
  425. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  426. GPIO_ACTIVE_LOW>;
  427. };
  428. sdhci@c8000600 {
  429. cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
  430. };
  431. clocks {
  432. compatible = "simple-bus";
  433. #address-cells = <1>;
  434. #size-cells = <0>;
  435. clk32k_in: clock {
  436. compatible = "fixed-clock";
  437. reg=<0>;
  438. #clock-cells = <0>;
  439. clock-frequency = <32768>;
  440. };
  441. };
  442. sound {
  443. compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
  444. "nvidia,tegra-audio-wm9712";
  445. nvidia,model = "Colibri T20 AC97 Audio";
  446. nvidia,audio-routing =
  447. "Headphone", "HPOUTL",
  448. "Headphone", "HPOUTR",
  449. "LineIn", "LINEINL",
  450. "LineIn", "LINEINR",
  451. "Mic", "MIC1";
  452. nvidia,ac97-controller = <&ac97>;
  453. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  454. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  455. <&tegra_car TEGRA20_CLK_CDEV1>;
  456. clock-names = "pll_a", "pll_a_out0", "mclk";
  457. };
  458. regulators {
  459. compatible = "simple-bus";
  460. #address-cells = <1>;
  461. #size-cells = <0>;
  462. vdd_5v0_reg: regulator@100 {
  463. compatible = "regulator-fixed";
  464. reg = <100>;
  465. regulator-name = "vdd_5v0";
  466. regulator-min-microvolt = <5000000>;
  467. regulator-max-microvolt = <5000000>;
  468. regulator-always-on;
  469. };
  470. regulator@101 {
  471. compatible = "regulator-fixed";
  472. reg = <101>;
  473. regulator-name = "internal_usb";
  474. regulator-min-microvolt = <5000000>;
  475. regulator-max-microvolt = <5000000>;
  476. enable-active-high;
  477. regulator-boot-on;
  478. regulator-always-on;
  479. gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
  480. };
  481. };
  482. };