stih416-pinctrl.dtsi 6.2 KB

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  1. /*
  2. * Copyright (C) 2013 STMicroelectronics Limited.
  3. * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. */
  9. #include "st-pincfg.h"
  10. / {
  11. aliases {
  12. gpio0 = &PIO0;
  13. gpio1 = &PIO1;
  14. gpio2 = &PIO2;
  15. gpio3 = &PIO3;
  16. gpio4 = &PIO4;
  17. gpio5 = &PIO40;
  18. gpio6 = &PIO5;
  19. gpio7 = &PIO6;
  20. gpio8 = &PIO7;
  21. gpio9 = &PIO8;
  22. gpio10 = &PIO9;
  23. gpio11 = &PIO10;
  24. gpio12 = &PIO11;
  25. gpio13 = &PIO12;
  26. gpio14 = &PIO30;
  27. gpio15 = &PIO31;
  28. gpio16 = &PIO13;
  29. gpio17 = &PIO14;
  30. gpio18 = &PIO15;
  31. gpio19 = &PIO16;
  32. gpio20 = &PIO17;
  33. gpio21 = &PIO18;
  34. gpio22 = &PIO100;
  35. gpio23 = &PIO101;
  36. gpio24 = &PIO102;
  37. gpio25 = &PIO103;
  38. gpio26 = &PIO104;
  39. gpio27 = &PIO105;
  40. gpio28 = &PIO106;
  41. gpio29 = &PIO107;
  42. };
  43. soc {
  44. pin-controller-sbc {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. compatible = "st,stih416-sbc-pinctrl";
  48. st,syscfg = <&syscfg_sbc>;
  49. ranges = <0 0xfe610000 0x6000>;
  50. PIO0: gpio@fe610000 {
  51. gpio-controller;
  52. #gpio-cells = <1>;
  53. reg = <0 0x100>;
  54. st,bank-name = "PIO0";
  55. };
  56. PIO1: gpio@fe611000 {
  57. gpio-controller;
  58. #gpio-cells = <1>;
  59. reg = <0x1000 0x100>;
  60. st,bank-name = "PIO1";
  61. };
  62. PIO2: gpio@fe612000 {
  63. gpio-controller;
  64. #gpio-cells = <1>;
  65. reg = <0x2000 0x100>;
  66. st,bank-name = "PIO2";
  67. };
  68. PIO3: gpio@fe613000 {
  69. gpio-controller;
  70. #gpio-cells = <1>;
  71. reg = <0x3000 0x100>;
  72. st,bank-name = "PIO3";
  73. };
  74. PIO4: gpio@fe614000 {
  75. gpio-controller;
  76. #gpio-cells = <1>;
  77. reg = <0x4000 0x100>;
  78. st,bank-name = "PIO4";
  79. };
  80. PIO40: gpio@fe615000 {
  81. gpio-controller;
  82. #gpio-cells = <1>;
  83. reg = <0x5000 0x100>;
  84. st,bank-name = "PIO40";
  85. st,retime-pin-mask = <0x7f>;
  86. };
  87. sbc_serial1 {
  88. pinctrl_sbc_serial1: sbc_serial1 {
  89. st,pins {
  90. tx = <&PIO2 6 ALT3 OUT>;
  91. rx = <&PIO2 7 ALT3 IN>;
  92. };
  93. };
  94. };
  95. };
  96. pin-controller-front {
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. compatible = "st,stih416-front-pinctrl";
  100. st,syscfg = <&syscfg_front>;
  101. ranges = <0 0xfee00000 0x10000>;
  102. PIO5: gpio@fee00000 {
  103. gpio-controller;
  104. #gpio-cells = <1>;
  105. reg = <0 0x100>;
  106. st,bank-name = "PIO5";
  107. };
  108. PIO6: gpio@fee01000 {
  109. gpio-controller;
  110. #gpio-cells = <1>;
  111. reg = <0x1000 0x100>;
  112. st,bank-name = "PIO6";
  113. };
  114. PIO7: gpio@fee02000 {
  115. gpio-controller;
  116. #gpio-cells = <1>;
  117. reg = <0x2000 0x100>;
  118. st,bank-name = "PIO7";
  119. };
  120. PIO8: gpio@fee03000 {
  121. gpio-controller;
  122. #gpio-cells = <1>;
  123. reg = <0x3000 0x100>;
  124. st,bank-name = "PIO8";
  125. };
  126. PIO9: gpio@fee04000 {
  127. gpio-controller;
  128. #gpio-cells = <1>;
  129. reg = <0x4000 0x100>;
  130. st,bank-name = "PIO9";
  131. };
  132. PIO10: gpio@fee05000 {
  133. gpio-controller;
  134. #gpio-cells = <1>;
  135. reg = <0x5000 0x100>;
  136. st,bank-name = "PIO10";
  137. };
  138. PIO11: gpio@fee06000 {
  139. gpio-controller;
  140. #gpio-cells = <1>;
  141. reg = <0x6000 0x100>;
  142. st,bank-name = "PIO11";
  143. };
  144. PIO12: gpio@fee07000 {
  145. gpio-controller;
  146. #gpio-cells = <1>;
  147. reg = <0x7000 0x100>;
  148. st,bank-name = "PIO12";
  149. };
  150. PIO30: gpio@fee08000 {
  151. gpio-controller;
  152. #gpio-cells = <1>;
  153. reg = <0x8000 0x100>;
  154. st,bank-name = "PIO30";
  155. };
  156. PIO31: gpio@fee09000 {
  157. gpio-controller;
  158. #gpio-cells = <1>;
  159. reg = <0x9000 0x100>;
  160. st,bank-name = "PIO31";
  161. };
  162. serial2-oe {
  163. pinctrl_serial2_oe: serial2-1 {
  164. st,pins {
  165. output-enable = <&PIO11 3 ALT2 OUT>;
  166. };
  167. };
  168. };
  169. };
  170. pin-controller-rear {
  171. #address-cells = <1>;
  172. #size-cells = <1>;
  173. compatible = "st,stih416-rear-pinctrl";
  174. st,syscfg = <&syscfg_rear>;
  175. ranges = <0 0xfe820000 0x6000>;
  176. PIO13: gpio@fe820000 {
  177. gpio-controller;
  178. #gpio-cells = <1>;
  179. reg = <0 0x100>;
  180. st,bank-name = "PIO13";
  181. };
  182. PIO14: gpio@fe821000 {
  183. gpio-controller;
  184. #gpio-cells = <1>;
  185. reg = <0x1000 0x100>;
  186. st,bank-name = "PIO14";
  187. };
  188. PIO15: gpio@fe822000 {
  189. gpio-controller;
  190. #gpio-cells = <1>;
  191. reg = <0x2000 0x100>;
  192. st,bank-name = "PIO15";
  193. };
  194. PIO16: gpio@fe823000 {
  195. gpio-controller;
  196. #gpio-cells = <1>;
  197. reg = <0x3000 0x100>;
  198. st,bank-name = "PIO16";
  199. };
  200. PIO17: gpio@fe824000 {
  201. gpio-controller;
  202. #gpio-cells = <1>;
  203. reg = <0x4000 0x100>;
  204. st,bank-name = "PIO17";
  205. };
  206. PIO18: gpio@fe825000 {
  207. gpio-controller;
  208. #gpio-cells = <1>;
  209. reg = <0x5000 0x100>;
  210. st,bank-name = "PIO18";
  211. st,retime-pin-mask = <0xf>;
  212. };
  213. serial2 {
  214. pinctrl_serial2: serial2-0 {
  215. st,pins {
  216. tx = <&PIO17 4 ALT2 OUT>;
  217. rx = <&PIO17 5 ALT2 IN>;
  218. };
  219. };
  220. };
  221. };
  222. pin-controller-fvdp-fe {
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. compatible = "st,stih416-fvdp-fe-pinctrl";
  226. st,syscfg = <&syscfg_fvdp_fe>;
  227. ranges = <0 0xfd6b0000 0x3000>;
  228. PIO100: gpio@fd6b0000 {
  229. gpio-controller;
  230. #gpio-cells = <1>;
  231. reg = <0 0x100>;
  232. st,bank-name = "PIO100";
  233. };
  234. PIO101: gpio@fd6b1000 {
  235. gpio-controller;
  236. #gpio-cells = <1>;
  237. reg = <0x1000 0x100>;
  238. st,bank-name = "PIO101";
  239. };
  240. PIO102: gpio@fd6b2000 {
  241. gpio-controller;
  242. #gpio-cells = <1>;
  243. reg = <0x2000 0x100>;
  244. st,bank-name = "PIO102";
  245. };
  246. };
  247. pin-controller-fvdp-lite {
  248. #address-cells = <1>;
  249. #size-cells = <1>;
  250. compatible = "st,stih416-fvdp-lite-pinctrl";
  251. st,syscfg = <&syscfg_fvdp_lite>;
  252. ranges = <0 0xfd330000 0x5000>;
  253. PIO103: gpio@fd330000 {
  254. gpio-controller;
  255. #gpio-cells = <1>;
  256. reg = <0 0x100>;
  257. st,bank-name = "PIO103";
  258. };
  259. PIO104: gpio@fd331000 {
  260. gpio-controller;
  261. #gpio-cells = <1>;
  262. reg = <0x1000 0x100>;
  263. st,bank-name = "PIO104";
  264. };
  265. PIO105: gpio@fd332000 {
  266. gpio-controller;
  267. #gpio-cells = <1>;
  268. reg = <0x2000 0x100>;
  269. st,bank-name = "PIO105";
  270. };
  271. PIO106: gpio@fd333000 {
  272. gpio-controller;
  273. #gpio-cells = <1>;
  274. reg = <0x3000 0x100>;
  275. st,bank-name = "PIO106";
  276. };
  277. PIO107: gpio@fd334000 {
  278. gpio-controller;
  279. #gpio-cells = <1>;
  280. reg = <0x4000 0x100>;
  281. st,bank-name = "PIO107";
  282. st,retime-pin-mask = <0xf>;
  283. };
  284. };
  285. };
  286. };