stih415.dtsi 2.1 KB

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  1. /*
  2. * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
  3. * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. */
  9. #include "stih41x.dtsi"
  10. #include "stih415-clock.dtsi"
  11. #include "stih415-pinctrl.dtsi"
  12. / {
  13. L2: cache-controller {
  14. compatible = "arm,pl310-cache";
  15. reg = <0xfffe2000 0x1000>;
  16. arm,data-latency = <3 2 2>;
  17. arm,tag-latency = <1 1 1>;
  18. cache-unified;
  19. cache-level = <2>;
  20. };
  21. soc {
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. interrupt-parent = <&intc>;
  25. ranges;
  26. compatible = "simple-bus";
  27. syscfg_sbc: sbc-syscfg@fe600000{
  28. compatible = "st,stih415-sbc-syscfg", "syscon";
  29. reg = <0xfe600000 0xb4>;
  30. };
  31. syscfg_front: front-syscfg@fee10000{
  32. compatible = "st,stih415-front-syscfg", "syscon";
  33. reg = <0xfee10000 0x194>;
  34. };
  35. syscfg_rear: rear-syscfg@fe830000{
  36. compatible = "st,stih415-rear-syscfg", "syscon";
  37. reg = <0xfe830000 0x190>;
  38. };
  39. /* MPE syscfgs */
  40. syscfg_left: left-syscfg@fd690000{
  41. compatible = "st,stih415-left-syscfg", "syscon";
  42. reg = <0xfd690000 0x78>;
  43. };
  44. syscfg_right: right-syscfg@fd320000{
  45. compatible = "st,stih415-right-syscfg", "syscon";
  46. reg = <0xfd320000 0x180>;
  47. };
  48. syscfg_system: system-syscfg@fdde0000 {
  49. compatible = "st,stih415-system-syscfg", "syscon";
  50. reg = <0xfdde0000 0x15c>;
  51. };
  52. syscfg_lpm: lpm-syscfg@fe4b5100{
  53. compatible = "st,stih415-lpm-syscfg", "syscon";
  54. reg = <0xfe4b5100 0x08>;
  55. };
  56. serial2: serial@fed32000 {
  57. compatible = "st,asc";
  58. status = "disabled";
  59. reg = <0xfed32000 0x2c>;
  60. interrupts = <0 197 0>;
  61. pinctrl-names = "default";
  62. pinctrl-0 = <&pinctrl_serial2>;
  63. clocks = <&CLKS_ICN_REG_0>;
  64. };
  65. /* SBC comms block ASCs in SASG1 */
  66. sbc_serial1: serial@fe531000 {
  67. compatible = "st,asc";
  68. status = "disabled";
  69. reg = <0xfe531000 0x2c>;
  70. interrupts = <0 210 0>;
  71. clocks = <&CLK_SYSIN>;
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&pinctrl_sbc_serial1>;
  74. };
  75. };
  76. };