kirkwood.dtsi 6.4 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,kirkwood";
  5. interrupt-parent = <&intc>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "marvell,feroceon";
  12. clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  13. clock-names = "cpu_clk", "ddrclk", "powersave";
  14. };
  15. };
  16. aliases {
  17. gpio0 = &gpio0;
  18. gpio1 = &gpio1;
  19. };
  20. mbus {
  21. compatible = "marvell,kirkwood-mbus", "simple-bus";
  22. #address-cells = <2>;
  23. #size-cells = <1>;
  24. /* If a board file needs to change this ranges it must replace it completely */
  25. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
  26. MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
  27. MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
  28. >;
  29. controller = <&mbusc>;
  30. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
  31. pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
  32. crypto@0301 {
  33. compatible = "marvell,orion-crypto";
  34. reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
  35. <MBUS_ID(0x03, 0x01) 0 0x800>;
  36. reg-names = "regs", "sram";
  37. interrupts = <22>;
  38. clocks = <&gate_clk 17>;
  39. status = "okay";
  40. };
  41. nand: nand@012f {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. cle = <0>;
  45. ale = <1>;
  46. bank-width = <1>;
  47. compatible = "marvell,orion-nand";
  48. reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
  49. chip-delay = <25>;
  50. /* set partition map and/or chip-delay in board dts */
  51. clocks = <&gate_clk 7>;
  52. status = "disabled";
  53. };
  54. };
  55. ocp@f1000000 {
  56. compatible = "simple-bus";
  57. ranges = <0x00000000 0xf1000000 0x0100000>;
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. mbusc: mbus-controller@20000 {
  61. compatible = "marvell,mbus-controller";
  62. reg = <0x20000 0x80>, <0x1500 0x20>;
  63. };
  64. timer: timer@20300 {
  65. compatible = "marvell,orion-timer";
  66. reg = <0x20300 0x20>;
  67. interrupt-parent = <&bridge_intc>;
  68. interrupts = <1>, <2>;
  69. clocks = <&core_clk 0>;
  70. };
  71. intc: main-interrupt-ctrl@20200 {
  72. compatible = "marvell,orion-intc";
  73. interrupt-controller;
  74. #interrupt-cells = <1>;
  75. reg = <0x20200 0x10>, <0x20210 0x10>;
  76. };
  77. bridge_intc: bridge-interrupt-ctrl@20110 {
  78. compatible = "marvell,orion-bridge-intc";
  79. interrupt-controller;
  80. #interrupt-cells = <1>;
  81. reg = <0x20110 0x8>;
  82. interrupts = <1>;
  83. marvell,#interrupts = <6>;
  84. };
  85. core_clk: core-clocks@10030 {
  86. compatible = "marvell,kirkwood-core-clock";
  87. reg = <0x10030 0x4>;
  88. #clock-cells = <1>;
  89. };
  90. gpio0: gpio@10100 {
  91. compatible = "marvell,orion-gpio";
  92. #gpio-cells = <2>;
  93. gpio-controller;
  94. reg = <0x10100 0x40>;
  95. ngpios = <32>;
  96. interrupt-controller;
  97. #interrupt-cells = <2>;
  98. interrupts = <35>, <36>, <37>, <38>;
  99. clocks = <&gate_clk 7>;
  100. };
  101. gpio1: gpio@10140 {
  102. compatible = "marvell,orion-gpio";
  103. #gpio-cells = <2>;
  104. gpio-controller;
  105. reg = <0x10140 0x40>;
  106. ngpios = <18>;
  107. interrupt-controller;
  108. #interrupt-cells = <2>;
  109. interrupts = <39>, <40>, <41>;
  110. clocks = <&gate_clk 7>;
  111. };
  112. serial@12000 {
  113. compatible = "ns16550a";
  114. reg = <0x12000 0x100>;
  115. reg-shift = <2>;
  116. interrupts = <33>;
  117. clocks = <&gate_clk 7>;
  118. status = "disabled";
  119. };
  120. serial@12100 {
  121. compatible = "ns16550a";
  122. reg = <0x12100 0x100>;
  123. reg-shift = <2>;
  124. interrupts = <34>;
  125. clocks = <&gate_clk 7>;
  126. status = "disabled";
  127. };
  128. spi@10600 {
  129. compatible = "marvell,orion-spi";
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. cell-index = <0>;
  133. interrupts = <23>;
  134. reg = <0x10600 0x28>;
  135. clocks = <&gate_clk 7>;
  136. status = "disabled";
  137. };
  138. gate_clk: clock-gating-control@2011c {
  139. compatible = "marvell,kirkwood-gating-clock";
  140. reg = <0x2011c 0x4>;
  141. clocks = <&core_clk 0>;
  142. #clock-cells = <1>;
  143. };
  144. wdt: watchdog-timer@20300 {
  145. compatible = "marvell,orion-wdt";
  146. reg = <0x20300 0x28>;
  147. interrupt-parent = <&bridge_intc>;
  148. interrupts = <3>;
  149. clocks = <&gate_clk 7>;
  150. status = "okay";
  151. };
  152. xor@60800 {
  153. compatible = "marvell,orion-xor";
  154. reg = <0x60800 0x100
  155. 0x60A00 0x100>;
  156. status = "okay";
  157. clocks = <&gate_clk 8>;
  158. xor00 {
  159. interrupts = <5>;
  160. dmacap,memcpy;
  161. dmacap,xor;
  162. };
  163. xor01 {
  164. interrupts = <6>;
  165. dmacap,memcpy;
  166. dmacap,xor;
  167. dmacap,memset;
  168. };
  169. };
  170. xor@60900 {
  171. compatible = "marvell,orion-xor";
  172. reg = <0x60900 0x100
  173. 0xd0B00 0x100>;
  174. status = "okay";
  175. clocks = <&gate_clk 16>;
  176. xor00 {
  177. interrupts = <7>;
  178. dmacap,memcpy;
  179. dmacap,xor;
  180. };
  181. xor01 {
  182. interrupts = <8>;
  183. dmacap,memcpy;
  184. dmacap,xor;
  185. dmacap,memset;
  186. };
  187. };
  188. ehci@50000 {
  189. compatible = "marvell,orion-ehci";
  190. reg = <0x50000 0x1000>;
  191. interrupts = <19>;
  192. clocks = <&gate_clk 3>;
  193. status = "okay";
  194. };
  195. i2c@11000 {
  196. compatible = "marvell,mv64xxx-i2c";
  197. reg = <0x11000 0x20>;
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. interrupts = <29>;
  201. clock-frequency = <100000>;
  202. clocks = <&gate_clk 7>;
  203. status = "disabled";
  204. };
  205. mdio: mdio-bus@72004 {
  206. compatible = "marvell,orion-mdio";
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. reg = <0x72004 0x84>;
  210. interrupts = <46>;
  211. clocks = <&gate_clk 0>;
  212. status = "disabled";
  213. /* add phy nodes in board file */
  214. };
  215. eth0: ethernet-controller@72000 {
  216. compatible = "marvell,kirkwood-eth";
  217. #address-cells = <1>;
  218. #size-cells = <0>;
  219. reg = <0x72000 0x4000>;
  220. clocks = <&gate_clk 0>;
  221. marvell,tx-checksum-limit = <1600>;
  222. status = "disabled";
  223. ethernet0-port@0 {
  224. device_type = "network";
  225. compatible = "marvell,kirkwood-eth-port";
  226. reg = <0>;
  227. interrupts = <11>;
  228. /* overwrite MAC address in bootloader */
  229. local-mac-address = [00 00 00 00 00 00];
  230. /* set phy-handle property in board file */
  231. };
  232. };
  233. eth1: ethernet-controller@76000 {
  234. compatible = "marvell,kirkwood-eth";
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. reg = <0x76000 0x4000>;
  238. clocks = <&gate_clk 19>;
  239. marvell,tx-checksum-limit = <1600>;
  240. status = "disabled";
  241. ethernet1-port@0 {
  242. device_type = "network";
  243. compatible = "marvell,kirkwood-eth-port";
  244. reg = <0>;
  245. interrupts = <15>;
  246. /* overwrite MAC address in bootloader */
  247. local-mac-address = [00 00 00 00 00 00];
  248. /* set phy-handle property in board file */
  249. };
  250. };
  251. };
  252. };