iwl-agn-ucode.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include <linux/dma-mapping.h>
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-agn-hw.h"
  38. #include "iwl-agn.h"
  39. #include "iwl-agn-calib.h"
  40. #include "iwl-trans.h"
  41. #include "iwl-fh.h"
  42. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  43. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  44. 0, COEX_UNASSOC_IDLE_FLAGS},
  45. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  46. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  47. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  48. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  49. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  50. 0, COEX_CALIBRATION_FLAGS},
  51. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  52. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  53. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  54. 0, COEX_CONNECTION_ESTAB_FLAGS},
  55. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  56. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  57. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  58. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  59. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  60. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  61. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  62. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  63. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  64. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  65. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  66. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  67. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  68. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  69. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  70. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  71. };
  72. /******************************************************************************
  73. *
  74. * uCode download functions
  75. *
  76. ******************************************************************************/
  77. static void iwl_free_fw_desc(struct iwl_bus *bus, struct fw_desc *desc)
  78. {
  79. if (desc->v_addr)
  80. dma_free_coherent(bus->dev, desc->len,
  81. desc->v_addr, desc->p_addr);
  82. desc->v_addr = NULL;
  83. desc->len = 0;
  84. }
  85. static void iwl_free_fw_img(struct iwl_bus *bus, struct fw_img *img)
  86. {
  87. iwl_free_fw_desc(bus, &img->code);
  88. iwl_free_fw_desc(bus, &img->data);
  89. }
  90. void iwl_dealloc_ucode(struct iwl_trans *trans)
  91. {
  92. iwl_free_fw_img(bus(trans), &trans->ucode_rt);
  93. iwl_free_fw_img(bus(trans), &trans->ucode_init);
  94. iwl_free_fw_img(bus(trans), &trans->ucode_wowlan);
  95. }
  96. int iwl_alloc_fw_desc(struct iwl_bus *bus, struct fw_desc *desc,
  97. const void *data, size_t len)
  98. {
  99. if (!len) {
  100. desc->v_addr = NULL;
  101. return -EINVAL;
  102. }
  103. desc->v_addr = dma_alloc_coherent(bus->dev, len,
  104. &desc->p_addr, GFP_KERNEL);
  105. if (!desc->v_addr)
  106. return -ENOMEM;
  107. desc->len = len;
  108. memcpy(desc->v_addr, data, len);
  109. return 0;
  110. }
  111. /*
  112. * ucode
  113. */
  114. static int iwlagn_load_section(struct iwl_trans *trans, const char *name,
  115. struct fw_desc *image, u32 dst_addr)
  116. {
  117. struct iwl_bus *bus = bus(trans);
  118. dma_addr_t phy_addr = image->p_addr;
  119. u32 byte_cnt = image->len;
  120. int ret;
  121. trans->ucode_write_complete = 0;
  122. iwl_write_direct32(bus,
  123. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  124. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  125. iwl_write_direct32(bus,
  126. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  127. iwl_write_direct32(bus,
  128. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  129. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  130. iwl_write_direct32(bus,
  131. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  132. (iwl_get_dma_hi_addr(phy_addr)
  133. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  134. iwl_write_direct32(bus,
  135. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  136. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  137. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  138. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  139. iwl_write_direct32(bus,
  140. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  141. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  142. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  143. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  144. IWL_DEBUG_FW(bus, "%s uCode section being loaded...\n", name);
  145. ret = wait_event_timeout(trans->shrd->wait_command_queue,
  146. trans->ucode_write_complete, 5 * HZ);
  147. if (!ret) {
  148. IWL_ERR(trans, "Could not load the %s uCode section\n",
  149. name);
  150. return -ETIMEDOUT;
  151. }
  152. return 0;
  153. }
  154. static inline struct fw_img *iwl_get_ucode_image(struct iwl_trans *trans,
  155. enum iwl_ucode_type ucode_type)
  156. {
  157. switch (ucode_type) {
  158. case IWL_UCODE_INIT:
  159. return &trans->ucode_init;
  160. case IWL_UCODE_WOWLAN:
  161. return &trans->ucode_wowlan;
  162. case IWL_UCODE_REGULAR:
  163. return &trans->ucode_rt;
  164. case IWL_UCODE_NONE:
  165. break;
  166. }
  167. return NULL;
  168. }
  169. static int iwlagn_load_given_ucode(struct iwl_trans *trans,
  170. enum iwl_ucode_type ucode_type)
  171. {
  172. int ret = 0;
  173. struct fw_img *image = iwl_get_ucode_image(trans, ucode_type);
  174. if (!image) {
  175. IWL_ERR(trans, "Invalid ucode requested (%d)\n",
  176. ucode_type);
  177. return -EINVAL;
  178. }
  179. ret = iwlagn_load_section(trans, "INST", &image->code,
  180. IWLAGN_RTC_INST_LOWER_BOUND);
  181. if (ret)
  182. return ret;
  183. return iwlagn_load_section(trans, "DATA", &image->data,
  184. IWLAGN_RTC_DATA_LOWER_BOUND);
  185. }
  186. /*
  187. * Calibration
  188. */
  189. static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
  190. {
  191. struct iwl_calib_xtal_freq_cmd cmd;
  192. __le16 *xtal_calib =
  193. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
  194. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  195. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  196. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  197. return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd));
  198. }
  199. static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
  200. {
  201. struct iwl_calib_temperature_offset_cmd cmd;
  202. __le16 *offset_calib =
  203. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  204. memset(&cmd, 0, sizeof(cmd));
  205. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  206. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
  207. if (!(cmd.radio_sensor_offset))
  208. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  209. IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
  210. le16_to_cpu(cmd.radio_sensor_offset));
  211. return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd));
  212. }
  213. static int iwlagn_set_temperature_offset_calib_v2(struct iwl_priv *priv)
  214. {
  215. struct iwl_calib_temperature_offset_v2_cmd cmd;
  216. __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(priv,
  217. EEPROM_KELVIN_TEMPERATURE);
  218. __le16 *offset_calib_low =
  219. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  220. struct iwl_eeprom_calib_hdr *hdr;
  221. memset(&cmd, 0, sizeof(cmd));
  222. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  223. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
  224. EEPROM_CALIB_ALL);
  225. memcpy(&cmd.radio_sensor_offset_high, offset_calib_high,
  226. sizeof(*offset_calib_high));
  227. memcpy(&cmd.radio_sensor_offset_low, offset_calib_low,
  228. sizeof(*offset_calib_low));
  229. if (!(cmd.radio_sensor_offset_low)) {
  230. IWL_DEBUG_CALIB(priv, "no info in EEPROM, use default\n");
  231. cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET;
  232. cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET;
  233. }
  234. memcpy(&cmd.burntVoltageRef, &hdr->voltage,
  235. sizeof(hdr->voltage));
  236. IWL_DEBUG_CALIB(priv, "Radio sensor offset high: %d\n",
  237. le16_to_cpu(cmd.radio_sensor_offset_high));
  238. IWL_DEBUG_CALIB(priv, "Radio sensor offset low: %d\n",
  239. le16_to_cpu(cmd.radio_sensor_offset_low));
  240. IWL_DEBUG_CALIB(priv, "Voltage Ref: %d\n",
  241. le16_to_cpu(cmd.burntVoltageRef));
  242. return iwl_calib_set(priv, (void *)&cmd, sizeof(cmd));
  243. }
  244. static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
  245. {
  246. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  247. struct iwl_host_cmd cmd = {
  248. .id = CALIBRATION_CFG_CMD,
  249. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  250. .data = { &calib_cfg_cmd, },
  251. };
  252. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  253. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  254. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  255. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  256. calib_cfg_cmd.ucd_calib_cfg.flags =
  257. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  258. return iwl_trans_send_cmd(trans(priv), &cmd);
  259. }
  260. int iwlagn_rx_calib_result(struct iwl_priv *priv,
  261. struct iwl_rx_mem_buffer *rxb,
  262. struct iwl_device_cmd *cmd)
  263. {
  264. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  265. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  266. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  267. /* reduce the size of the length field itself */
  268. len -= 4;
  269. if (iwl_calib_set(priv, hdr, len))
  270. IWL_ERR(priv, "Failed to record calibration data %d\n",
  271. hdr->op_code);
  272. return 0;
  273. }
  274. int iwlagn_init_alive_start(struct iwl_priv *priv)
  275. {
  276. int ret;
  277. if (priv->cfg->bt_params &&
  278. priv->cfg->bt_params->advanced_bt_coexist) {
  279. /*
  280. * Tell uCode we are ready to perform calibration
  281. * need to perform this before any calibration
  282. * no need to close the envlope since we are going
  283. * to load the runtime uCode later.
  284. */
  285. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  286. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  287. if (ret)
  288. return ret;
  289. }
  290. ret = iwlagn_send_calib_cfg(priv);
  291. if (ret)
  292. return ret;
  293. /**
  294. * temperature offset calibration is only needed for runtime ucode,
  295. * so prepare the value now.
  296. */
  297. if (priv->cfg->need_temp_offset_calib) {
  298. if (priv->cfg->temp_offset_v2)
  299. return iwlagn_set_temperature_offset_calib_v2(priv);
  300. else
  301. return iwlagn_set_temperature_offset_calib(priv);
  302. }
  303. return 0;
  304. }
  305. static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
  306. {
  307. struct iwl_wimax_coex_cmd coex_cmd;
  308. if (priv->cfg->base_params->support_wimax_coexist) {
  309. /* UnMask wake up src at associated sleep */
  310. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  311. /* UnMask wake up src at unassociated sleep */
  312. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  313. memcpy(coex_cmd.sta_prio, cu_priorities,
  314. sizeof(struct iwl_wimax_coex_event_entry) *
  315. COEX_NUM_OF_EVENTS);
  316. /* enabling the coexistence feature */
  317. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  318. /* enabling the priorities tables */
  319. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  320. } else {
  321. /* coexistence is disabled */
  322. memset(&coex_cmd, 0, sizeof(coex_cmd));
  323. }
  324. return iwl_trans_send_cmd_pdu(trans(priv),
  325. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  326. sizeof(coex_cmd), &coex_cmd);
  327. }
  328. static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  329. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  330. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  331. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  332. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  333. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  334. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  335. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  336. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  337. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  338. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  339. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  340. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  341. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  342. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  343. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  344. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  345. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  346. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  347. 0, 0, 0, 0, 0, 0, 0
  348. };
  349. void iwlagn_send_prio_tbl(struct iwl_priv *priv)
  350. {
  351. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  352. memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
  353. sizeof(iwlagn_bt_prio_tbl));
  354. if (iwl_trans_send_cmd_pdu(trans(priv),
  355. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  356. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  357. IWL_ERR(priv, "failed to send BT prio tbl command\n");
  358. }
  359. int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
  360. {
  361. struct iwl_bt_coex_prot_env_cmd env_cmd;
  362. int ret;
  363. env_cmd.action = action;
  364. env_cmd.type = type;
  365. ret = iwl_trans_send_cmd_pdu(trans(priv),
  366. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  367. sizeof(env_cmd), &env_cmd);
  368. if (ret)
  369. IWL_ERR(priv, "failed to send BT env command\n");
  370. return ret;
  371. }
  372. static int iwlagn_alive_notify(struct iwl_priv *priv)
  373. {
  374. struct iwl_rxon_context *ctx;
  375. int ret;
  376. if (!priv->tx_cmd_pool)
  377. priv->tx_cmd_pool =
  378. kmem_cache_create("iwlagn_dev_cmd",
  379. sizeof(struct iwl_device_cmd),
  380. sizeof(void *), 0, NULL);
  381. if (!priv->tx_cmd_pool)
  382. return -ENOMEM;
  383. iwl_trans_tx_start(trans(priv));
  384. for_each_context(priv, ctx)
  385. ctx->last_tx_rejected = false;
  386. ret = iwlagn_send_wimax_coex(priv);
  387. if (ret)
  388. return ret;
  389. if (!priv->cfg->no_xtal_calib) {
  390. ret = iwlagn_set_Xtal_calib(priv);
  391. if (ret)
  392. return ret;
  393. }
  394. return iwl_send_calib_results(priv);
  395. }
  396. /**
  397. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  398. * using sample data 100 bytes apart. If these sample points are good,
  399. * it's a pretty good bet that everything between them is good, too.
  400. */
  401. static int iwl_verify_inst_sparse(struct iwl_bus *bus,
  402. struct fw_desc *fw_desc)
  403. {
  404. __le32 *image = (__le32 *)fw_desc->v_addr;
  405. u32 len = fw_desc->len;
  406. u32 val;
  407. u32 i;
  408. IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len);
  409. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  410. /* read data comes through single port, auto-incr addr */
  411. /* NOTE: Use the debugless read so we don't flood kernel log
  412. * if IWL_DL_IO is set */
  413. iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR,
  414. i + IWLAGN_RTC_INST_LOWER_BOUND);
  415. val = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
  416. if (val != le32_to_cpu(*image))
  417. return -EIO;
  418. }
  419. return 0;
  420. }
  421. static void iwl_print_mismatch_inst(struct iwl_bus *bus,
  422. struct fw_desc *fw_desc)
  423. {
  424. __le32 *image = (__le32 *)fw_desc->v_addr;
  425. u32 len = fw_desc->len;
  426. u32 val;
  427. u32 offs;
  428. int errors = 0;
  429. IWL_DEBUG_FW(bus, "ucode inst image size is %u\n", len);
  430. iwl_write_direct32(bus, HBUS_TARG_MEM_RADDR,
  431. IWLAGN_RTC_INST_LOWER_BOUND);
  432. for (offs = 0;
  433. offs < len && errors < 20;
  434. offs += sizeof(u32), image++) {
  435. /* read data comes through single port, auto-incr addr */
  436. val = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
  437. if (val != le32_to_cpu(*image)) {
  438. IWL_ERR(bus, "uCode INST section at "
  439. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  440. offs, val, le32_to_cpu(*image));
  441. errors++;
  442. }
  443. }
  444. }
  445. /**
  446. * iwl_verify_ucode - determine which instruction image is in SRAM,
  447. * and verify its contents
  448. */
  449. static int iwl_verify_ucode(struct iwl_trans *trans,
  450. enum iwl_ucode_type ucode_type)
  451. {
  452. struct fw_img *img = iwl_get_ucode_image(trans, ucode_type);
  453. if (!img) {
  454. IWL_ERR(trans, "Invalid ucode requested (%d)\n", ucode_type);
  455. return -EINVAL;
  456. }
  457. if (!iwl_verify_inst_sparse(bus(trans), &img->code)) {
  458. IWL_DEBUG_FW(trans, "uCode is good in inst SRAM\n");
  459. return 0;
  460. }
  461. IWL_ERR(trans, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  462. iwl_print_mismatch_inst(bus(trans), &img->code);
  463. return -EIO;
  464. }
  465. struct iwlagn_alive_data {
  466. bool valid;
  467. u8 subtype;
  468. };
  469. static void iwlagn_alive_fn(struct iwl_priv *priv,
  470. struct iwl_rx_packet *pkt,
  471. void *data)
  472. {
  473. struct iwlagn_alive_data *alive_data = data;
  474. struct iwl_alive_resp *palive;
  475. palive = &pkt->u.alive_frame;
  476. IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
  477. "0x%01X 0x%01X\n",
  478. palive->is_valid, palive->ver_type,
  479. palive->ver_subtype);
  480. priv->device_pointers.error_event_table =
  481. le32_to_cpu(palive->error_event_table_ptr);
  482. priv->device_pointers.log_event_table =
  483. le32_to_cpu(palive->log_event_table_ptr);
  484. alive_data->subtype = palive->ver_subtype;
  485. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  486. }
  487. #define UCODE_ALIVE_TIMEOUT HZ
  488. #define UCODE_CALIB_TIMEOUT (2*HZ)
  489. int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
  490. enum iwl_ucode_type ucode_type)
  491. {
  492. struct iwl_notification_wait alive_wait;
  493. struct iwlagn_alive_data alive_data;
  494. int ret;
  495. enum iwl_ucode_type old_type;
  496. ret = iwl_trans_start_device(trans(priv));
  497. if (ret)
  498. return ret;
  499. iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
  500. iwlagn_alive_fn, &alive_data);
  501. old_type = priv->ucode_type;
  502. priv->ucode_type = ucode_type;
  503. ret = iwlagn_load_given_ucode(trans(priv), ucode_type);
  504. if (ret) {
  505. priv->ucode_type = old_type;
  506. iwlagn_remove_notification(priv, &alive_wait);
  507. return ret;
  508. }
  509. iwl_trans_kick_nic(trans(priv));
  510. /*
  511. * Some things may run in the background now, but we
  512. * just wait for the ALIVE notification here.
  513. */
  514. ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
  515. if (ret) {
  516. priv->ucode_type = old_type;
  517. return ret;
  518. }
  519. if (!alive_data.valid) {
  520. IWL_ERR(priv, "Loaded ucode is not valid!\n");
  521. priv->ucode_type = old_type;
  522. return -EIO;
  523. }
  524. /*
  525. * This step takes a long time (60-80ms!!) and
  526. * WoWLAN image should be loaded quickly, so
  527. * skip it for WoWLAN.
  528. */
  529. if (ucode_type != IWL_UCODE_WOWLAN) {
  530. ret = iwl_verify_ucode(trans(priv), ucode_type);
  531. if (ret) {
  532. priv->ucode_type = old_type;
  533. return ret;
  534. }
  535. /* delay a bit to give rfkill time to run */
  536. msleep(5);
  537. }
  538. ret = iwlagn_alive_notify(priv);
  539. if (ret) {
  540. IWL_WARN(priv,
  541. "Could not complete ALIVE transition: %d\n", ret);
  542. priv->ucode_type = old_type;
  543. return ret;
  544. }
  545. return 0;
  546. }
  547. int iwlagn_run_init_ucode(struct iwl_priv *priv)
  548. {
  549. struct iwl_notification_wait calib_wait;
  550. int ret;
  551. lockdep_assert_held(&priv->shrd->mutex);
  552. /* No init ucode required? Curious, but maybe ok */
  553. if (!trans(priv)->ucode_init.code.len)
  554. return 0;
  555. if (priv->ucode_type != IWL_UCODE_NONE)
  556. return 0;
  557. iwlagn_init_notification_wait(priv, &calib_wait,
  558. CALIBRATION_COMPLETE_NOTIFICATION,
  559. NULL, NULL);
  560. /* Will also start the device */
  561. ret = iwlagn_load_ucode_wait_alive(priv, IWL_UCODE_INIT);
  562. if (ret)
  563. goto error;
  564. ret = iwlagn_init_alive_start(priv);
  565. if (ret)
  566. goto error;
  567. /*
  568. * Some things may run in the background now, but we
  569. * just wait for the calibration complete notification.
  570. */
  571. ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
  572. goto out;
  573. error:
  574. iwlagn_remove_notification(priv, &calib_wait);
  575. out:
  576. /* Whatever happened, stop the device */
  577. iwl_trans_stop_device(trans(priv));
  578. return ret;
  579. }