common.c 148 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/types.h>
  34. #include <linux/lockdep.h>
  35. #include <linux/init.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/delay.h>
  39. #include <linux/skbuff.h>
  40. #include <net/mac80211.h>
  41. #include "common.h"
  42. const char *il_get_cmd_string(u8 cmd)
  43. {
  44. switch (cmd) {
  45. IL_CMD(N_ALIVE);
  46. IL_CMD(N_ERROR);
  47. IL_CMD(C_RXON);
  48. IL_CMD(C_RXON_ASSOC);
  49. IL_CMD(C_QOS_PARAM);
  50. IL_CMD(C_RXON_TIMING);
  51. IL_CMD(C_ADD_STA);
  52. IL_CMD(C_REM_STA);
  53. IL_CMD(C_WEPKEY);
  54. IL_CMD(N_3945_RX);
  55. IL_CMD(C_TX);
  56. IL_CMD(C_RATE_SCALE);
  57. IL_CMD(C_LEDS);
  58. IL_CMD(C_TX_LINK_QUALITY_CMD);
  59. IL_CMD(C_CHANNEL_SWITCH);
  60. IL_CMD(N_CHANNEL_SWITCH);
  61. IL_CMD(C_SPECTRUM_MEASUREMENT);
  62. IL_CMD(N_SPECTRUM_MEASUREMENT);
  63. IL_CMD(C_POWER_TBL);
  64. IL_CMD(N_PM_SLEEP);
  65. IL_CMD(N_PM_DEBUG_STATS);
  66. IL_CMD(C_SCAN);
  67. IL_CMD(C_SCAN_ABORT);
  68. IL_CMD(N_SCAN_START);
  69. IL_CMD(N_SCAN_RESULTS);
  70. IL_CMD(N_SCAN_COMPLETE);
  71. IL_CMD(N_BEACON);
  72. IL_CMD(C_TX_BEACON);
  73. IL_CMD(C_TX_PWR_TBL);
  74. IL_CMD(C_BT_CONFIG);
  75. IL_CMD(C_STATS);
  76. IL_CMD(N_STATS);
  77. IL_CMD(N_CARD_STATE);
  78. IL_CMD(N_MISSED_BEACONS);
  79. IL_CMD(C_CT_KILL_CONFIG);
  80. IL_CMD(C_SENSITIVITY);
  81. IL_CMD(C_PHY_CALIBRATION);
  82. IL_CMD(N_RX_PHY);
  83. IL_CMD(N_RX_MPDU);
  84. IL_CMD(N_RX);
  85. IL_CMD(N_COMPRESSED_BA);
  86. default:
  87. return "UNKNOWN";
  88. }
  89. }
  90. EXPORT_SYMBOL(il_get_cmd_string);
  91. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  92. static void il_generic_cmd_callback(struct il_priv *il,
  93. struct il_device_cmd *cmd,
  94. struct il_rx_pkt *pkt)
  95. {
  96. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  97. IL_ERR("Bad return from %s (0x%08X)\n",
  98. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  99. return;
  100. }
  101. #ifdef CONFIG_IWLEGACY_DEBUG
  102. switch (cmd->hdr.cmd) {
  103. case C_TX_LINK_QUALITY_CMD:
  104. case C_SENSITIVITY:
  105. D_HC_DUMP("back from %s (0x%08X)\n",
  106. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  107. break;
  108. default:
  109. D_HC("back from %s (0x%08X)\n",
  110. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  111. }
  112. #endif
  113. }
  114. static int
  115. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  116. {
  117. int ret;
  118. BUG_ON(!(cmd->flags & CMD_ASYNC));
  119. /* An asynchronous command can not expect an SKB to be set. */
  120. BUG_ON(cmd->flags & CMD_WANT_SKB);
  121. /* Assign a generic callback if one is not provided */
  122. if (!cmd->callback)
  123. cmd->callback = il_generic_cmd_callback;
  124. if (test_bit(S_EXIT_PENDING, &il->status))
  125. return -EBUSY;
  126. ret = il_enqueue_hcmd(il, cmd);
  127. if (ret < 0) {
  128. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  129. il_get_cmd_string(cmd->id), ret);
  130. return ret;
  131. }
  132. return 0;
  133. }
  134. int il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  135. {
  136. int cmd_idx;
  137. int ret;
  138. lockdep_assert_held(&il->mutex);
  139. BUG_ON(cmd->flags & CMD_ASYNC);
  140. /* A synchronous command can not have a callback set. */
  141. BUG_ON(cmd->callback);
  142. D_INFO("Attempting to send sync command %s\n",
  143. il_get_cmd_string(cmd->id));
  144. set_bit(S_HCMD_ACTIVE, &il->status);
  145. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  146. il_get_cmd_string(cmd->id));
  147. cmd_idx = il_enqueue_hcmd(il, cmd);
  148. if (cmd_idx < 0) {
  149. ret = cmd_idx;
  150. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  151. il_get_cmd_string(cmd->id), ret);
  152. goto out;
  153. }
  154. ret = wait_event_timeout(il->wait_command_queue,
  155. !test_bit(S_HCMD_ACTIVE, &il->status),
  156. HOST_COMPLETE_TIMEOUT);
  157. if (!ret) {
  158. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  159. IL_ERR(
  160. "Error sending %s: time out after %dms.\n",
  161. il_get_cmd_string(cmd->id),
  162. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  163. clear_bit(S_HCMD_ACTIVE, &il->status);
  164. D_INFO(
  165. "Clearing HCMD_ACTIVE for command %s\n",
  166. il_get_cmd_string(cmd->id));
  167. ret = -ETIMEDOUT;
  168. goto cancel;
  169. }
  170. }
  171. if (test_bit(S_RF_KILL_HW, &il->status)) {
  172. IL_ERR("Command %s aborted: RF KILL Switch\n",
  173. il_get_cmd_string(cmd->id));
  174. ret = -ECANCELED;
  175. goto fail;
  176. }
  177. if (test_bit(S_FW_ERROR, &il->status)) {
  178. IL_ERR("Command %s failed: FW Error\n",
  179. il_get_cmd_string(cmd->id));
  180. ret = -EIO;
  181. goto fail;
  182. }
  183. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  184. IL_ERR("Error: Response NULL in '%s'\n",
  185. il_get_cmd_string(cmd->id));
  186. ret = -EIO;
  187. goto cancel;
  188. }
  189. ret = 0;
  190. goto out;
  191. cancel:
  192. if (cmd->flags & CMD_WANT_SKB) {
  193. /*
  194. * Cancel the CMD_WANT_SKB flag for the cmd in the
  195. * TX cmd queue. Otherwise in case the cmd comes
  196. * in later, it will possibly set an invalid
  197. * address (cmd->meta.source).
  198. */
  199. il->txq[il->cmd_queue].meta[cmd_idx].flags &=
  200. ~CMD_WANT_SKB;
  201. }
  202. fail:
  203. if (cmd->reply_page) {
  204. il_free_pages(il, cmd->reply_page);
  205. cmd->reply_page = 0;
  206. }
  207. out:
  208. return ret;
  209. }
  210. EXPORT_SYMBOL(il_send_cmd_sync);
  211. int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  212. {
  213. if (cmd->flags & CMD_ASYNC)
  214. return il_send_cmd_async(il, cmd);
  215. return il_send_cmd_sync(il, cmd);
  216. }
  217. EXPORT_SYMBOL(il_send_cmd);
  218. int
  219. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  220. {
  221. struct il_host_cmd cmd = {
  222. .id = id,
  223. .len = len,
  224. .data = data,
  225. };
  226. return il_send_cmd_sync(il, &cmd);
  227. }
  228. EXPORT_SYMBOL(il_send_cmd_pdu);
  229. int il_send_cmd_pdu_async(struct il_priv *il,
  230. u8 id, u16 len, const void *data,
  231. void (*callback)(struct il_priv *il,
  232. struct il_device_cmd *cmd,
  233. struct il_rx_pkt *pkt))
  234. {
  235. struct il_host_cmd cmd = {
  236. .id = id,
  237. .len = len,
  238. .data = data,
  239. };
  240. cmd.flags |= CMD_ASYNC;
  241. cmd.callback = callback;
  242. return il_send_cmd_async(il, &cmd);
  243. }
  244. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  245. /* default: IL_LED_BLINK(0) using blinking idx table */
  246. static int led_mode;
  247. module_param(led_mode, int, S_IRUGO);
  248. MODULE_PARM_DESC(led_mode, "0=system default, "
  249. "1=On(RF On)/Off(RF Off), 2=blinking");
  250. /* Throughput OFF time(ms) ON time (ms)
  251. * >300 25 25
  252. * >200 to 300 40 40
  253. * >100 to 200 55 55
  254. * >70 to 100 65 65
  255. * >50 to 70 75 75
  256. * >20 to 50 85 85
  257. * >10 to 20 95 95
  258. * >5 to 10 110 110
  259. * >1 to 5 130 130
  260. * >0 to 1 167 167
  261. * <=0 SOLID ON
  262. */
  263. static const struct ieee80211_tpt_blink il_blink[] = {
  264. { .throughput = 0, .blink_time = 334 },
  265. { .throughput = 1 * 1024 - 1, .blink_time = 260 },
  266. { .throughput = 5 * 1024 - 1, .blink_time = 220 },
  267. { .throughput = 10 * 1024 - 1, .blink_time = 190 },
  268. { .throughput = 20 * 1024 - 1, .blink_time = 170 },
  269. { .throughput = 50 * 1024 - 1, .blink_time = 150 },
  270. { .throughput = 70 * 1024 - 1, .blink_time = 130 },
  271. { .throughput = 100 * 1024 - 1, .blink_time = 110 },
  272. { .throughput = 200 * 1024 - 1, .blink_time = 80 },
  273. { .throughput = 300 * 1024 - 1, .blink_time = 50 },
  274. };
  275. /*
  276. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  277. * Led blink rate analysis showed an average deviation of 0% on 3945,
  278. * 5% on 4965 HW.
  279. * Need to compensate on the led on/off time per HW according to the deviation
  280. * to achieve the desired led frequency
  281. * The calculation is: (100-averageDeviation)/100 * blinkTime
  282. * For code efficiency the calculation will be:
  283. * compensation = (100 - averageDeviation) * 64 / 100
  284. * NewBlinkTime = (compensation * BlinkTime) / 64
  285. */
  286. static inline u8 il_blink_compensation(struct il_priv *il,
  287. u8 time, u16 compensation)
  288. {
  289. if (!compensation) {
  290. IL_ERR("undefined blink compensation: "
  291. "use pre-defined blinking time\n");
  292. return time;
  293. }
  294. return (u8)((time * compensation) >> 6);
  295. }
  296. /* Set led pattern command */
  297. static int il_led_cmd(struct il_priv *il,
  298. unsigned long on,
  299. unsigned long off)
  300. {
  301. struct il_led_cmd led_cmd = {
  302. .id = IL_LED_LINK,
  303. .interval = IL_DEF_LED_INTRVL
  304. };
  305. int ret;
  306. if (!test_bit(S_READY, &il->status))
  307. return -EBUSY;
  308. if (il->blink_on == on && il->blink_off == off)
  309. return 0;
  310. if (off == 0) {
  311. /* led is SOLID_ON */
  312. on = IL_LED_SOLID;
  313. }
  314. D_LED("Led blink time compensation=%u\n",
  315. il->cfg->base_params->led_compensation);
  316. led_cmd.on = il_blink_compensation(il, on,
  317. il->cfg->base_params->led_compensation);
  318. led_cmd.off = il_blink_compensation(il, off,
  319. il->cfg->base_params->led_compensation);
  320. ret = il->cfg->ops->led->cmd(il, &led_cmd);
  321. if (!ret) {
  322. il->blink_on = on;
  323. il->blink_off = off;
  324. }
  325. return ret;
  326. }
  327. static void il_led_brightness_set(struct led_classdev *led_cdev,
  328. enum led_brightness brightness)
  329. {
  330. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  331. unsigned long on = 0;
  332. if (brightness > 0)
  333. on = IL_LED_SOLID;
  334. il_led_cmd(il, on, 0);
  335. }
  336. static int il_led_blink_set(struct led_classdev *led_cdev,
  337. unsigned long *delay_on,
  338. unsigned long *delay_off)
  339. {
  340. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  341. return il_led_cmd(il, *delay_on, *delay_off);
  342. }
  343. void il_leds_init(struct il_priv *il)
  344. {
  345. int mode = led_mode;
  346. int ret;
  347. if (mode == IL_LED_DEFAULT)
  348. mode = il->cfg->led_mode;
  349. il->led.name = kasprintf(GFP_KERNEL, "%s-led",
  350. wiphy_name(il->hw->wiphy));
  351. il->led.brightness_set = il_led_brightness_set;
  352. il->led.blink_set = il_led_blink_set;
  353. il->led.max_brightness = 1;
  354. switch (mode) {
  355. case IL_LED_DEFAULT:
  356. WARN_ON(1);
  357. break;
  358. case IL_LED_BLINK:
  359. il->led.default_trigger =
  360. ieee80211_create_tpt_led_trigger(il->hw,
  361. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  362. il_blink, ARRAY_SIZE(il_blink));
  363. break;
  364. case IL_LED_RF_STATE:
  365. il->led.default_trigger =
  366. ieee80211_get_radio_led_name(il->hw);
  367. break;
  368. }
  369. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  370. if (ret) {
  371. kfree(il->led.name);
  372. return;
  373. }
  374. il->led_registered = true;
  375. }
  376. EXPORT_SYMBOL(il_leds_init);
  377. void il_leds_exit(struct il_priv *il)
  378. {
  379. if (!il->led_registered)
  380. return;
  381. led_classdev_unregister(&il->led);
  382. kfree(il->led.name);
  383. }
  384. EXPORT_SYMBOL(il_leds_exit);
  385. /************************** EEPROM BANDS ****************************
  386. *
  387. * The il_eeprom_band definitions below provide the mapping from the
  388. * EEPROM contents to the specific channel number supported for each
  389. * band.
  390. *
  391. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  392. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  393. * The specific geography and calibration information for that channel
  394. * is contained in the eeprom map itself.
  395. *
  396. * During init, we copy the eeprom information and channel map
  397. * information into il->channel_info_24/52 and il->channel_map_24/52
  398. *
  399. * channel_map_24/52 provides the idx in the channel_info array for a
  400. * given channel. We have to have two separate maps as there is channel
  401. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  402. * band_2
  403. *
  404. * A value of 0xff stored in the channel_map indicates that the channel
  405. * is not supported by the hardware at all.
  406. *
  407. * A value of 0xfe in the channel_map indicates that the channel is not
  408. * valid for Tx with the current hardware. This means that
  409. * while the system can tune and receive on a given channel, it may not
  410. * be able to associate or transmit any frames on that
  411. * channel. There is no corresponding channel information for that
  412. * entry.
  413. *
  414. *********************************************************************/
  415. /* 2.4 GHz */
  416. const u8 il_eeprom_band_1[14] = {
  417. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  418. };
  419. /* 5.2 GHz bands */
  420. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  421. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  422. };
  423. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  424. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  425. };
  426. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  427. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  428. };
  429. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  430. 145, 149, 153, 157, 161, 165
  431. };
  432. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  433. 1, 2, 3, 4, 5, 6, 7
  434. };
  435. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  436. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  437. };
  438. /******************************************************************************
  439. *
  440. * EEPROM related functions
  441. *
  442. ******************************************************************************/
  443. static int il_eeprom_verify_signature(struct il_priv *il)
  444. {
  445. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  446. int ret = 0;
  447. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  448. switch (gp) {
  449. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  450. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  451. break;
  452. default:
  453. IL_ERR("bad EEPROM signature,"
  454. "EEPROM_GP=0x%08x\n", gp);
  455. ret = -ENOENT;
  456. break;
  457. }
  458. return ret;
  459. }
  460. const u8
  461. *il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  462. {
  463. BUG_ON(offset >= il->cfg->base_params->eeprom_size);
  464. return &il->eeprom[offset];
  465. }
  466. EXPORT_SYMBOL(il_eeprom_query_addr);
  467. u16 il_eeprom_query16(const struct il_priv *il, size_t offset)
  468. {
  469. if (!il->eeprom)
  470. return 0;
  471. return (u16)il->eeprom[offset] | ((u16)il->eeprom[offset + 1] << 8);
  472. }
  473. EXPORT_SYMBOL(il_eeprom_query16);
  474. /**
  475. * il_eeprom_init - read EEPROM contents
  476. *
  477. * Load the EEPROM contents from adapter into il->eeprom
  478. *
  479. * NOTE: This routine uses the non-debug IO access functions.
  480. */
  481. int il_eeprom_init(struct il_priv *il)
  482. {
  483. __le16 *e;
  484. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  485. int sz;
  486. int ret;
  487. u16 addr;
  488. /* allocate eeprom */
  489. sz = il->cfg->base_params->eeprom_size;
  490. D_EEPROM("NVM size = %d\n", sz);
  491. il->eeprom = kzalloc(sz, GFP_KERNEL);
  492. if (!il->eeprom) {
  493. ret = -ENOMEM;
  494. goto alloc_err;
  495. }
  496. e = (__le16 *)il->eeprom;
  497. il->cfg->ops->lib->apm_ops.init(il);
  498. ret = il_eeprom_verify_signature(il);
  499. if (ret < 0) {
  500. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  501. ret = -ENOENT;
  502. goto err;
  503. }
  504. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  505. ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il);
  506. if (ret < 0) {
  507. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  508. ret = -ENOENT;
  509. goto err;
  510. }
  511. /* eeprom is an array of 16bit values */
  512. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  513. u32 r;
  514. _il_wr(il, CSR_EEPROM_REG,
  515. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  516. ret = _il_poll_bit(il, CSR_EEPROM_REG,
  517. CSR_EEPROM_REG_READ_VALID_MSK,
  518. CSR_EEPROM_REG_READ_VALID_MSK,
  519. IL_EEPROM_ACCESS_TIMEOUT);
  520. if (ret < 0) {
  521. IL_ERR("Time out reading EEPROM[%d]\n",
  522. addr);
  523. goto done;
  524. }
  525. r = _il_rd(il, CSR_EEPROM_REG);
  526. e[addr / 2] = cpu_to_le16(r >> 16);
  527. }
  528. D_EEPROM("NVM Type: %s, version: 0x%x\n",
  529. "EEPROM",
  530. il_eeprom_query16(il, EEPROM_VERSION));
  531. ret = 0;
  532. done:
  533. il->cfg->ops->lib->eeprom_ops.release_semaphore(il);
  534. err:
  535. if (ret)
  536. il_eeprom_free(il);
  537. /* Reset chip to save power until we load uCode during "up". */
  538. il_apm_stop(il);
  539. alloc_err:
  540. return ret;
  541. }
  542. EXPORT_SYMBOL(il_eeprom_init);
  543. void il_eeprom_free(struct il_priv *il)
  544. {
  545. kfree(il->eeprom);
  546. il->eeprom = NULL;
  547. }
  548. EXPORT_SYMBOL(il_eeprom_free);
  549. static void il_init_band_reference(const struct il_priv *il,
  550. int eep_band, int *eeprom_ch_count,
  551. const struct il_eeprom_channel **eeprom_ch_info,
  552. const u8 **eeprom_ch_idx)
  553. {
  554. u32 offset = il->cfg->ops->lib->
  555. eeprom_ops.regulatory_bands[eep_band - 1];
  556. switch (eep_band) {
  557. case 1: /* 2.4GHz band */
  558. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  559. *eeprom_ch_info = (struct il_eeprom_channel *)
  560. il_eeprom_query_addr(il, offset);
  561. *eeprom_ch_idx = il_eeprom_band_1;
  562. break;
  563. case 2: /* 4.9GHz band */
  564. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  565. *eeprom_ch_info = (struct il_eeprom_channel *)
  566. il_eeprom_query_addr(il, offset);
  567. *eeprom_ch_idx = il_eeprom_band_2;
  568. break;
  569. case 3: /* 5.2GHz band */
  570. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  571. *eeprom_ch_info = (struct il_eeprom_channel *)
  572. il_eeprom_query_addr(il, offset);
  573. *eeprom_ch_idx = il_eeprom_band_3;
  574. break;
  575. case 4: /* 5.5GHz band */
  576. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  577. *eeprom_ch_info = (struct il_eeprom_channel *)
  578. il_eeprom_query_addr(il, offset);
  579. *eeprom_ch_idx = il_eeprom_band_4;
  580. break;
  581. case 5: /* 5.7GHz band */
  582. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  583. *eeprom_ch_info = (struct il_eeprom_channel *)
  584. il_eeprom_query_addr(il, offset);
  585. *eeprom_ch_idx = il_eeprom_band_5;
  586. break;
  587. case 6: /* 2.4GHz ht40 channels */
  588. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  589. *eeprom_ch_info = (struct il_eeprom_channel *)
  590. il_eeprom_query_addr(il, offset);
  591. *eeprom_ch_idx = il_eeprom_band_6;
  592. break;
  593. case 7: /* 5 GHz ht40 channels */
  594. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  595. *eeprom_ch_info = (struct il_eeprom_channel *)
  596. il_eeprom_query_addr(il, offset);
  597. *eeprom_ch_idx = il_eeprom_band_7;
  598. break;
  599. default:
  600. BUG();
  601. }
  602. }
  603. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  604. ? # x " " : "")
  605. /**
  606. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  607. *
  608. * Does not set up a command, or touch hardware.
  609. */
  610. static int il_mod_ht40_chan_info(struct il_priv *il,
  611. enum ieee80211_band band, u16 channel,
  612. const struct il_eeprom_channel *eeprom_ch,
  613. u8 clear_ht40_extension_channel)
  614. {
  615. struct il_channel_info *ch_info;
  616. ch_info = (struct il_channel_info *)
  617. il_get_channel_info(il, band, channel);
  618. if (!il_is_channel_valid(ch_info))
  619. return -1;
  620. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  621. " Ad-Hoc %ssupported\n",
  622. ch_info->channel,
  623. il_is_channel_a_band(ch_info) ?
  624. "5.2" : "2.4",
  625. CHECK_AND_PRINT(IBSS),
  626. CHECK_AND_PRINT(ACTIVE),
  627. CHECK_AND_PRINT(RADAR),
  628. CHECK_AND_PRINT(WIDE),
  629. CHECK_AND_PRINT(DFS),
  630. eeprom_ch->flags,
  631. eeprom_ch->max_power_avg,
  632. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
  633. && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
  634. "" : "not ");
  635. ch_info->ht40_eeprom = *eeprom_ch;
  636. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  637. ch_info->ht40_flags = eeprom_ch->flags;
  638. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  639. ch_info->ht40_extension_channel &=
  640. ~clear_ht40_extension_channel;
  641. return 0;
  642. }
  643. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  644. ? # x " " : "")
  645. /**
  646. * il_init_channel_map - Set up driver's info for all possible channels
  647. */
  648. int il_init_channel_map(struct il_priv *il)
  649. {
  650. int eeprom_ch_count = 0;
  651. const u8 *eeprom_ch_idx = NULL;
  652. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  653. int band, ch;
  654. struct il_channel_info *ch_info;
  655. if (il->channel_count) {
  656. D_EEPROM("Channel map already initialized.\n");
  657. return 0;
  658. }
  659. D_EEPROM("Initializing regulatory info from EEPROM\n");
  660. il->channel_count =
  661. ARRAY_SIZE(il_eeprom_band_1) +
  662. ARRAY_SIZE(il_eeprom_band_2) +
  663. ARRAY_SIZE(il_eeprom_band_3) +
  664. ARRAY_SIZE(il_eeprom_band_4) +
  665. ARRAY_SIZE(il_eeprom_band_5);
  666. D_EEPROM("Parsing data for %d channels.\n",
  667. il->channel_count);
  668. il->channel_info = kzalloc(sizeof(struct il_channel_info) *
  669. il->channel_count, GFP_KERNEL);
  670. if (!il->channel_info) {
  671. IL_ERR("Could not allocate channel_info\n");
  672. il->channel_count = 0;
  673. return -ENOMEM;
  674. }
  675. ch_info = il->channel_info;
  676. /* Loop through the 5 EEPROM bands adding them in order to the
  677. * channel map we maintain (that contains additional information than
  678. * what just in the EEPROM) */
  679. for (band = 1; band <= 5; band++) {
  680. il_init_band_reference(il, band, &eeprom_ch_count,
  681. &eeprom_ch_info, &eeprom_ch_idx);
  682. /* Loop through each band adding each of the channels */
  683. for (ch = 0; ch < eeprom_ch_count; ch++) {
  684. ch_info->channel = eeprom_ch_idx[ch];
  685. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  686. IEEE80211_BAND_5GHZ;
  687. /* permanently store EEPROM's channel regulatory flags
  688. * and max power in channel info database. */
  689. ch_info->eeprom = eeprom_ch_info[ch];
  690. /* Copy the run-time flags so they are there even on
  691. * invalid channels */
  692. ch_info->flags = eeprom_ch_info[ch].flags;
  693. /* First write that ht40 is not enabled, and then enable
  694. * one by one */
  695. ch_info->ht40_extension_channel =
  696. IEEE80211_CHAN_NO_HT40;
  697. if (!(il_is_channel_valid(ch_info))) {
  698. D_EEPROM(
  699. "Ch. %d Flags %x [%sGHz] - "
  700. "No traffic\n",
  701. ch_info->channel,
  702. ch_info->flags,
  703. il_is_channel_a_band(ch_info) ?
  704. "5.2" : "2.4");
  705. ch_info++;
  706. continue;
  707. }
  708. /* Initialize regulatory-based run-time data */
  709. ch_info->max_power_avg = ch_info->curr_txpow =
  710. eeprom_ch_info[ch].max_power_avg;
  711. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  712. ch_info->min_power = 0;
  713. D_EEPROM("Ch. %d [%sGHz] "
  714. "%s%s%s%s%s%s(0x%02x %ddBm):"
  715. " Ad-Hoc %ssupported\n",
  716. ch_info->channel,
  717. il_is_channel_a_band(ch_info) ?
  718. "5.2" : "2.4",
  719. CHECK_AND_PRINT_I(VALID),
  720. CHECK_AND_PRINT_I(IBSS),
  721. CHECK_AND_PRINT_I(ACTIVE),
  722. CHECK_AND_PRINT_I(RADAR),
  723. CHECK_AND_PRINT_I(WIDE),
  724. CHECK_AND_PRINT_I(DFS),
  725. eeprom_ch_info[ch].flags,
  726. eeprom_ch_info[ch].max_power_avg,
  727. ((eeprom_ch_info[ch].
  728. flags & EEPROM_CHANNEL_IBSS)
  729. && !(eeprom_ch_info[ch].
  730. flags & EEPROM_CHANNEL_RADAR))
  731. ? "" : "not ");
  732. ch_info++;
  733. }
  734. }
  735. /* Check if we do have HT40 channels */
  736. if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
  737. EEPROM_REGULATORY_BAND_NO_HT40 &&
  738. il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
  739. EEPROM_REGULATORY_BAND_NO_HT40)
  740. return 0;
  741. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  742. for (band = 6; band <= 7; band++) {
  743. enum ieee80211_band ieeeband;
  744. il_init_band_reference(il, band, &eeprom_ch_count,
  745. &eeprom_ch_info, &eeprom_ch_idx);
  746. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  747. ieeeband =
  748. (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  749. /* Loop through each band adding each of the channels */
  750. for (ch = 0; ch < eeprom_ch_count; ch++) {
  751. /* Set up driver's info for lower half */
  752. il_mod_ht40_chan_info(il, ieeeband,
  753. eeprom_ch_idx[ch],
  754. &eeprom_ch_info[ch],
  755. IEEE80211_CHAN_NO_HT40PLUS);
  756. /* Set up driver's info for upper half */
  757. il_mod_ht40_chan_info(il, ieeeband,
  758. eeprom_ch_idx[ch] + 4,
  759. &eeprom_ch_info[ch],
  760. IEEE80211_CHAN_NO_HT40MINUS);
  761. }
  762. }
  763. return 0;
  764. }
  765. EXPORT_SYMBOL(il_init_channel_map);
  766. /*
  767. * il_free_channel_map - undo allocations in il_init_channel_map
  768. */
  769. void il_free_channel_map(struct il_priv *il)
  770. {
  771. kfree(il->channel_info);
  772. il->channel_count = 0;
  773. }
  774. EXPORT_SYMBOL(il_free_channel_map);
  775. /**
  776. * il_get_channel_info - Find driver's ilate channel info
  777. *
  778. * Based on band and channel number.
  779. */
  780. const struct
  781. il_channel_info *il_get_channel_info(const struct il_priv *il,
  782. enum ieee80211_band band, u16 channel)
  783. {
  784. int i;
  785. switch (band) {
  786. case IEEE80211_BAND_5GHZ:
  787. for (i = 14; i < il->channel_count; i++) {
  788. if (il->channel_info[i].channel == channel)
  789. return &il->channel_info[i];
  790. }
  791. break;
  792. case IEEE80211_BAND_2GHZ:
  793. if (channel >= 1 && channel <= 14)
  794. return &il->channel_info[channel - 1];
  795. break;
  796. default:
  797. BUG();
  798. }
  799. return NULL;
  800. }
  801. EXPORT_SYMBOL(il_get_channel_info);
  802. /*
  803. * Setting power level allows the card to go to sleep when not busy.
  804. *
  805. * We calculate a sleep command based on the required latency, which
  806. * we get from mac80211. In order to handle thermal throttling, we can
  807. * also use pre-defined power levels.
  808. */
  809. /*
  810. * This defines the old power levels. They are still used by default
  811. * (level 1) and for thermal throttle (levels 3 through 5)
  812. */
  813. struct il_power_vec_entry {
  814. struct il_powertable_cmd cmd;
  815. u8 no_dtim; /* number of skip dtim */
  816. };
  817. static void il_power_sleep_cam_cmd(struct il_priv *il,
  818. struct il_powertable_cmd *cmd)
  819. {
  820. memset(cmd, 0, sizeof(*cmd));
  821. if (il->power_data.pci_pm)
  822. cmd->flags |= IL_POWER_PCI_PM_MSK;
  823. D_POWER("Sleep command for CAM\n");
  824. }
  825. static int
  826. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  827. {
  828. D_POWER("Sending power/sleep command\n");
  829. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  830. D_POWER("Tx timeout = %u\n",
  831. le32_to_cpu(cmd->tx_data_timeout));
  832. D_POWER("Rx timeout = %u\n",
  833. le32_to_cpu(cmd->rx_data_timeout));
  834. D_POWER(
  835. "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  836. le32_to_cpu(cmd->sleep_interval[0]),
  837. le32_to_cpu(cmd->sleep_interval[1]),
  838. le32_to_cpu(cmd->sleep_interval[2]),
  839. le32_to_cpu(cmd->sleep_interval[3]),
  840. le32_to_cpu(cmd->sleep_interval[4]));
  841. return il_send_cmd_pdu(il, C_POWER_TBL,
  842. sizeof(struct il_powertable_cmd), cmd);
  843. }
  844. int
  845. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd,
  846. bool force)
  847. {
  848. int ret;
  849. bool update_chains;
  850. lockdep_assert_held(&il->mutex);
  851. /* Don't update the RX chain when chain noise calibration is running */
  852. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  853. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  854. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  855. return 0;
  856. if (!il_is_ready_rf(il))
  857. return -EIO;
  858. /* scan complete use sleep_power_next, need to be updated */
  859. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  860. if (test_bit(S_SCANNING, &il->status) && !force) {
  861. D_INFO("Defer power set mode while scanning\n");
  862. return 0;
  863. }
  864. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  865. set_bit(S_POWER_PMI, &il->status);
  866. ret = il_set_power(il, cmd);
  867. if (!ret) {
  868. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  869. clear_bit(S_POWER_PMI, &il->status);
  870. if (il->cfg->ops->lib->update_chain_flags && update_chains)
  871. il->cfg->ops->lib->update_chain_flags(il);
  872. else if (il->cfg->ops->lib->update_chain_flags)
  873. D_POWER(
  874. "Cannot update the power, chain noise "
  875. "calibration running: %d\n",
  876. il->chain_noise_data.state);
  877. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  878. } else
  879. IL_ERR("set power fail, ret = %d", ret);
  880. return ret;
  881. }
  882. int il_power_update_mode(struct il_priv *il, bool force)
  883. {
  884. struct il_powertable_cmd cmd;
  885. il_power_sleep_cam_cmd(il, &cmd);
  886. return il_power_set_mode(il, &cmd, force);
  887. }
  888. EXPORT_SYMBOL(il_power_update_mode);
  889. /* initialize to default */
  890. void il_power_initialize(struct il_priv *il)
  891. {
  892. u16 lctl = il_pcie_link_ctl(il);
  893. il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
  894. il->power_data.debug_sleep_level_override = -1;
  895. memset(&il->power_data.sleep_cmd, 0,
  896. sizeof(il->power_data.sleep_cmd));
  897. }
  898. EXPORT_SYMBOL(il_power_initialize);
  899. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  900. * sending probe req. This should be set long enough to hear probe responses
  901. * from more than one AP. */
  902. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  903. #define IL_ACTIVE_DWELL_TIME_52 (20)
  904. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  905. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  906. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  907. * Must be set longer than active dwell time.
  908. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  909. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  910. #define IL_PASSIVE_DWELL_TIME_52 (10)
  911. #define IL_PASSIVE_DWELL_BASE (100)
  912. #define IL_CHANNEL_TUNE_TIME 5
  913. static int il_send_scan_abort(struct il_priv *il)
  914. {
  915. int ret;
  916. struct il_rx_pkt *pkt;
  917. struct il_host_cmd cmd = {
  918. .id = C_SCAN_ABORT,
  919. .flags = CMD_WANT_SKB,
  920. };
  921. /* Exit instantly with error when device is not ready
  922. * to receive scan abort command or it does not perform
  923. * hardware scan currently */
  924. if (!test_bit(S_READY, &il->status) ||
  925. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  926. !test_bit(S_SCAN_HW, &il->status) ||
  927. test_bit(S_FW_ERROR, &il->status) ||
  928. test_bit(S_EXIT_PENDING, &il->status))
  929. return -EIO;
  930. ret = il_send_cmd_sync(il, &cmd);
  931. if (ret)
  932. return ret;
  933. pkt = (struct il_rx_pkt *)cmd.reply_page;
  934. if (pkt->u.status != CAN_ABORT_STATUS) {
  935. /* The scan abort will return 1 for success or
  936. * 2 for "failure". A failure condition can be
  937. * due to simply not being in an active scan which
  938. * can occur if we send the scan abort before we
  939. * the microcode has notified us that a scan is
  940. * completed. */
  941. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  942. ret = -EIO;
  943. }
  944. il_free_pages(il, cmd.reply_page);
  945. return ret;
  946. }
  947. static void il_complete_scan(struct il_priv *il, bool aborted)
  948. {
  949. /* check if scan was requested from mac80211 */
  950. if (il->scan_request) {
  951. D_SCAN("Complete scan in mac80211\n");
  952. ieee80211_scan_completed(il->hw, aborted);
  953. }
  954. il->scan_vif = NULL;
  955. il->scan_request = NULL;
  956. }
  957. void il_force_scan_end(struct il_priv *il)
  958. {
  959. lockdep_assert_held(&il->mutex);
  960. if (!test_bit(S_SCANNING, &il->status)) {
  961. D_SCAN("Forcing scan end while not scanning\n");
  962. return;
  963. }
  964. D_SCAN("Forcing scan end\n");
  965. clear_bit(S_SCANNING, &il->status);
  966. clear_bit(S_SCAN_HW, &il->status);
  967. clear_bit(S_SCAN_ABORTING, &il->status);
  968. il_complete_scan(il, true);
  969. }
  970. static void il_do_scan_abort(struct il_priv *il)
  971. {
  972. int ret;
  973. lockdep_assert_held(&il->mutex);
  974. if (!test_bit(S_SCANNING, &il->status)) {
  975. D_SCAN("Not performing scan to abort\n");
  976. return;
  977. }
  978. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  979. D_SCAN("Scan abort in progress\n");
  980. return;
  981. }
  982. ret = il_send_scan_abort(il);
  983. if (ret) {
  984. D_SCAN("Send scan abort failed %d\n", ret);
  985. il_force_scan_end(il);
  986. } else
  987. D_SCAN("Successfully send scan abort\n");
  988. }
  989. /**
  990. * il_scan_cancel - Cancel any currently executing HW scan
  991. */
  992. int il_scan_cancel(struct il_priv *il)
  993. {
  994. D_SCAN("Queuing abort scan\n");
  995. queue_work(il->workqueue, &il->abort_scan);
  996. return 0;
  997. }
  998. EXPORT_SYMBOL(il_scan_cancel);
  999. /**
  1000. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1001. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1002. *
  1003. */
  1004. int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1005. {
  1006. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1007. lockdep_assert_held(&il->mutex);
  1008. D_SCAN("Scan cancel timeout\n");
  1009. il_do_scan_abort(il);
  1010. while (time_before_eq(jiffies, timeout)) {
  1011. if (!test_bit(S_SCAN_HW, &il->status))
  1012. break;
  1013. msleep(20);
  1014. }
  1015. return test_bit(S_SCAN_HW, &il->status);
  1016. }
  1017. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1018. /* Service response to C_SCAN (0x80) */
  1019. static void il_hdl_scan(struct il_priv *il,
  1020. struct il_rx_buf *rxb)
  1021. {
  1022. #ifdef CONFIG_IWLEGACY_DEBUG
  1023. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1024. struct il_scanreq_notification *notif =
  1025. (struct il_scanreq_notification *)pkt->u.raw;
  1026. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1027. #endif
  1028. }
  1029. /* Service N_SCAN_START (0x82) */
  1030. static void il_hdl_scan_start(struct il_priv *il,
  1031. struct il_rx_buf *rxb)
  1032. {
  1033. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1034. struct il_scanstart_notification *notif =
  1035. (struct il_scanstart_notification *)pkt->u.raw;
  1036. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1037. D_SCAN("Scan start: "
  1038. "%d [802.11%s] "
  1039. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  1040. notif->channel,
  1041. notif->band ? "bg" : "a",
  1042. le32_to_cpu(notif->tsf_high),
  1043. le32_to_cpu(notif->tsf_low),
  1044. notif->status, notif->beacon_timer);
  1045. }
  1046. /* Service N_SCAN_RESULTS (0x83) */
  1047. static void il_hdl_scan_results(struct il_priv *il,
  1048. struct il_rx_buf *rxb)
  1049. {
  1050. #ifdef CONFIG_IWLEGACY_DEBUG
  1051. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1052. struct il_scanresults_notification *notif =
  1053. (struct il_scanresults_notification *)pkt->u.raw;
  1054. D_SCAN("Scan ch.res: "
  1055. "%d [802.11%s] "
  1056. "(TSF: 0x%08X:%08X) - %d "
  1057. "elapsed=%lu usec\n",
  1058. notif->channel,
  1059. notif->band ? "bg" : "a",
  1060. le32_to_cpu(notif->tsf_high),
  1061. le32_to_cpu(notif->tsf_low),
  1062. le32_to_cpu(notif->stats[0]),
  1063. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1064. #endif
  1065. }
  1066. /* Service N_SCAN_COMPLETE (0x84) */
  1067. static void il_hdl_scan_complete(struct il_priv *il,
  1068. struct il_rx_buf *rxb)
  1069. {
  1070. #ifdef CONFIG_IWLEGACY_DEBUG
  1071. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1072. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1073. #endif
  1074. D_SCAN(
  1075. "Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1076. scan_notif->scanned_channels,
  1077. scan_notif->tsf_low,
  1078. scan_notif->tsf_high, scan_notif->status);
  1079. /* The HW is no longer scanning */
  1080. clear_bit(S_SCAN_HW, &il->status);
  1081. D_SCAN("Scan on %sGHz took %dms\n",
  1082. (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
  1083. jiffies_to_msecs(jiffies - il->scan_start));
  1084. queue_work(il->workqueue, &il->scan_completed);
  1085. }
  1086. void il_setup_rx_scan_handlers(struct il_priv *il)
  1087. {
  1088. /* scan handlers */
  1089. il->handlers[C_SCAN] = il_hdl_scan;
  1090. il->handlers[N_SCAN_START] =
  1091. il_hdl_scan_start;
  1092. il->handlers[N_SCAN_RESULTS] =
  1093. il_hdl_scan_results;
  1094. il->handlers[N_SCAN_COMPLETE] =
  1095. il_hdl_scan_complete;
  1096. }
  1097. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1098. inline u16 il_get_active_dwell_time(struct il_priv *il,
  1099. enum ieee80211_band band,
  1100. u8 n_probes)
  1101. {
  1102. if (band == IEEE80211_BAND_5GHZ)
  1103. return IL_ACTIVE_DWELL_TIME_52 +
  1104. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1105. else
  1106. return IL_ACTIVE_DWELL_TIME_24 +
  1107. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1108. }
  1109. EXPORT_SYMBOL(il_get_active_dwell_time);
  1110. u16 il_get_passive_dwell_time(struct il_priv *il,
  1111. enum ieee80211_band band,
  1112. struct ieee80211_vif *vif)
  1113. {
  1114. struct il_rxon_context *ctx = &il->ctx;
  1115. u16 value;
  1116. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  1117. IL_PASSIVE_DWELL_BASE + IL_PASSIVE_DWELL_TIME_24 :
  1118. IL_PASSIVE_DWELL_BASE + IL_PASSIVE_DWELL_TIME_52;
  1119. if (il_is_any_associated(il)) {
  1120. /*
  1121. * If we're associated, we clamp the maximum passive
  1122. * dwell time to be 98% of the smallest beacon interval
  1123. * (minus 2 * channel tune time)
  1124. */
  1125. value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0;
  1126. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1127. value = IL_PASSIVE_DWELL_BASE;
  1128. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1129. passive = min(value, passive);
  1130. }
  1131. return passive;
  1132. }
  1133. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1134. void il_init_scan_params(struct il_priv *il)
  1135. {
  1136. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1137. if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
  1138. il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
  1139. if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
  1140. il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
  1141. }
  1142. EXPORT_SYMBOL(il_init_scan_params);
  1143. static int il_scan_initiate(struct il_priv *il,
  1144. struct ieee80211_vif *vif)
  1145. {
  1146. int ret;
  1147. lockdep_assert_held(&il->mutex);
  1148. if (WARN_ON(!il->cfg->ops->utils->request_scan))
  1149. return -EOPNOTSUPP;
  1150. cancel_delayed_work(&il->scan_check);
  1151. if (!il_is_ready_rf(il)) {
  1152. IL_WARN("Request scan called when driver not ready.\n");
  1153. return -EIO;
  1154. }
  1155. if (test_bit(S_SCAN_HW, &il->status)) {
  1156. D_SCAN(
  1157. "Multiple concurrent scan requests in parallel.\n");
  1158. return -EBUSY;
  1159. }
  1160. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1161. D_SCAN("Scan request while abort pending.\n");
  1162. return -EBUSY;
  1163. }
  1164. D_SCAN("Starting scan...\n");
  1165. set_bit(S_SCANNING, &il->status);
  1166. il->scan_start = jiffies;
  1167. ret = il->cfg->ops->utils->request_scan(il, vif);
  1168. if (ret) {
  1169. clear_bit(S_SCANNING, &il->status);
  1170. return ret;
  1171. }
  1172. queue_delayed_work(il->workqueue, &il->scan_check,
  1173. IL_SCAN_CHECK_WATCHDOG);
  1174. return 0;
  1175. }
  1176. int il_mac_hw_scan(struct ieee80211_hw *hw,
  1177. struct ieee80211_vif *vif,
  1178. struct cfg80211_scan_request *req)
  1179. {
  1180. struct il_priv *il = hw->priv;
  1181. int ret;
  1182. D_MAC80211("enter\n");
  1183. if (req->n_channels == 0)
  1184. return -EINVAL;
  1185. mutex_lock(&il->mutex);
  1186. if (test_bit(S_SCANNING, &il->status)) {
  1187. D_SCAN("Scan already in progress.\n");
  1188. ret = -EAGAIN;
  1189. goto out_unlock;
  1190. }
  1191. /* mac80211 will only ask for one band at a time */
  1192. il->scan_request = req;
  1193. il->scan_vif = vif;
  1194. il->scan_band = req->channels[0]->band;
  1195. ret = il_scan_initiate(il, vif);
  1196. D_MAC80211("leave\n");
  1197. out_unlock:
  1198. mutex_unlock(&il->mutex);
  1199. return ret;
  1200. }
  1201. EXPORT_SYMBOL(il_mac_hw_scan);
  1202. static void il_bg_scan_check(struct work_struct *data)
  1203. {
  1204. struct il_priv *il =
  1205. container_of(data, struct il_priv, scan_check.work);
  1206. D_SCAN("Scan check work\n");
  1207. /* Since we are here firmware does not finish scan and
  1208. * most likely is in bad shape, so we don't bother to
  1209. * send abort command, just force scan complete to mac80211 */
  1210. mutex_lock(&il->mutex);
  1211. il_force_scan_end(il);
  1212. mutex_unlock(&il->mutex);
  1213. }
  1214. /**
  1215. * il_fill_probe_req - fill in all required fields and IE for probe request
  1216. */
  1217. u16
  1218. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1219. const u8 *ta, const u8 *ies, int ie_len, int left)
  1220. {
  1221. int len = 0;
  1222. u8 *pos = NULL;
  1223. /* Make sure there is enough space for the probe request,
  1224. * two mandatory IEs and the data */
  1225. left -= 24;
  1226. if (left < 0)
  1227. return 0;
  1228. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1229. memcpy(frame->da, il_bcast_addr, ETH_ALEN);
  1230. memcpy(frame->sa, ta, ETH_ALEN);
  1231. memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
  1232. frame->seq_ctrl = 0;
  1233. len += 24;
  1234. /* ...next IE... */
  1235. pos = &frame->u.probe_req.variable[0];
  1236. /* fill in our indirect SSID IE */
  1237. left -= 2;
  1238. if (left < 0)
  1239. return 0;
  1240. *pos++ = WLAN_EID_SSID;
  1241. *pos++ = 0;
  1242. len += 2;
  1243. if (WARN_ON(left < ie_len))
  1244. return len;
  1245. if (ies && ie_len) {
  1246. memcpy(pos, ies, ie_len);
  1247. len += ie_len;
  1248. }
  1249. return (u16)len;
  1250. }
  1251. EXPORT_SYMBOL(il_fill_probe_req);
  1252. static void il_bg_abort_scan(struct work_struct *work)
  1253. {
  1254. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1255. D_SCAN("Abort scan work\n");
  1256. /* We keep scan_check work queued in case when firmware will not
  1257. * report back scan completed notification */
  1258. mutex_lock(&il->mutex);
  1259. il_scan_cancel_timeout(il, 200);
  1260. mutex_unlock(&il->mutex);
  1261. }
  1262. static void il_bg_scan_completed(struct work_struct *work)
  1263. {
  1264. struct il_priv *il =
  1265. container_of(work, struct il_priv, scan_completed);
  1266. bool aborted;
  1267. D_SCAN("Completed scan.\n");
  1268. cancel_delayed_work(&il->scan_check);
  1269. mutex_lock(&il->mutex);
  1270. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1271. if (aborted)
  1272. D_SCAN("Aborted scan completed.\n");
  1273. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1274. D_SCAN("Scan already completed.\n");
  1275. goto out_settings;
  1276. }
  1277. il_complete_scan(il, aborted);
  1278. out_settings:
  1279. /* Can we still talk to firmware ? */
  1280. if (!il_is_ready_rf(il))
  1281. goto out;
  1282. /*
  1283. * We do not commit power settings while scan is pending,
  1284. * do it now if the settings changed.
  1285. */
  1286. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1287. il_set_tx_power(il, il->tx_power_next, false);
  1288. il->cfg->ops->utils->post_scan(il);
  1289. out:
  1290. mutex_unlock(&il->mutex);
  1291. }
  1292. void il_setup_scan_deferred_work(struct il_priv *il)
  1293. {
  1294. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1295. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1296. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1297. }
  1298. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1299. void il_cancel_scan_deferred_work(struct il_priv *il)
  1300. {
  1301. cancel_work_sync(&il->abort_scan);
  1302. cancel_work_sync(&il->scan_completed);
  1303. if (cancel_delayed_work_sync(&il->scan_check)) {
  1304. mutex_lock(&il->mutex);
  1305. il_force_scan_end(il);
  1306. mutex_unlock(&il->mutex);
  1307. }
  1308. }
  1309. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1310. /* il->sta_lock must be held */
  1311. static void il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1312. {
  1313. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1314. IL_ERR(
  1315. "ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1316. sta_id, il->stations[sta_id].sta.sta.addr);
  1317. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1318. D_ASSOC(
  1319. "STA id %u addr %pM already present"
  1320. " in uCode (according to driver)\n",
  1321. sta_id, il->stations[sta_id].sta.sta.addr);
  1322. } else {
  1323. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1324. D_ASSOC("Added STA id %u addr %pM to uCode\n",
  1325. sta_id, il->stations[sta_id].sta.sta.addr);
  1326. }
  1327. }
  1328. static int il_process_add_sta_resp(struct il_priv *il,
  1329. struct il_addsta_cmd *addsta,
  1330. struct il_rx_pkt *pkt,
  1331. bool sync)
  1332. {
  1333. u8 sta_id = addsta->sta.sta_id;
  1334. unsigned long flags;
  1335. int ret = -EIO;
  1336. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1337. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n",
  1338. pkt->hdr.flags);
  1339. return ret;
  1340. }
  1341. D_INFO("Processing response for adding station %u\n",
  1342. sta_id);
  1343. spin_lock_irqsave(&il->sta_lock, flags);
  1344. switch (pkt->u.add_sta.status) {
  1345. case ADD_STA_SUCCESS_MSK:
  1346. D_INFO("C_ADD_STA PASSED\n");
  1347. il_sta_ucode_activate(il, sta_id);
  1348. ret = 0;
  1349. break;
  1350. case ADD_STA_NO_ROOM_IN_TBL:
  1351. IL_ERR("Adding station %d failed, no room in table.\n",
  1352. sta_id);
  1353. break;
  1354. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1355. IL_ERR(
  1356. "Adding station %d failed, no block ack resource.\n",
  1357. sta_id);
  1358. break;
  1359. case ADD_STA_MODIFY_NON_EXIST_STA:
  1360. IL_ERR("Attempting to modify non-existing station %d\n",
  1361. sta_id);
  1362. break;
  1363. default:
  1364. D_ASSOC("Received C_ADD_STA:(0x%08X)\n",
  1365. pkt->u.add_sta.status);
  1366. break;
  1367. }
  1368. D_INFO("%s station id %u addr %pM\n",
  1369. il->stations[sta_id].sta.mode ==
  1370. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added",
  1371. sta_id, il->stations[sta_id].sta.sta.addr);
  1372. /*
  1373. * XXX: The MAC address in the command buffer is often changed from
  1374. * the original sent to the device. That is, the MAC address
  1375. * written to the command buffer often is not the same MAC address
  1376. * read from the command buffer when the command returns. This
  1377. * issue has not yet been resolved and this debugging is left to
  1378. * observe the problem.
  1379. */
  1380. D_INFO("%s station according to cmd buffer %pM\n",
  1381. il->stations[sta_id].sta.mode ==
  1382. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added",
  1383. addsta->sta.addr);
  1384. spin_unlock_irqrestore(&il->sta_lock, flags);
  1385. return ret;
  1386. }
  1387. static void il_add_sta_callback(struct il_priv *il,
  1388. struct il_device_cmd *cmd,
  1389. struct il_rx_pkt *pkt)
  1390. {
  1391. struct il_addsta_cmd *addsta =
  1392. (struct il_addsta_cmd *)cmd->cmd.payload;
  1393. il_process_add_sta_resp(il, addsta, pkt, false);
  1394. }
  1395. int il_send_add_sta(struct il_priv *il,
  1396. struct il_addsta_cmd *sta, u8 flags)
  1397. {
  1398. struct il_rx_pkt *pkt = NULL;
  1399. int ret = 0;
  1400. u8 data[sizeof(*sta)];
  1401. struct il_host_cmd cmd = {
  1402. .id = C_ADD_STA,
  1403. .flags = flags,
  1404. .data = data,
  1405. };
  1406. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1407. D_INFO("Adding sta %u (%pM) %ssynchronously\n",
  1408. sta_id, sta->sta.addr, flags & CMD_ASYNC ? "a" : "");
  1409. if (flags & CMD_ASYNC)
  1410. cmd.callback = il_add_sta_callback;
  1411. else {
  1412. cmd.flags |= CMD_WANT_SKB;
  1413. might_sleep();
  1414. }
  1415. cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data);
  1416. ret = il_send_cmd(il, &cmd);
  1417. if (ret || (flags & CMD_ASYNC))
  1418. return ret;
  1419. if (ret == 0) {
  1420. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1421. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1422. }
  1423. il_free_pages(il, cmd.reply_page);
  1424. return ret;
  1425. }
  1426. EXPORT_SYMBOL(il_send_add_sta);
  1427. static void il_set_ht_add_station(struct il_priv *il, u8 idx,
  1428. struct ieee80211_sta *sta,
  1429. struct il_rxon_context *ctx)
  1430. {
  1431. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
  1432. __le32 sta_flags;
  1433. u8 mimo_ps_mode;
  1434. if (!sta || !sta_ht_inf->ht_supported)
  1435. goto done;
  1436. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
  1437. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1438. (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ?
  1439. "static" :
  1440. (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ?
  1441. "dynamic" : "disabled");
  1442. sta_flags = il->stations[idx].sta.station_flags;
  1443. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1444. switch (mimo_ps_mode) {
  1445. case WLAN_HT_CAP_SM_PS_STATIC:
  1446. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1447. break;
  1448. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  1449. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1450. break;
  1451. case WLAN_HT_CAP_SM_PS_DISABLED:
  1452. break;
  1453. default:
  1454. IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
  1455. break;
  1456. }
  1457. sta_flags |= cpu_to_le32(
  1458. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1459. sta_flags |= cpu_to_le32(
  1460. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1461. if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap))
  1462. sta_flags |= STA_FLG_HT40_EN_MSK;
  1463. else
  1464. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1465. il->stations[idx].sta.station_flags = sta_flags;
  1466. done:
  1467. return;
  1468. }
  1469. /**
  1470. * il_prep_station - Prepare station information for addition
  1471. *
  1472. * should be called with sta_lock held
  1473. */
  1474. u8 il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
  1475. const u8 *addr, bool is_ap, struct ieee80211_sta *sta)
  1476. {
  1477. struct il_station_entry *station;
  1478. int i;
  1479. u8 sta_id = IL_INVALID_STATION;
  1480. u16 rate;
  1481. if (is_ap)
  1482. sta_id = ctx->ap_sta_id;
  1483. else if (is_broadcast_ether_addr(addr))
  1484. sta_id = ctx->bcast_sta_id;
  1485. else
  1486. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1487. if (!compare_ether_addr(il->stations[i].sta.sta.addr,
  1488. addr)) {
  1489. sta_id = i;
  1490. break;
  1491. }
  1492. if (!il->stations[i].used &&
  1493. sta_id == IL_INVALID_STATION)
  1494. sta_id = i;
  1495. }
  1496. /*
  1497. * These two conditions have the same outcome, but keep them
  1498. * separate
  1499. */
  1500. if (unlikely(sta_id == IL_INVALID_STATION))
  1501. return sta_id;
  1502. /*
  1503. * uCode is not able to deal with multiple requests to add a
  1504. * station. Keep track if one is in progress so that we do not send
  1505. * another.
  1506. */
  1507. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1508. D_INFO(
  1509. "STA %d already in process of being added.\n",
  1510. sta_id);
  1511. return sta_id;
  1512. }
  1513. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1514. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1515. !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
  1516. D_ASSOC(
  1517. "STA %d (%pM) already added, not adding again.\n",
  1518. sta_id, addr);
  1519. return sta_id;
  1520. }
  1521. station = &il->stations[sta_id];
  1522. station->used = IL_STA_DRIVER_ACTIVE;
  1523. D_ASSOC("Add STA to driver ID %d: %pM\n",
  1524. sta_id, addr);
  1525. il->num_stations++;
  1526. /* Set up the C_ADD_STA command to send to device */
  1527. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1528. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1529. station->sta.mode = 0;
  1530. station->sta.sta.sta_id = sta_id;
  1531. station->sta.station_flags = ctx->station_flags;
  1532. station->ctxid = ctx->ctxid;
  1533. if (sta) {
  1534. struct il_station_priv_common *sta_priv;
  1535. sta_priv = (void *)sta->drv_priv;
  1536. sta_priv->ctx = ctx;
  1537. }
  1538. /*
  1539. * OK to call unconditionally, since local stations (IBSS BSSID
  1540. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1541. * doesn't allow HT IBSS.
  1542. */
  1543. il_set_ht_add_station(il, sta_id, sta, ctx);
  1544. /* 3945 only */
  1545. rate = (il->band == IEEE80211_BAND_5GHZ) ?
  1546. RATE_6M_PLCP : RATE_1M_PLCP;
  1547. /* Turn on both antennas for the station... */
  1548. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1549. return sta_id;
  1550. }
  1551. EXPORT_SYMBOL_GPL(il_prep_station);
  1552. #define STA_WAIT_TIMEOUT (HZ/2)
  1553. /**
  1554. * il_add_station_common -
  1555. */
  1556. int
  1557. il_add_station_common(struct il_priv *il,
  1558. struct il_rxon_context *ctx,
  1559. const u8 *addr, bool is_ap,
  1560. struct ieee80211_sta *sta, u8 *sta_id_r)
  1561. {
  1562. unsigned long flags_spin;
  1563. int ret = 0;
  1564. u8 sta_id;
  1565. struct il_addsta_cmd sta_cmd;
  1566. *sta_id_r = 0;
  1567. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1568. sta_id = il_prep_station(il, ctx, addr, is_ap, sta);
  1569. if (sta_id == IL_INVALID_STATION) {
  1570. IL_ERR("Unable to prepare station %pM for addition\n",
  1571. addr);
  1572. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1573. return -EINVAL;
  1574. }
  1575. /*
  1576. * uCode is not able to deal with multiple requests to add a
  1577. * station. Keep track if one is in progress so that we do not send
  1578. * another.
  1579. */
  1580. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1581. D_INFO(
  1582. "STA %d already in process of being added.\n",
  1583. sta_id);
  1584. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1585. return -EEXIST;
  1586. }
  1587. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1588. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1589. D_ASSOC(
  1590. "STA %d (%pM) already added, not adding again.\n",
  1591. sta_id, addr);
  1592. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1593. return -EEXIST;
  1594. }
  1595. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1596. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1597. sizeof(struct il_addsta_cmd));
  1598. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1599. /* Add station to device's station table */
  1600. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1601. if (ret) {
  1602. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1603. IL_ERR("Adding station %pM failed.\n",
  1604. il->stations[sta_id].sta.sta.addr);
  1605. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1606. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1607. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1608. }
  1609. *sta_id_r = sta_id;
  1610. return ret;
  1611. }
  1612. EXPORT_SYMBOL(il_add_station_common);
  1613. /**
  1614. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1615. *
  1616. * il->sta_lock must be held
  1617. */
  1618. static void il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1619. {
  1620. /* Ucode must be active and driver must be non active */
  1621. if ((il->stations[sta_id].used &
  1622. (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1623. IL_STA_UCODE_ACTIVE)
  1624. IL_ERR("removed non active STA %u\n", sta_id);
  1625. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1626. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1627. D_ASSOC("Removed STA %u\n", sta_id);
  1628. }
  1629. static int il_send_remove_station(struct il_priv *il,
  1630. const u8 *addr, int sta_id,
  1631. bool temporary)
  1632. {
  1633. struct il_rx_pkt *pkt;
  1634. int ret;
  1635. unsigned long flags_spin;
  1636. struct il_rem_sta_cmd rm_sta_cmd;
  1637. struct il_host_cmd cmd = {
  1638. .id = C_REM_STA,
  1639. .len = sizeof(struct il_rem_sta_cmd),
  1640. .flags = CMD_SYNC,
  1641. .data = &rm_sta_cmd,
  1642. };
  1643. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1644. rm_sta_cmd.num_sta = 1;
  1645. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1646. cmd.flags |= CMD_WANT_SKB;
  1647. ret = il_send_cmd(il, &cmd);
  1648. if (ret)
  1649. return ret;
  1650. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1651. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1652. IL_ERR("Bad return from C_REM_STA (0x%08X)\n",
  1653. pkt->hdr.flags);
  1654. ret = -EIO;
  1655. }
  1656. if (!ret) {
  1657. switch (pkt->u.rem_sta.status) {
  1658. case REM_STA_SUCCESS_MSK:
  1659. if (!temporary) {
  1660. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1661. il_sta_ucode_deactivate(il, sta_id);
  1662. spin_unlock_irqrestore(&il->sta_lock,
  1663. flags_spin);
  1664. }
  1665. D_ASSOC("C_REM_STA PASSED\n");
  1666. break;
  1667. default:
  1668. ret = -EIO;
  1669. IL_ERR("C_REM_STA failed\n");
  1670. break;
  1671. }
  1672. }
  1673. il_free_pages(il, cmd.reply_page);
  1674. return ret;
  1675. }
  1676. /**
  1677. * il_remove_station - Remove driver's knowledge of station.
  1678. */
  1679. int il_remove_station(struct il_priv *il, const u8 sta_id,
  1680. const u8 *addr)
  1681. {
  1682. unsigned long flags;
  1683. if (!il_is_ready(il)) {
  1684. D_INFO(
  1685. "Unable to remove station %pM, device not ready.\n",
  1686. addr);
  1687. /*
  1688. * It is typical for stations to be removed when we are
  1689. * going down. Return success since device will be down
  1690. * soon anyway
  1691. */
  1692. return 0;
  1693. }
  1694. D_ASSOC("Removing STA from driver:%d %pM\n",
  1695. sta_id, addr);
  1696. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1697. return -EINVAL;
  1698. spin_lock_irqsave(&il->sta_lock, flags);
  1699. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1700. D_INFO("Removing %pM but non DRIVER active\n",
  1701. addr);
  1702. goto out_err;
  1703. }
  1704. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1705. D_INFO("Removing %pM but non UCODE active\n",
  1706. addr);
  1707. goto out_err;
  1708. }
  1709. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1710. kfree(il->stations[sta_id].lq);
  1711. il->stations[sta_id].lq = NULL;
  1712. }
  1713. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1714. il->num_stations--;
  1715. BUG_ON(il->num_stations < 0);
  1716. spin_unlock_irqrestore(&il->sta_lock, flags);
  1717. return il_send_remove_station(il, addr, sta_id, false);
  1718. out_err:
  1719. spin_unlock_irqrestore(&il->sta_lock, flags);
  1720. return -EINVAL;
  1721. }
  1722. EXPORT_SYMBOL_GPL(il_remove_station);
  1723. /**
  1724. * il_clear_ucode_stations - clear ucode station table bits
  1725. *
  1726. * This function clears all the bits in the driver indicating
  1727. * which stations are active in the ucode. Call when something
  1728. * other than explicit station management would cause this in
  1729. * the ucode, e.g. unassociated RXON.
  1730. */
  1731. void il_clear_ucode_stations(struct il_priv *il,
  1732. struct il_rxon_context *ctx)
  1733. {
  1734. int i;
  1735. unsigned long flags_spin;
  1736. bool cleared = false;
  1737. D_INFO("Clearing ucode stations in driver\n");
  1738. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1739. for (i = 0; i < il->hw_params.max_stations; i++) {
  1740. if (ctx && ctx->ctxid != il->stations[i].ctxid)
  1741. continue;
  1742. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1743. D_INFO(
  1744. "Clearing ucode active for station %d\n", i);
  1745. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1746. cleared = true;
  1747. }
  1748. }
  1749. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1750. if (!cleared)
  1751. D_INFO(
  1752. "No active stations found to be cleared\n");
  1753. }
  1754. EXPORT_SYMBOL(il_clear_ucode_stations);
  1755. /**
  1756. * il_restore_stations() - Restore driver known stations to device
  1757. *
  1758. * All stations considered active by driver, but not present in ucode, is
  1759. * restored.
  1760. *
  1761. * Function sleeps.
  1762. */
  1763. void
  1764. il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx)
  1765. {
  1766. struct il_addsta_cmd sta_cmd;
  1767. struct il_link_quality_cmd lq;
  1768. unsigned long flags_spin;
  1769. int i;
  1770. bool found = false;
  1771. int ret;
  1772. bool send_lq;
  1773. if (!il_is_ready(il)) {
  1774. D_INFO(
  1775. "Not ready yet, not restoring any stations.\n");
  1776. return;
  1777. }
  1778. D_ASSOC("Restoring all known stations ... start.\n");
  1779. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1780. for (i = 0; i < il->hw_params.max_stations; i++) {
  1781. if (ctx->ctxid != il->stations[i].ctxid)
  1782. continue;
  1783. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1784. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1785. D_ASSOC("Restoring sta %pM\n",
  1786. il->stations[i].sta.sta.addr);
  1787. il->stations[i].sta.mode = 0;
  1788. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1789. found = true;
  1790. }
  1791. }
  1792. for (i = 0; i < il->hw_params.max_stations; i++) {
  1793. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1794. memcpy(&sta_cmd, &il->stations[i].sta,
  1795. sizeof(struct il_addsta_cmd));
  1796. send_lq = false;
  1797. if (il->stations[i].lq) {
  1798. memcpy(&lq, il->stations[i].lq,
  1799. sizeof(struct il_link_quality_cmd));
  1800. send_lq = true;
  1801. }
  1802. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1803. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1804. if (ret) {
  1805. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1806. IL_ERR("Adding station %pM failed.\n",
  1807. il->stations[i].sta.sta.addr);
  1808. il->stations[i].used &=
  1809. ~IL_STA_DRIVER_ACTIVE;
  1810. il->stations[i].used &=
  1811. ~IL_STA_UCODE_INPROGRESS;
  1812. spin_unlock_irqrestore(&il->sta_lock,
  1813. flags_spin);
  1814. }
  1815. /*
  1816. * Rate scaling has already been initialized, send
  1817. * current LQ command
  1818. */
  1819. if (send_lq)
  1820. il_send_lq_cmd(il, ctx, &lq,
  1821. CMD_SYNC, true);
  1822. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1823. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1824. }
  1825. }
  1826. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1827. if (!found)
  1828. D_INFO("Restoring all known stations"
  1829. " .... no stations to be restored.\n");
  1830. else
  1831. D_INFO("Restoring all known stations"
  1832. " .... complete.\n");
  1833. }
  1834. EXPORT_SYMBOL(il_restore_stations);
  1835. int il_get_free_ucode_key_idx(struct il_priv *il)
  1836. {
  1837. int i;
  1838. for (i = 0; i < il->sta_key_max_num; i++)
  1839. if (!test_and_set_bit(i, &il->ucode_key_table))
  1840. return i;
  1841. return WEP_INVALID_OFFSET;
  1842. }
  1843. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1844. void il_dealloc_bcast_stations(struct il_priv *il)
  1845. {
  1846. unsigned long flags;
  1847. int i;
  1848. spin_lock_irqsave(&il->sta_lock, flags);
  1849. for (i = 0; i < il->hw_params.max_stations; i++) {
  1850. if (!(il->stations[i].used & IL_STA_BCAST))
  1851. continue;
  1852. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1853. il->num_stations--;
  1854. BUG_ON(il->num_stations < 0);
  1855. kfree(il->stations[i].lq);
  1856. il->stations[i].lq = NULL;
  1857. }
  1858. spin_unlock_irqrestore(&il->sta_lock, flags);
  1859. }
  1860. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1861. #ifdef CONFIG_IWLEGACY_DEBUG
  1862. static void il_dump_lq_cmd(struct il_priv *il,
  1863. struct il_link_quality_cmd *lq)
  1864. {
  1865. int i;
  1866. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1867. D_RATE("lq ant 0x%X 0x%X\n",
  1868. lq->general_params.single_stream_ant_msk,
  1869. lq->general_params.dual_stream_ant_msk);
  1870. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1871. D_RATE("lq idx %d 0x%X\n",
  1872. i, lq->rs_table[i].rate_n_flags);
  1873. }
  1874. #else
  1875. static inline void il_dump_lq_cmd(struct il_priv *il,
  1876. struct il_link_quality_cmd *lq)
  1877. {
  1878. }
  1879. #endif
  1880. /**
  1881. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  1882. *
  1883. * It sometimes happens when a HT rate has been in use and we
  1884. * loose connectivity with AP then mac80211 will first tell us that the
  1885. * current channel is not HT anymore before removing the station. In such a
  1886. * scenario the RXON flags will be updated to indicate we are not
  1887. * communicating HT anymore, but the LQ command may still contain HT rates.
  1888. * Test for this to prevent driver from sending LQ command between the time
  1889. * RXON flags are updated and when LQ command is updated.
  1890. */
  1891. static bool il_is_lq_table_valid(struct il_priv *il,
  1892. struct il_rxon_context *ctx,
  1893. struct il_link_quality_cmd *lq)
  1894. {
  1895. int i;
  1896. if (ctx->ht.enabled)
  1897. return true;
  1898. D_INFO("Channel %u is not an HT channel\n",
  1899. ctx->active.channel);
  1900. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  1901. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) &
  1902. RATE_MCS_HT_MSK) {
  1903. D_INFO(
  1904. "idx %d of LQ expects HT channel\n",
  1905. i);
  1906. return false;
  1907. }
  1908. }
  1909. return true;
  1910. }
  1911. /**
  1912. * il_send_lq_cmd() - Send link quality command
  1913. * @init: This command is sent as part of station initialization right
  1914. * after station has been added.
  1915. *
  1916. * The link quality command is sent as the last step of station creation.
  1917. * This is the special case in which init is set and we call a callback in
  1918. * this case to clear the state indicating that station creation is in
  1919. * progress.
  1920. */
  1921. int il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
  1922. struct il_link_quality_cmd *lq, u8 flags, bool init)
  1923. {
  1924. int ret = 0;
  1925. unsigned long flags_spin;
  1926. struct il_host_cmd cmd = {
  1927. .id = C_TX_LINK_QUALITY_CMD,
  1928. .len = sizeof(struct il_link_quality_cmd),
  1929. .flags = flags,
  1930. .data = lq,
  1931. };
  1932. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  1933. return -EINVAL;
  1934. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1935. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1936. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1937. return -EINVAL;
  1938. }
  1939. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1940. il_dump_lq_cmd(il, lq);
  1941. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  1942. if (il_is_lq_table_valid(il, ctx, lq))
  1943. ret = il_send_cmd(il, &cmd);
  1944. else
  1945. ret = -EINVAL;
  1946. if (cmd.flags & CMD_ASYNC)
  1947. return ret;
  1948. if (init) {
  1949. D_INFO("init LQ command complete,"
  1950. " clearing sta addition status for sta %d\n",
  1951. lq->sta_id);
  1952. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1953. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1954. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1955. }
  1956. return ret;
  1957. }
  1958. EXPORT_SYMBOL(il_send_lq_cmd);
  1959. int il_mac_sta_remove(struct ieee80211_hw *hw,
  1960. struct ieee80211_vif *vif,
  1961. struct ieee80211_sta *sta)
  1962. {
  1963. struct il_priv *il = hw->priv;
  1964. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  1965. int ret;
  1966. D_INFO("received request to remove station %pM\n",
  1967. sta->addr);
  1968. mutex_lock(&il->mutex);
  1969. D_INFO("proceeding to remove station %pM\n",
  1970. sta->addr);
  1971. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  1972. if (ret)
  1973. IL_ERR("Error removing station %pM\n",
  1974. sta->addr);
  1975. mutex_unlock(&il->mutex);
  1976. return ret;
  1977. }
  1978. EXPORT_SYMBOL(il_mac_sta_remove);
  1979. /************************** RX-FUNCTIONS ****************************/
  1980. /*
  1981. * Rx theory of operation
  1982. *
  1983. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  1984. * each of which point to Receive Buffers to be filled by the NIC. These get
  1985. * used not only for Rx frames, but for any command response or notification
  1986. * from the NIC. The driver and NIC manage the Rx buffers by means
  1987. * of idxes into the circular buffer.
  1988. *
  1989. * Rx Queue Indexes
  1990. * The host/firmware share two idx registers for managing the Rx buffers.
  1991. *
  1992. * The READ idx maps to the first position that the firmware may be writing
  1993. * to -- the driver can read up to (but not including) this position and get
  1994. * good data.
  1995. * The READ idx is managed by the firmware once the card is enabled.
  1996. *
  1997. * The WRITE idx maps to the last position the driver has read from -- the
  1998. * position preceding WRITE is the last slot the firmware can place a packet.
  1999. *
  2000. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2001. * WRITE = READ.
  2002. *
  2003. * During initialization, the host sets up the READ queue position to the first
  2004. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2005. *
  2006. * When the firmware places a packet in a buffer, it will advance the READ idx
  2007. * and fire the RX interrupt. The driver can then query the READ idx and
  2008. * process as many packets as possible, moving the WRITE idx forward as it
  2009. * resets the Rx queue buffers with new memory.
  2010. *
  2011. * The management in the driver is as follows:
  2012. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2013. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2014. * to replenish the iwl->rxq->rx_free.
  2015. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2016. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2017. * 'processed' and 'read' driver idxes as well)
  2018. * + A received packet is processed and handed to the kernel network stack,
  2019. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2020. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2021. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2022. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2023. * were enough free buffers and RX_STALLED is set it is cleared.
  2024. *
  2025. *
  2026. * Driver sequence:
  2027. *
  2028. * il_rx_queue_alloc() Allocates rx_free
  2029. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2030. * il_rx_queue_restock
  2031. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2032. * queue, updates firmware pointers, and updates
  2033. * the WRITE idx. If insufficient rx_free buffers
  2034. * are available, schedules il_rx_replenish
  2035. *
  2036. * -- enable interrupts --
  2037. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2038. * READ IDX, detaching the SKB from the pool.
  2039. * Moves the packet buffer from queue to rx_used.
  2040. * Calls il_rx_queue_restock to refill any empty
  2041. * slots.
  2042. * ...
  2043. *
  2044. */
  2045. /**
  2046. * il_rx_queue_space - Return number of free slots available in queue.
  2047. */
  2048. int il_rx_queue_space(const struct il_rx_queue *q)
  2049. {
  2050. int s = q->read - q->write;
  2051. if (s <= 0)
  2052. s += RX_QUEUE_SIZE;
  2053. /* keep some buffer to not confuse full and empty queue */
  2054. s -= 2;
  2055. if (s < 0)
  2056. s = 0;
  2057. return s;
  2058. }
  2059. EXPORT_SYMBOL(il_rx_queue_space);
  2060. /**
  2061. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2062. */
  2063. void
  2064. il_rx_queue_update_write_ptr(struct il_priv *il,
  2065. struct il_rx_queue *q)
  2066. {
  2067. unsigned long flags;
  2068. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2069. u32 reg;
  2070. spin_lock_irqsave(&q->lock, flags);
  2071. if (q->need_update == 0)
  2072. goto exit_unlock;
  2073. /* If power-saving is in use, make sure device is awake */
  2074. if (test_bit(S_POWER_PMI, &il->status)) {
  2075. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2076. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2077. D_INFO(
  2078. "Rx queue requesting wakeup,"
  2079. " GP1 = 0x%x\n", reg);
  2080. il_set_bit(il, CSR_GP_CNTRL,
  2081. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2082. goto exit_unlock;
  2083. }
  2084. q->write_actual = (q->write & ~0x7);
  2085. il_wr(il, rx_wrt_ptr_reg,
  2086. q->write_actual);
  2087. /* Else device is assumed to be awake */
  2088. } else {
  2089. /* Device expects a multiple of 8 */
  2090. q->write_actual = (q->write & ~0x7);
  2091. il_wr(il, rx_wrt_ptr_reg,
  2092. q->write_actual);
  2093. }
  2094. q->need_update = 0;
  2095. exit_unlock:
  2096. spin_unlock_irqrestore(&q->lock, flags);
  2097. }
  2098. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2099. int il_rx_queue_alloc(struct il_priv *il)
  2100. {
  2101. struct il_rx_queue *rxq = &il->rxq;
  2102. struct device *dev = &il->pci_dev->dev;
  2103. int i;
  2104. spin_lock_init(&rxq->lock);
  2105. INIT_LIST_HEAD(&rxq->rx_free);
  2106. INIT_LIST_HEAD(&rxq->rx_used);
  2107. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2108. rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2109. GFP_KERNEL);
  2110. if (!rxq->bd)
  2111. goto err_bd;
  2112. rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2113. &rxq->rb_stts_dma, GFP_KERNEL);
  2114. if (!rxq->rb_stts)
  2115. goto err_rb;
  2116. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2117. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2118. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2119. /* Set us so that we have processed and used all buffers, but have
  2120. * not restocked the Rx queue with fresh buffers */
  2121. rxq->read = rxq->write = 0;
  2122. rxq->write_actual = 0;
  2123. rxq->free_count = 0;
  2124. rxq->need_update = 0;
  2125. return 0;
  2126. err_rb:
  2127. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2128. rxq->bd_dma);
  2129. err_bd:
  2130. return -ENOMEM;
  2131. }
  2132. EXPORT_SYMBOL(il_rx_queue_alloc);
  2133. void il_hdl_spectrum_measurement(struct il_priv *il,
  2134. struct il_rx_buf *rxb)
  2135. {
  2136. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2137. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2138. if (!report->state) {
  2139. D_11H(
  2140. "Spectrum Measure Notification: Start\n");
  2141. return;
  2142. }
  2143. memcpy(&il->measure_report, report, sizeof(*report));
  2144. il->measurement_status |= MEASUREMENT_READY;
  2145. }
  2146. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2147. /*
  2148. * returns non-zero if packet should be dropped
  2149. */
  2150. int il_set_decrypted_flag(struct il_priv *il,
  2151. struct ieee80211_hdr *hdr,
  2152. u32 decrypt_res,
  2153. struct ieee80211_rx_status *stats)
  2154. {
  2155. u16 fc = le16_to_cpu(hdr->frame_control);
  2156. /*
  2157. * All contexts have the same setting here due to it being
  2158. * a module parameter, so OK to check any context.
  2159. */
  2160. if (il->ctx.active.filter_flags &
  2161. RXON_FILTER_DIS_DECRYPT_MSK)
  2162. return 0;
  2163. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2164. return 0;
  2165. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2166. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2167. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2168. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2169. * Decryption will be done in SW. */
  2170. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2171. RX_RES_STATUS_BAD_KEY_TTAK)
  2172. break;
  2173. case RX_RES_STATUS_SEC_TYPE_WEP:
  2174. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2175. RX_RES_STATUS_BAD_ICV_MIC) {
  2176. /* bad ICV, the packet is destroyed since the
  2177. * decryption is inplace, drop it */
  2178. D_RX("Packet destroyed\n");
  2179. return -1;
  2180. }
  2181. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2182. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2183. RX_RES_STATUS_DECRYPT_OK) {
  2184. D_RX("hw decrypt successfully!!!\n");
  2185. stats->flag |= RX_FLAG_DECRYPTED;
  2186. }
  2187. break;
  2188. default:
  2189. break;
  2190. }
  2191. return 0;
  2192. }
  2193. EXPORT_SYMBOL(il_set_decrypted_flag);
  2194. /**
  2195. * il_txq_update_write_ptr - Send new write idx to hardware
  2196. */
  2197. void
  2198. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2199. {
  2200. u32 reg = 0;
  2201. int txq_id = txq->q.id;
  2202. if (txq->need_update == 0)
  2203. return;
  2204. /* if we're trying to save power */
  2205. if (test_bit(S_POWER_PMI, &il->status)) {
  2206. /* wake up nic if it's powered down ...
  2207. * uCode will wake up, and interrupt us again, so next
  2208. * time we'll skip this part. */
  2209. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2210. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2211. D_INFO(
  2212. "Tx queue %d requesting wakeup,"
  2213. " GP1 = 0x%x\n", txq_id, reg);
  2214. il_set_bit(il, CSR_GP_CNTRL,
  2215. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2216. return;
  2217. }
  2218. il_wr(il, HBUS_TARG_WRPTR,
  2219. txq->q.write_ptr | (txq_id << 8));
  2220. /*
  2221. * else not in power-save mode,
  2222. * uCode will never sleep when we're
  2223. * trying to tx (during RFKILL, we're not trying to tx).
  2224. */
  2225. } else
  2226. _il_wr(il, HBUS_TARG_WRPTR,
  2227. txq->q.write_ptr | (txq_id << 8));
  2228. txq->need_update = 0;
  2229. }
  2230. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2231. /**
  2232. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2233. */
  2234. void il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2235. {
  2236. struct il_tx_queue *txq = &il->txq[txq_id];
  2237. struct il_queue *q = &txq->q;
  2238. if (q->n_bd == 0)
  2239. return;
  2240. while (q->write_ptr != q->read_ptr) {
  2241. il->cfg->ops->lib->txq_free_tfd(il, txq);
  2242. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2243. }
  2244. }
  2245. EXPORT_SYMBOL(il_tx_queue_unmap);
  2246. /**
  2247. * il_tx_queue_free - Deallocate DMA queue.
  2248. * @txq: Transmit queue to deallocate.
  2249. *
  2250. * Empty queue by removing and destroying all BD's.
  2251. * Free all buffers.
  2252. * 0-fill, but do not free "txq" descriptor structure.
  2253. */
  2254. void il_tx_queue_free(struct il_priv *il, int txq_id)
  2255. {
  2256. struct il_tx_queue *txq = &il->txq[txq_id];
  2257. struct device *dev = &il->pci_dev->dev;
  2258. int i;
  2259. il_tx_queue_unmap(il, txq_id);
  2260. /* De-alloc array of command/tx buffers */
  2261. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2262. kfree(txq->cmd[i]);
  2263. /* De-alloc circular buffer of TFDs */
  2264. if (txq->q.n_bd)
  2265. dma_free_coherent(dev, il->hw_params.tfd_size *
  2266. txq->q.n_bd, txq->tfds, txq->q.dma_addr);
  2267. /* De-alloc array of per-TFD driver data */
  2268. kfree(txq->txb);
  2269. txq->txb = NULL;
  2270. /* deallocate arrays */
  2271. kfree(txq->cmd);
  2272. kfree(txq->meta);
  2273. txq->cmd = NULL;
  2274. txq->meta = NULL;
  2275. /* 0-fill queue descriptor structure */
  2276. memset(txq, 0, sizeof(*txq));
  2277. }
  2278. EXPORT_SYMBOL(il_tx_queue_free);
  2279. /**
  2280. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2281. */
  2282. void il_cmd_queue_unmap(struct il_priv *il)
  2283. {
  2284. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2285. struct il_queue *q = &txq->q;
  2286. int i;
  2287. if (q->n_bd == 0)
  2288. return;
  2289. while (q->read_ptr != q->write_ptr) {
  2290. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2291. if (txq->meta[i].flags & CMD_MAPPED) {
  2292. pci_unmap_single(il->pci_dev,
  2293. dma_unmap_addr(&txq->meta[i], mapping),
  2294. dma_unmap_len(&txq->meta[i], len),
  2295. PCI_DMA_BIDIRECTIONAL);
  2296. txq->meta[i].flags = 0;
  2297. }
  2298. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2299. }
  2300. i = q->n_win;
  2301. if (txq->meta[i].flags & CMD_MAPPED) {
  2302. pci_unmap_single(il->pci_dev,
  2303. dma_unmap_addr(&txq->meta[i], mapping),
  2304. dma_unmap_len(&txq->meta[i], len),
  2305. PCI_DMA_BIDIRECTIONAL);
  2306. txq->meta[i].flags = 0;
  2307. }
  2308. }
  2309. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2310. /**
  2311. * il_cmd_queue_free - Deallocate DMA queue.
  2312. * @txq: Transmit queue to deallocate.
  2313. *
  2314. * Empty queue by removing and destroying all BD's.
  2315. * Free all buffers.
  2316. * 0-fill, but do not free "txq" descriptor structure.
  2317. */
  2318. void il_cmd_queue_free(struct il_priv *il)
  2319. {
  2320. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2321. struct device *dev = &il->pci_dev->dev;
  2322. int i;
  2323. il_cmd_queue_unmap(il);
  2324. /* De-alloc array of command/tx buffers */
  2325. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2326. kfree(txq->cmd[i]);
  2327. /* De-alloc circular buffer of TFDs */
  2328. if (txq->q.n_bd)
  2329. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2330. txq->tfds, txq->q.dma_addr);
  2331. /* deallocate arrays */
  2332. kfree(txq->cmd);
  2333. kfree(txq->meta);
  2334. txq->cmd = NULL;
  2335. txq->meta = NULL;
  2336. /* 0-fill queue descriptor structure */
  2337. memset(txq, 0, sizeof(*txq));
  2338. }
  2339. EXPORT_SYMBOL(il_cmd_queue_free);
  2340. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2341. * DMA services
  2342. *
  2343. * Theory of operation
  2344. *
  2345. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2346. * of buffer descriptors, each of which points to one or more data buffers for
  2347. * the device to read from or fill. Driver and device exchange status of each
  2348. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2349. * entries in each circular buffer, to protect against confusing empty and full
  2350. * queue states.
  2351. *
  2352. * The device reads or writes the data in the queues via the device's several
  2353. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2354. *
  2355. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2356. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2357. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2358. * Tx queue resumed.
  2359. *
  2360. * See more detailed info in 4965.h.
  2361. ***************************************************/
  2362. int il_queue_space(const struct il_queue *q)
  2363. {
  2364. int s = q->read_ptr - q->write_ptr;
  2365. if (q->read_ptr > q->write_ptr)
  2366. s -= q->n_bd;
  2367. if (s <= 0)
  2368. s += q->n_win;
  2369. /* keep some reserve to not confuse empty and full situations */
  2370. s -= 2;
  2371. if (s < 0)
  2372. s = 0;
  2373. return s;
  2374. }
  2375. EXPORT_SYMBOL(il_queue_space);
  2376. /**
  2377. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2378. */
  2379. static int il_queue_init(struct il_priv *il, struct il_queue *q,
  2380. int count, int slots_num, u32 id)
  2381. {
  2382. q->n_bd = count;
  2383. q->n_win = slots_num;
  2384. q->id = id;
  2385. /* count must be power-of-two size, otherwise il_queue_inc_wrap
  2386. * and il_queue_dec_wrap are broken. */
  2387. BUG_ON(!is_power_of_2(count));
  2388. /* slots_num must be power-of-two size, otherwise
  2389. * il_get_cmd_idx is broken. */
  2390. BUG_ON(!is_power_of_2(slots_num));
  2391. q->low_mark = q->n_win / 4;
  2392. if (q->low_mark < 4)
  2393. q->low_mark = 4;
  2394. q->high_mark = q->n_win / 8;
  2395. if (q->high_mark < 2)
  2396. q->high_mark = 2;
  2397. q->write_ptr = q->read_ptr = 0;
  2398. return 0;
  2399. }
  2400. /**
  2401. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2402. */
  2403. static int il_tx_queue_alloc(struct il_priv *il,
  2404. struct il_tx_queue *txq, u32 id)
  2405. {
  2406. struct device *dev = &il->pci_dev->dev;
  2407. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2408. /* Driver ilate data, only for Tx (not command) queues,
  2409. * not shared with device. */
  2410. if (id != il->cmd_queue) {
  2411. txq->txb = kzalloc(sizeof(txq->txb[0]) *
  2412. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  2413. if (!txq->txb) {
  2414. IL_ERR("kmalloc for auxiliary BD "
  2415. "structures failed\n");
  2416. goto error;
  2417. }
  2418. } else {
  2419. txq->txb = NULL;
  2420. }
  2421. /* Circular buffer of transmit frame descriptors (TFDs),
  2422. * shared with device */
  2423. txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
  2424. GFP_KERNEL);
  2425. if (!txq->tfds) {
  2426. IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz);
  2427. goto error;
  2428. }
  2429. txq->q.id = id;
  2430. return 0;
  2431. error:
  2432. kfree(txq->txb);
  2433. txq->txb = NULL;
  2434. return -ENOMEM;
  2435. }
  2436. /**
  2437. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2438. */
  2439. int il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq,
  2440. int slots_num, u32 txq_id)
  2441. {
  2442. int i, len;
  2443. int ret;
  2444. int actual_slots = slots_num;
  2445. /*
  2446. * Alloc buffer array for commands (Tx or other types of commands).
  2447. * For the command queue (#4/#9), allocate command space + one big
  2448. * command for scan, since scan command is very huge; the system will
  2449. * not have two scans at the same time, so only one is needed.
  2450. * For normal Tx queues (all other queues), no super-size command
  2451. * space is needed.
  2452. */
  2453. if (txq_id == il->cmd_queue)
  2454. actual_slots++;
  2455. txq->meta = kzalloc(sizeof(struct il_cmd_meta) * actual_slots,
  2456. GFP_KERNEL);
  2457. txq->cmd = kzalloc(sizeof(struct il_device_cmd *) * actual_slots,
  2458. GFP_KERNEL);
  2459. if (!txq->meta || !txq->cmd)
  2460. goto out_free_arrays;
  2461. len = sizeof(struct il_device_cmd);
  2462. for (i = 0; i < actual_slots; i++) {
  2463. /* only happens for cmd queue */
  2464. if (i == slots_num)
  2465. len = IL_MAX_CMD_SIZE;
  2466. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2467. if (!txq->cmd[i])
  2468. goto err;
  2469. }
  2470. /* Alloc driver data array and TFD circular buffer */
  2471. ret = il_tx_queue_alloc(il, txq, txq_id);
  2472. if (ret)
  2473. goto err;
  2474. txq->need_update = 0;
  2475. /*
  2476. * For the default queues 0-3, set up the swq_id
  2477. * already -- all others need to get one later
  2478. * (if they need one at all).
  2479. */
  2480. if (txq_id < 4)
  2481. il_set_swq_id(txq, txq_id, txq_id);
  2482. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2483. * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
  2484. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2485. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2486. il_queue_init(il, &txq->q,
  2487. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  2488. /* Tell device where to find queue */
  2489. il->cfg->ops->lib->txq_init(il, txq);
  2490. return 0;
  2491. err:
  2492. for (i = 0; i < actual_slots; i++)
  2493. kfree(txq->cmd[i]);
  2494. out_free_arrays:
  2495. kfree(txq->meta);
  2496. kfree(txq->cmd);
  2497. return -ENOMEM;
  2498. }
  2499. EXPORT_SYMBOL(il_tx_queue_init);
  2500. void il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq,
  2501. int slots_num, u32 txq_id)
  2502. {
  2503. int actual_slots = slots_num;
  2504. if (txq_id == il->cmd_queue)
  2505. actual_slots++;
  2506. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2507. txq->need_update = 0;
  2508. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2509. il_queue_init(il, &txq->q,
  2510. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  2511. /* Tell device where to find queue */
  2512. il->cfg->ops->lib->txq_init(il, txq);
  2513. }
  2514. EXPORT_SYMBOL(il_tx_queue_reset);
  2515. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2516. /**
  2517. * il_enqueue_hcmd - enqueue a uCode command
  2518. * @il: device ilate data point
  2519. * @cmd: a point to the ucode command structure
  2520. *
  2521. * The function returns < 0 values to indicate the operation is
  2522. * failed. On success, it turns the idx (> 0) of command in the
  2523. * command queue.
  2524. */
  2525. int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2526. {
  2527. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2528. struct il_queue *q = &txq->q;
  2529. struct il_device_cmd *out_cmd;
  2530. struct il_cmd_meta *out_meta;
  2531. dma_addr_t phys_addr;
  2532. unsigned long flags;
  2533. int len;
  2534. u32 idx;
  2535. u16 fix_size;
  2536. cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
  2537. fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  2538. /* If any of the command structures end up being larger than
  2539. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2540. * we will need to increase the size of the TFD entries
  2541. * Also, check to see if command buffer should not exceed the size
  2542. * of device_cmd and max_cmd_size. */
  2543. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2544. !(cmd->flags & CMD_SIZE_HUGE));
  2545. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2546. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2547. IL_WARN("Not sending command - %s KILL\n",
  2548. il_is_rfkill(il) ? "RF" : "CT");
  2549. return -EIO;
  2550. }
  2551. spin_lock_irqsave(&il->hcmd_lock, flags);
  2552. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2553. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2554. IL_ERR("Restarting adapter due to command queue full\n");
  2555. queue_work(il->workqueue, &il->restart);
  2556. return -ENOSPC;
  2557. }
  2558. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2559. out_cmd = txq->cmd[idx];
  2560. out_meta = &txq->meta[idx];
  2561. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2562. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2563. return -ENOSPC;
  2564. }
  2565. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2566. out_meta->flags = cmd->flags | CMD_MAPPED;
  2567. if (cmd->flags & CMD_WANT_SKB)
  2568. out_meta->source = cmd;
  2569. if (cmd->flags & CMD_ASYNC)
  2570. out_meta->callback = cmd->callback;
  2571. out_cmd->hdr.cmd = cmd->id;
  2572. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  2573. /* At this point, the out_cmd now has all of the incoming cmd
  2574. * information */
  2575. out_cmd->hdr.flags = 0;
  2576. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) |
  2577. IDX_TO_SEQ(q->write_ptr));
  2578. if (cmd->flags & CMD_SIZE_HUGE)
  2579. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2580. len = sizeof(struct il_device_cmd);
  2581. if (idx == TFD_CMD_SLOTS)
  2582. len = IL_MAX_CMD_SIZE;
  2583. #ifdef CONFIG_IWLEGACY_DEBUG
  2584. switch (out_cmd->hdr.cmd) {
  2585. case C_TX_LINK_QUALITY_CMD:
  2586. case C_SENSITIVITY:
  2587. D_HC_DUMP(
  2588. "Sending command %s (#%x), seq: 0x%04X, "
  2589. "%d bytes at %d[%d]:%d\n",
  2590. il_get_cmd_string(out_cmd->hdr.cmd),
  2591. out_cmd->hdr.cmd,
  2592. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2593. q->write_ptr, idx, il->cmd_queue);
  2594. break;
  2595. default:
  2596. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2597. "%d bytes at %d[%d]:%d\n",
  2598. il_get_cmd_string(out_cmd->hdr.cmd),
  2599. out_cmd->hdr.cmd,
  2600. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2601. q->write_ptr, idx, il->cmd_queue);
  2602. }
  2603. #endif
  2604. txq->need_update = 1;
  2605. if (il->cfg->ops->lib->txq_update_byte_cnt_tbl)
  2606. /* Set up entry in queue's byte count circular buffer */
  2607. il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
  2608. phys_addr = pci_map_single(il->pci_dev, &out_cmd->hdr,
  2609. fix_size, PCI_DMA_BIDIRECTIONAL);
  2610. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2611. dma_unmap_len_set(out_meta, len, fix_size);
  2612. il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
  2613. phys_addr, fix_size, 1,
  2614. U32_PAD(cmd->len));
  2615. /* Increment and update queue's write idx */
  2616. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2617. il_txq_update_write_ptr(il, txq);
  2618. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2619. return idx;
  2620. }
  2621. /**
  2622. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2623. *
  2624. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2625. * need to be reclaimed. As result, some free space forms. If there is
  2626. * enough free space (> low mark), wake the stack that feeds us.
  2627. */
  2628. static void il_hcmd_queue_reclaim(struct il_priv *il, int txq_id,
  2629. int idx, int cmd_idx)
  2630. {
  2631. struct il_tx_queue *txq = &il->txq[txq_id];
  2632. struct il_queue *q = &txq->q;
  2633. int nfreed = 0;
  2634. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2635. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2636. "is out of range [0-%d] %d %d.\n", txq_id,
  2637. idx, q->n_bd, q->write_ptr, q->read_ptr);
  2638. return;
  2639. }
  2640. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2641. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2642. if (nfreed++ > 0) {
  2643. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2644. q->write_ptr, q->read_ptr);
  2645. queue_work(il->workqueue, &il->restart);
  2646. }
  2647. }
  2648. }
  2649. /**
  2650. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2651. * @rxb: Rx buffer to reclaim
  2652. *
  2653. * If an Rx buffer has an async callback associated with it the callback
  2654. * will be executed. The attached skb (if present) will only be freed
  2655. * if the callback returns 1
  2656. */
  2657. void
  2658. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2659. {
  2660. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2661. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2662. int txq_id = SEQ_TO_QUEUE(sequence);
  2663. int idx = SEQ_TO_IDX(sequence);
  2664. int cmd_idx;
  2665. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2666. struct il_device_cmd *cmd;
  2667. struct il_cmd_meta *meta;
  2668. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2669. unsigned long flags;
  2670. /* If a Tx command is being handled and it isn't in the actual
  2671. * command queue then there a command routing bug has been introduced
  2672. * in the queue management code. */
  2673. if (WARN(txq_id != il->cmd_queue,
  2674. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2675. txq_id, il->cmd_queue, sequence,
  2676. il->txq[il->cmd_queue].q.read_ptr,
  2677. il->txq[il->cmd_queue].q.write_ptr)) {
  2678. il_print_hex_error(il, pkt, 32);
  2679. return;
  2680. }
  2681. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2682. cmd = txq->cmd[cmd_idx];
  2683. meta = &txq->meta[cmd_idx];
  2684. txq->time_stamp = jiffies;
  2685. pci_unmap_single(il->pci_dev,
  2686. dma_unmap_addr(meta, mapping),
  2687. dma_unmap_len(meta, len),
  2688. PCI_DMA_BIDIRECTIONAL);
  2689. /* Input error checking is done when commands are added to queue. */
  2690. if (meta->flags & CMD_WANT_SKB) {
  2691. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2692. rxb->page = NULL;
  2693. } else if (meta->callback)
  2694. meta->callback(il, cmd, pkt);
  2695. spin_lock_irqsave(&il->hcmd_lock, flags);
  2696. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2697. if (!(meta->flags & CMD_ASYNC)) {
  2698. clear_bit(S_HCMD_ACTIVE, &il->status);
  2699. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2700. il_get_cmd_string(cmd->hdr.cmd));
  2701. wake_up(&il->wait_command_queue);
  2702. }
  2703. /* Mark as unmapped */
  2704. meta->flags = 0;
  2705. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2706. }
  2707. EXPORT_SYMBOL(il_tx_cmd_complete);
  2708. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2709. MODULE_VERSION(IWLWIFI_VERSION);
  2710. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2711. MODULE_LICENSE("GPL");
  2712. /*
  2713. * set bt_coex_active to true, uCode will do kill/defer
  2714. * every time the priority line is asserted (BT is sending signals on the
  2715. * priority line in the PCIx).
  2716. * set bt_coex_active to false, uCode will ignore the BT activity and
  2717. * perform the normal operation
  2718. *
  2719. * User might experience transmit issue on some platform due to WiFi/BT
  2720. * co-exist problem. The possible behaviors are:
  2721. * Able to scan and finding all the available AP
  2722. * Not able to associate with any AP
  2723. * On those platforms, WiFi communication can be restored by set
  2724. * "bt_coex_active" module parameter to "false"
  2725. *
  2726. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2727. */
  2728. static bool bt_coex_active = true;
  2729. module_param(bt_coex_active, bool, S_IRUGO);
  2730. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2731. u32 il_debug_level;
  2732. EXPORT_SYMBOL(il_debug_level);
  2733. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2734. EXPORT_SYMBOL(il_bcast_addr);
  2735. /* This function both allocates and initializes hw and il. */
  2736. struct ieee80211_hw *il_alloc_all(struct il_cfg *cfg)
  2737. {
  2738. struct il_priv *il;
  2739. /* mac80211 allocates memory for this device instance, including
  2740. * space for this driver's ilate structure */
  2741. struct ieee80211_hw *hw;
  2742. hw = ieee80211_alloc_hw(sizeof(struct il_priv),
  2743. cfg->ops->ieee80211_ops);
  2744. if (hw == NULL) {
  2745. pr_err("%s: Can not allocate network device\n",
  2746. cfg->name);
  2747. goto out;
  2748. }
  2749. il = hw->priv;
  2750. il->hw = hw;
  2751. out:
  2752. return hw;
  2753. }
  2754. EXPORT_SYMBOL(il_alloc_all);
  2755. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2756. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2757. static void il_init_ht_hw_capab(const struct il_priv *il,
  2758. struct ieee80211_sta_ht_cap *ht_info,
  2759. enum ieee80211_band band)
  2760. {
  2761. u16 max_bit_rate = 0;
  2762. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2763. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2764. ht_info->cap = 0;
  2765. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2766. ht_info->ht_supported = true;
  2767. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2768. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2769. if (il->hw_params.ht40_channel & BIT(band)) {
  2770. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2771. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2772. ht_info->mcs.rx_mask[4] = 0x01;
  2773. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2774. }
  2775. if (il->cfg->mod_params->amsdu_size_8K)
  2776. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2777. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2778. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2779. ht_info->mcs.rx_mask[0] = 0xFF;
  2780. if (rx_chains_num >= 2)
  2781. ht_info->mcs.rx_mask[1] = 0xFF;
  2782. if (rx_chains_num >= 3)
  2783. ht_info->mcs.rx_mask[2] = 0xFF;
  2784. /* Highest supported Rx data rate */
  2785. max_bit_rate *= rx_chains_num;
  2786. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2787. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2788. /* Tx MCS capabilities */
  2789. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2790. if (tx_chains_num != rx_chains_num) {
  2791. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2792. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  2793. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2794. }
  2795. }
  2796. /**
  2797. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2798. */
  2799. int il_init_geos(struct il_priv *il)
  2800. {
  2801. struct il_channel_info *ch;
  2802. struct ieee80211_supported_band *sband;
  2803. struct ieee80211_channel *channels;
  2804. struct ieee80211_channel *geo_ch;
  2805. struct ieee80211_rate *rates;
  2806. int i = 0;
  2807. s8 max_tx_power = 0;
  2808. if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  2809. il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  2810. D_INFO("Geography modes already initialized.\n");
  2811. set_bit(S_GEO_CONFIGURED, &il->status);
  2812. return 0;
  2813. }
  2814. channels = kzalloc(sizeof(struct ieee80211_channel) *
  2815. il->channel_count, GFP_KERNEL);
  2816. if (!channels)
  2817. return -ENOMEM;
  2818. rates = kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
  2819. GFP_KERNEL);
  2820. if (!rates) {
  2821. kfree(channels);
  2822. return -ENOMEM;
  2823. }
  2824. /* 5.2GHz channels start after the 2.4GHz channels */
  2825. sband = &il->bands[IEEE80211_BAND_5GHZ];
  2826. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2827. /* just OFDM */
  2828. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2829. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2830. if (il->cfg->sku & IL_SKU_N)
  2831. il_init_ht_hw_capab(il, &sband->ht_cap,
  2832. IEEE80211_BAND_5GHZ);
  2833. sband = &il->bands[IEEE80211_BAND_2GHZ];
  2834. sband->channels = channels;
  2835. /* OFDM & CCK */
  2836. sband->bitrates = rates;
  2837. sband->n_bitrates = RATE_COUNT_LEGACY;
  2838. if (il->cfg->sku & IL_SKU_N)
  2839. il_init_ht_hw_capab(il, &sband->ht_cap,
  2840. IEEE80211_BAND_2GHZ);
  2841. il->ieee_channels = channels;
  2842. il->ieee_rates = rates;
  2843. for (i = 0; i < il->channel_count; i++) {
  2844. ch = &il->channel_info[i];
  2845. if (!il_is_channel_valid(ch))
  2846. continue;
  2847. sband = &il->bands[ch->band];
  2848. geo_ch = &sband->channels[sband->n_channels++];
  2849. geo_ch->center_freq =
  2850. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2851. geo_ch->max_power = ch->max_power_avg;
  2852. geo_ch->max_antenna_gain = 0xff;
  2853. geo_ch->hw_value = ch->channel;
  2854. if (il_is_channel_valid(ch)) {
  2855. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2856. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  2857. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2858. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2859. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2860. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2861. geo_ch->flags |= ch->ht40_extension_channel;
  2862. if (ch->max_power_avg > max_tx_power)
  2863. max_tx_power = ch->max_power_avg;
  2864. } else {
  2865. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2866. }
  2867. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  2868. ch->channel, geo_ch->center_freq,
  2869. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2870. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  2871. "restricted" : "valid",
  2872. geo_ch->flags);
  2873. }
  2874. il->tx_power_device_lmt = max_tx_power;
  2875. il->tx_power_user_lmt = max_tx_power;
  2876. il->tx_power_next = max_tx_power;
  2877. if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
  2878. (il->cfg->sku & IL_SKU_A)) {
  2879. IL_INFO("Incorrectly detected BG card as ABG. "
  2880. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2881. il->pci_dev->device,
  2882. il->pci_dev->subsystem_device);
  2883. il->cfg->sku &= ~IL_SKU_A;
  2884. }
  2885. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2886. il->bands[IEEE80211_BAND_2GHZ].n_channels,
  2887. il->bands[IEEE80211_BAND_5GHZ].n_channels);
  2888. set_bit(S_GEO_CONFIGURED, &il->status);
  2889. return 0;
  2890. }
  2891. EXPORT_SYMBOL(il_init_geos);
  2892. /*
  2893. * il_free_geos - undo allocations in il_init_geos
  2894. */
  2895. void il_free_geos(struct il_priv *il)
  2896. {
  2897. kfree(il->ieee_channels);
  2898. kfree(il->ieee_rates);
  2899. clear_bit(S_GEO_CONFIGURED, &il->status);
  2900. }
  2901. EXPORT_SYMBOL(il_free_geos);
  2902. static bool il_is_channel_extension(struct il_priv *il,
  2903. enum ieee80211_band band,
  2904. u16 channel, u8 extension_chan_offset)
  2905. {
  2906. const struct il_channel_info *ch_info;
  2907. ch_info = il_get_channel_info(il, band, channel);
  2908. if (!il_is_channel_valid(ch_info))
  2909. return false;
  2910. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  2911. return !(ch_info->ht40_extension_channel &
  2912. IEEE80211_CHAN_NO_HT40PLUS);
  2913. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  2914. return !(ch_info->ht40_extension_channel &
  2915. IEEE80211_CHAN_NO_HT40MINUS);
  2916. return false;
  2917. }
  2918. bool il_is_ht40_tx_allowed(struct il_priv *il,
  2919. struct il_rxon_context *ctx,
  2920. struct ieee80211_sta_ht_cap *ht_cap)
  2921. {
  2922. if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
  2923. return false;
  2924. /*
  2925. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  2926. * the bit will not set if it is pure 40MHz case
  2927. */
  2928. if (ht_cap && !ht_cap->ht_supported)
  2929. return false;
  2930. #ifdef CONFIG_IWLEGACY_DEBUGFS
  2931. if (il->disable_ht40)
  2932. return false;
  2933. #endif
  2934. return il_is_channel_extension(il, il->band,
  2935. le16_to_cpu(ctx->staging.channel),
  2936. ctx->ht.extension_chan_offset);
  2937. }
  2938. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  2939. static u16 il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  2940. {
  2941. u16 new_val;
  2942. u16 beacon_factor;
  2943. /*
  2944. * If mac80211 hasn't given us a beacon interval, program
  2945. * the default into the device.
  2946. */
  2947. if (!beacon_val)
  2948. return DEFAULT_BEACON_INTERVAL;
  2949. /*
  2950. * If the beacon interval we obtained from the peer
  2951. * is too large, we'll have to wake up more often
  2952. * (and in IBSS case, we'll beacon too much)
  2953. *
  2954. * For example, if max_beacon_val is 4096, and the
  2955. * requested beacon interval is 7000, we'll have to
  2956. * use 3500 to be able to wake up on the beacons.
  2957. *
  2958. * This could badly influence beacon detection stats.
  2959. */
  2960. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  2961. new_val = beacon_val / beacon_factor;
  2962. if (!new_val)
  2963. new_val = max_beacon_val;
  2964. return new_val;
  2965. }
  2966. int
  2967. il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx)
  2968. {
  2969. u64 tsf;
  2970. s32 interval_tm, rem;
  2971. struct ieee80211_conf *conf = NULL;
  2972. u16 beacon_int;
  2973. struct ieee80211_vif *vif = ctx->vif;
  2974. conf = &il->hw->conf;
  2975. lockdep_assert_held(&il->mutex);
  2976. memset(&ctx->timing, 0, sizeof(struct il_rxon_time_cmd));
  2977. ctx->timing.timestamp = cpu_to_le64(il->timestamp);
  2978. ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  2979. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  2980. /*
  2981. * TODO: For IBSS we need to get atim_win from mac80211,
  2982. * for now just always use 0
  2983. */
  2984. ctx->timing.atim_win = 0;
  2985. beacon_int = il_adjust_beacon_interval(beacon_int,
  2986. il->hw_params.max_beacon_itrvl * TIME_UNIT);
  2987. ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
  2988. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  2989. interval_tm = beacon_int * TIME_UNIT;
  2990. rem = do_div(tsf, interval_tm);
  2991. ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  2992. ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1;
  2993. D_ASSOC(
  2994. "beacon interval %d beacon timer %d beacon tim %d\n",
  2995. le16_to_cpu(ctx->timing.beacon_interval),
  2996. le32_to_cpu(ctx->timing.beacon_init_val),
  2997. le16_to_cpu(ctx->timing.atim_win));
  2998. return il_send_cmd_pdu(il, ctx->rxon_timing_cmd,
  2999. sizeof(ctx->timing), &ctx->timing);
  3000. }
  3001. EXPORT_SYMBOL(il_send_rxon_timing);
  3002. void
  3003. il_set_rxon_hwcrypto(struct il_priv *il,
  3004. struct il_rxon_context *ctx,
  3005. int hw_decrypt)
  3006. {
  3007. struct il_rxon_cmd *rxon = &ctx->staging;
  3008. if (hw_decrypt)
  3009. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3010. else
  3011. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3012. }
  3013. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3014. /* validate RXON structure is valid */
  3015. int
  3016. il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx)
  3017. {
  3018. struct il_rxon_cmd *rxon = &ctx->staging;
  3019. bool error = false;
  3020. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3021. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3022. IL_WARN("check 2.4G: wrong narrow\n");
  3023. error = true;
  3024. }
  3025. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3026. IL_WARN("check 2.4G: wrong radar\n");
  3027. error = true;
  3028. }
  3029. } else {
  3030. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3031. IL_WARN("check 5.2G: not short slot!\n");
  3032. error = true;
  3033. }
  3034. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3035. IL_WARN("check 5.2G: CCK!\n");
  3036. error = true;
  3037. }
  3038. }
  3039. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3040. IL_WARN("mac/bssid mcast!\n");
  3041. error = true;
  3042. }
  3043. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3044. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3045. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3046. IL_WARN("neither 1 nor 6 are basic\n");
  3047. error = true;
  3048. }
  3049. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3050. IL_WARN("aid > 2007\n");
  3051. error = true;
  3052. }
  3053. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  3054. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3055. IL_WARN("CCK and short slot\n");
  3056. error = true;
  3057. }
  3058. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  3059. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3060. IL_WARN("CCK and auto detect");
  3061. error = true;
  3062. }
  3063. if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  3064. RXON_FLG_TGG_PROTECT_MSK)) ==
  3065. RXON_FLG_TGG_PROTECT_MSK) {
  3066. IL_WARN("TGg but no auto-detect\n");
  3067. error = true;
  3068. }
  3069. if (error)
  3070. IL_WARN("Tuning to channel %d\n",
  3071. le16_to_cpu(rxon->channel));
  3072. if (error) {
  3073. IL_ERR("Invalid RXON\n");
  3074. return -EINVAL;
  3075. }
  3076. return 0;
  3077. }
  3078. EXPORT_SYMBOL(il_check_rxon_cmd);
  3079. /**
  3080. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3081. * @il: staging_rxon is compared to active_rxon
  3082. *
  3083. * If the RXON structure is changing enough to require a new tune,
  3084. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3085. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3086. */
  3087. int il_full_rxon_required(struct il_priv *il,
  3088. struct il_rxon_context *ctx)
  3089. {
  3090. const struct il_rxon_cmd *staging = &ctx->staging;
  3091. const struct il_rxon_cmd *active = &ctx->active;
  3092. #define CHK(cond) \
  3093. if ((cond)) { \
  3094. D_INFO("need full RXON - " #cond "\n"); \
  3095. return 1; \
  3096. }
  3097. #define CHK_NEQ(c1, c2) \
  3098. if ((c1) != (c2)) { \
  3099. D_INFO("need full RXON - " \
  3100. #c1 " != " #c2 " - %d != %d\n", \
  3101. (c1), (c2)); \
  3102. return 1; \
  3103. }
  3104. /* These items are only settable from the full RXON command */
  3105. CHK(!il_is_associated_ctx(ctx));
  3106. CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
  3107. CHK(compare_ether_addr(staging->node_addr, active->node_addr));
  3108. CHK(compare_ether_addr(staging->wlap_bssid_addr,
  3109. active->wlap_bssid_addr));
  3110. CHK_NEQ(staging->dev_type, active->dev_type);
  3111. CHK_NEQ(staging->channel, active->channel);
  3112. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3113. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3114. active->ofdm_ht_single_stream_basic_rates);
  3115. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3116. active->ofdm_ht_dual_stream_basic_rates);
  3117. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3118. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3119. * be updated with the RXON_ASSOC command -- however only some
  3120. * flag transitions are allowed using RXON_ASSOC */
  3121. /* Check if we are not switching bands */
  3122. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3123. active->flags & RXON_FLG_BAND_24G_MSK);
  3124. /* Check if we are switching association toggle */
  3125. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3126. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3127. #undef CHK
  3128. #undef CHK_NEQ
  3129. return 0;
  3130. }
  3131. EXPORT_SYMBOL(il_full_rxon_required);
  3132. u8 il_get_lowest_plcp(struct il_priv *il,
  3133. struct il_rxon_context *ctx)
  3134. {
  3135. /*
  3136. * Assign the lowest rate -- should really get this from
  3137. * the beacon skb from mac80211.
  3138. */
  3139. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK)
  3140. return RATE_1M_PLCP;
  3141. else
  3142. return RATE_6M_PLCP;
  3143. }
  3144. EXPORT_SYMBOL(il_get_lowest_plcp);
  3145. static void _il_set_rxon_ht(struct il_priv *il,
  3146. struct il_ht_config *ht_conf,
  3147. struct il_rxon_context *ctx)
  3148. {
  3149. struct il_rxon_cmd *rxon = &ctx->staging;
  3150. if (!ctx->ht.enabled) {
  3151. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  3152. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  3153. RXON_FLG_HT40_PROT_MSK |
  3154. RXON_FLG_HT_PROT_MSK);
  3155. return;
  3156. }
  3157. rxon->flags |= cpu_to_le32(ctx->ht.protection <<
  3158. RXON_FLG_HT_OPERATING_MODE_POS);
  3159. /* Set up channel bandwidth:
  3160. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3161. /* clear the HT channel mode before set the mode */
  3162. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  3163. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3164. if (il_is_ht40_tx_allowed(il, ctx, NULL)) {
  3165. /* pure ht40 */
  3166. if (ctx->ht.protection ==
  3167. IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3168. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3169. /* Note: control channel is opposite of extension channel */
  3170. switch (ctx->ht.extension_chan_offset) {
  3171. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3172. rxon->flags &=
  3173. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3174. break;
  3175. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3176. rxon->flags |=
  3177. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3178. break;
  3179. }
  3180. } else {
  3181. /* Note: control channel is opposite of extension channel */
  3182. switch (ctx->ht.extension_chan_offset) {
  3183. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3184. rxon->flags &=
  3185. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3186. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3187. break;
  3188. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3189. rxon->flags |=
  3190. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3191. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3192. break;
  3193. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3194. default:
  3195. /* channel location only valid if in Mixed mode */
  3196. IL_ERR(
  3197. "invalid extension channel offset\n");
  3198. break;
  3199. }
  3200. }
  3201. } else {
  3202. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3203. }
  3204. if (il->cfg->ops->hcmd->set_rxon_chain)
  3205. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  3206. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3207. "extension channel offset 0x%x\n",
  3208. le32_to_cpu(rxon->flags), ctx->ht.protection,
  3209. ctx->ht.extension_chan_offset);
  3210. }
  3211. void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3212. {
  3213. _il_set_rxon_ht(il, ht_conf, &il->ctx);
  3214. }
  3215. EXPORT_SYMBOL(il_set_rxon_ht);
  3216. /* Return valid, unused, channel for a passive scan to reset the RF */
  3217. u8 il_get_single_channel_number(struct il_priv *il,
  3218. enum ieee80211_band band)
  3219. {
  3220. const struct il_channel_info *ch_info;
  3221. int i;
  3222. u8 channel = 0;
  3223. u8 min, max;
  3224. if (band == IEEE80211_BAND_5GHZ) {
  3225. min = 14;
  3226. max = il->channel_count;
  3227. } else {
  3228. min = 0;
  3229. max = 14;
  3230. }
  3231. for (i = min; i < max; i++) {
  3232. channel = il->channel_info[i].channel;
  3233. if (channel == le16_to_cpu(il->ctx.staging.channel))
  3234. continue;
  3235. ch_info = il_get_channel_info(il, band, channel);
  3236. if (il_is_channel_valid(ch_info))
  3237. break;
  3238. }
  3239. return channel;
  3240. }
  3241. EXPORT_SYMBOL(il_get_single_channel_number);
  3242. /**
  3243. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3244. * @ch: requested channel as a pointer to struct ieee80211_channel
  3245. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3246. * in the staging RXON flag structure based on the ch->band
  3247. */
  3248. int
  3249. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
  3250. struct il_rxon_context *ctx)
  3251. {
  3252. enum ieee80211_band band = ch->band;
  3253. u16 channel = ch->hw_value;
  3254. if (le16_to_cpu(ctx->staging.channel) == channel && il->band == band)
  3255. return 0;
  3256. ctx->staging.channel = cpu_to_le16(channel);
  3257. if (band == IEEE80211_BAND_5GHZ)
  3258. ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3259. else
  3260. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3261. il->band = band;
  3262. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3263. return 0;
  3264. }
  3265. EXPORT_SYMBOL(il_set_rxon_channel);
  3266. void il_set_flags_for_band(struct il_priv *il,
  3267. struct il_rxon_context *ctx,
  3268. enum ieee80211_band band,
  3269. struct ieee80211_vif *vif)
  3270. {
  3271. if (band == IEEE80211_BAND_5GHZ) {
  3272. ctx->staging.flags &=
  3273. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  3274. | RXON_FLG_CCK_MSK);
  3275. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3276. } else {
  3277. /* Copied from il_post_associate() */
  3278. if (vif && vif->bss_conf.use_short_slot)
  3279. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3280. else
  3281. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3282. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3283. ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3284. ctx->staging.flags &= ~RXON_FLG_CCK_MSK;
  3285. }
  3286. }
  3287. EXPORT_SYMBOL(il_set_flags_for_band);
  3288. /*
  3289. * initialize rxon structure with default values from eeprom
  3290. */
  3291. void il_connection_init_rx_config(struct il_priv *il,
  3292. struct il_rxon_context *ctx)
  3293. {
  3294. const struct il_channel_info *ch_info;
  3295. memset(&ctx->staging, 0, sizeof(ctx->staging));
  3296. if (!ctx->vif) {
  3297. ctx->staging.dev_type = ctx->unused_devtype;
  3298. } else
  3299. switch (ctx->vif->type) {
  3300. case NL80211_IFTYPE_STATION:
  3301. ctx->staging.dev_type = ctx->station_devtype;
  3302. ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3303. break;
  3304. case NL80211_IFTYPE_ADHOC:
  3305. ctx->staging.dev_type = ctx->ibss_devtype;
  3306. ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3307. ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  3308. RXON_FILTER_ACCEPT_GRP_MSK;
  3309. break;
  3310. default:
  3311. IL_ERR("Unsupported interface type %d\n",
  3312. ctx->vif->type);
  3313. break;
  3314. }
  3315. #if 0
  3316. /* TODO: Figure out when short_preamble would be set and cache from
  3317. * that */
  3318. if (!hw_to_local(il->hw)->short_preamble)
  3319. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3320. else
  3321. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3322. #endif
  3323. ch_info = il_get_channel_info(il, il->band,
  3324. le16_to_cpu(ctx->active.channel));
  3325. if (!ch_info)
  3326. ch_info = &il->channel_info[0];
  3327. ctx->staging.channel = cpu_to_le16(ch_info->channel);
  3328. il->band = ch_info->band;
  3329. il_set_flags_for_band(il, ctx, il->band, ctx->vif);
  3330. ctx->staging.ofdm_basic_rates =
  3331. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3332. ctx->staging.cck_basic_rates =
  3333. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3334. /* clear both MIX and PURE40 mode flag */
  3335. ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  3336. RXON_FLG_CHANNEL_MODE_PURE_40);
  3337. if (ctx->vif)
  3338. memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN);
  3339. ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3340. ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3341. }
  3342. EXPORT_SYMBOL(il_connection_init_rx_config);
  3343. void il_set_rate(struct il_priv *il)
  3344. {
  3345. const struct ieee80211_supported_band *hw = NULL;
  3346. struct ieee80211_rate *rate;
  3347. int i;
  3348. hw = il_get_hw_mode(il, il->band);
  3349. if (!hw) {
  3350. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3351. return;
  3352. }
  3353. il->active_rate = 0;
  3354. for (i = 0; i < hw->n_bitrates; i++) {
  3355. rate = &(hw->bitrates[i]);
  3356. if (rate->hw_value < RATE_COUNT_LEGACY)
  3357. il->active_rate |= (1 << rate->hw_value);
  3358. }
  3359. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3360. il->ctx.staging.cck_basic_rates =
  3361. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3362. il->ctx.staging.ofdm_basic_rates =
  3363. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3364. }
  3365. EXPORT_SYMBOL(il_set_rate);
  3366. void il_chswitch_done(struct il_priv *il, bool is_success)
  3367. {
  3368. struct il_rxon_context *ctx = &il->ctx;
  3369. if (test_bit(S_EXIT_PENDING, &il->status))
  3370. return;
  3371. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3372. ieee80211_chswitch_done(ctx->vif, is_success);
  3373. }
  3374. EXPORT_SYMBOL(il_chswitch_done);
  3375. void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3376. {
  3377. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3378. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3379. struct il_rxon_context *ctx = &il->ctx;
  3380. struct il_rxon_cmd *rxon = (void *)&ctx->active;
  3381. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3382. return;
  3383. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3384. rxon->channel = csa->channel;
  3385. ctx->staging.channel = csa->channel;
  3386. D_11H("CSA notif: channel %d\n",
  3387. le16_to_cpu(csa->channel));
  3388. il_chswitch_done(il, true);
  3389. } else {
  3390. IL_ERR("CSA notif (fail) : channel %d\n",
  3391. le16_to_cpu(csa->channel));
  3392. il_chswitch_done(il, false);
  3393. }
  3394. }
  3395. EXPORT_SYMBOL(il_hdl_csa);
  3396. #ifdef CONFIG_IWLEGACY_DEBUG
  3397. void il_print_rx_config_cmd(struct il_priv *il,
  3398. struct il_rxon_context *ctx)
  3399. {
  3400. struct il_rxon_cmd *rxon = &ctx->staging;
  3401. D_RADIO("RX CONFIG:\n");
  3402. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3403. D_RADIO("u16 channel: 0x%x\n",
  3404. le16_to_cpu(rxon->channel));
  3405. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3406. D_RADIO("u32 filter_flags: 0x%08x\n",
  3407. le32_to_cpu(rxon->filter_flags));
  3408. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3409. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3410. rxon->ofdm_basic_rates);
  3411. D_RADIO("u8 cck_basic_rates: 0x%02x\n",
  3412. rxon->cck_basic_rates);
  3413. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3414. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3415. D_RADIO("u16 assoc_id: 0x%x\n",
  3416. le16_to_cpu(rxon->assoc_id));
  3417. }
  3418. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3419. #endif
  3420. /**
  3421. * il_irq_handle_error - called for HW or SW error interrupt from card
  3422. */
  3423. void il_irq_handle_error(struct il_priv *il)
  3424. {
  3425. /* Set the FW error flag -- cleared on il_down */
  3426. set_bit(S_FW_ERROR, &il->status);
  3427. /* Cancel currently queued command. */
  3428. clear_bit(S_HCMD_ACTIVE, &il->status);
  3429. IL_ERR("Loaded firmware version: %s\n",
  3430. il->hw->wiphy->fw_version);
  3431. il->cfg->ops->lib->dump_nic_error_log(il);
  3432. if (il->cfg->ops->lib->dump_fh)
  3433. il->cfg->ops->lib->dump_fh(il, NULL, false);
  3434. #ifdef CONFIG_IWLEGACY_DEBUG
  3435. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3436. il_print_rx_config_cmd(il,
  3437. &il->ctx);
  3438. #endif
  3439. wake_up(&il->wait_command_queue);
  3440. /* Keep the restart process from trying to send host
  3441. * commands by clearing the INIT status bit */
  3442. clear_bit(S_READY, &il->status);
  3443. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3444. IL_DBG(IL_DL_FW_ERRORS,
  3445. "Restarting adapter due to uCode error.\n");
  3446. if (il->cfg->mod_params->restart_fw)
  3447. queue_work(il->workqueue, &il->restart);
  3448. }
  3449. }
  3450. EXPORT_SYMBOL(il_irq_handle_error);
  3451. static int il_apm_stop_master(struct il_priv *il)
  3452. {
  3453. int ret = 0;
  3454. /* stop device's busmaster DMA activity */
  3455. il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3456. ret = _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3457. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3458. if (ret)
  3459. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3460. D_INFO("stop master\n");
  3461. return ret;
  3462. }
  3463. void il_apm_stop(struct il_priv *il)
  3464. {
  3465. D_INFO("Stop card, put in low power state\n");
  3466. /* Stop device's DMA activity */
  3467. il_apm_stop_master(il);
  3468. /* Reset the entire device */
  3469. il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3470. udelay(10);
  3471. /*
  3472. * Clear "initialization complete" bit to move adapter from
  3473. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3474. */
  3475. il_clear_bit(il, CSR_GP_CNTRL,
  3476. CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3477. }
  3478. EXPORT_SYMBOL(il_apm_stop);
  3479. /*
  3480. * Start up NIC's basic functionality after it has been reset
  3481. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3482. * NOTE: This does not load uCode nor start the embedded processor
  3483. */
  3484. int il_apm_init(struct il_priv *il)
  3485. {
  3486. int ret = 0;
  3487. u16 lctl;
  3488. D_INFO("Init card's basic functions\n");
  3489. /*
  3490. * Use "set_bit" below rather than "write", to preserve any hardware
  3491. * bits already set by default after reset.
  3492. */
  3493. /* Disable L0S exit timer (platform NMI Work/Around) */
  3494. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3495. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3496. /*
  3497. * Disable L0s without affecting L1;
  3498. * don't wait for ICH L0s (ICH bug W/A)
  3499. */
  3500. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3501. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3502. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3503. il_set_bit(il, CSR_DBG_HPET_MEM_REG,
  3504. CSR_DBG_HPET_MEM_REG_VAL);
  3505. /*
  3506. * Enable HAP INTA (interrupt from management bus) to
  3507. * wake device's PCI Express link L1a -> L0s
  3508. * NOTE: This is no-op for 3945 (non-existent bit)
  3509. */
  3510. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3511. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3512. /*
  3513. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3514. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3515. * If so (likely), disable L0S, so device moves directly L0->L1;
  3516. * costs negligible amount of power savings.
  3517. * If not (unlikely), enable L0S, so there is at least some
  3518. * power savings, even without L1.
  3519. */
  3520. if (il->cfg->base_params->set_l0s) {
  3521. lctl = il_pcie_link_ctl(il);
  3522. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  3523. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  3524. /* L1-ASPM enabled; disable(!) L0S */
  3525. il_set_bit(il, CSR_GIO_REG,
  3526. CSR_GIO_REG_VAL_L0S_ENABLED);
  3527. D_POWER("L1 Enabled; Disabling L0S\n");
  3528. } else {
  3529. /* L1-ASPM disabled; enable(!) L0S */
  3530. il_clear_bit(il, CSR_GIO_REG,
  3531. CSR_GIO_REG_VAL_L0S_ENABLED);
  3532. D_POWER("L1 Disabled; Enabling L0S\n");
  3533. }
  3534. }
  3535. /* Configure analog phase-lock-loop before activating to D0A */
  3536. if (il->cfg->base_params->pll_cfg_val)
  3537. il_set_bit(il, CSR_ANA_PLL_CFG,
  3538. il->cfg->base_params->pll_cfg_val);
  3539. /*
  3540. * Set "initialization complete" bit to move adapter from
  3541. * D0U* --> D0A* (powered-up active) state.
  3542. */
  3543. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3544. /*
  3545. * Wait for clock stabilization; once stabilized, access to
  3546. * device-internal resources is supported, e.g. il_wr_prph()
  3547. * and accesses to uCode SRAM.
  3548. */
  3549. ret = _il_poll_bit(il, CSR_GP_CNTRL,
  3550. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3551. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3552. if (ret < 0) {
  3553. D_INFO("Failed to init the card\n");
  3554. goto out;
  3555. }
  3556. /*
  3557. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3558. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3559. *
  3560. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3561. * do not disable clocks. This preserves any hardware bits already
  3562. * set by default in "CLK_CTRL_REG" after reset.
  3563. */
  3564. if (il->cfg->base_params->use_bsm)
  3565. il_wr_prph(il, APMG_CLK_EN_REG,
  3566. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3567. else
  3568. il_wr_prph(il, APMG_CLK_EN_REG,
  3569. APMG_CLK_VAL_DMA_CLK_RQT);
  3570. udelay(20);
  3571. /* Disable L1-Active */
  3572. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3573. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3574. out:
  3575. return ret;
  3576. }
  3577. EXPORT_SYMBOL(il_apm_init);
  3578. int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3579. {
  3580. int ret;
  3581. s8 prev_tx_power;
  3582. bool defer;
  3583. struct il_rxon_context *ctx = &il->ctx;
  3584. lockdep_assert_held(&il->mutex);
  3585. if (il->tx_power_user_lmt == tx_power && !force)
  3586. return 0;
  3587. if (!il->cfg->ops->lib->send_tx_power)
  3588. return -EOPNOTSUPP;
  3589. /* 0 dBm mean 1 milliwatt */
  3590. if (tx_power < 0) {
  3591. IL_WARN(
  3592. "Requested user TXPOWER %d below 1 mW.\n",
  3593. tx_power);
  3594. return -EINVAL;
  3595. }
  3596. if (tx_power > il->tx_power_device_lmt) {
  3597. IL_WARN(
  3598. "Requested user TXPOWER %d above upper limit %d.\n",
  3599. tx_power, il->tx_power_device_lmt);
  3600. return -EINVAL;
  3601. }
  3602. if (!il_is_ready_rf(il))
  3603. return -EIO;
  3604. /* scan complete and commit_rxon use tx_power_next value,
  3605. * it always need to be updated for newest request */
  3606. il->tx_power_next = tx_power;
  3607. /* do not set tx power when scanning or channel changing */
  3608. defer = test_bit(S_SCANNING, &il->status) ||
  3609. memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging));
  3610. if (defer && !force) {
  3611. D_INFO("Deferring tx power set\n");
  3612. return 0;
  3613. }
  3614. prev_tx_power = il->tx_power_user_lmt;
  3615. il->tx_power_user_lmt = tx_power;
  3616. ret = il->cfg->ops->lib->send_tx_power(il);
  3617. /* if fail to set tx_power, restore the orig. tx power */
  3618. if (ret) {
  3619. il->tx_power_user_lmt = prev_tx_power;
  3620. il->tx_power_next = prev_tx_power;
  3621. }
  3622. return ret;
  3623. }
  3624. EXPORT_SYMBOL(il_set_tx_power);
  3625. void il_send_bt_config(struct il_priv *il)
  3626. {
  3627. struct il_bt_cmd bt_cmd = {
  3628. .lead_time = BT_LEAD_TIME_DEF,
  3629. .max_kill = BT_MAX_KILL_DEF,
  3630. .kill_ack_mask = 0,
  3631. .kill_cts_mask = 0,
  3632. };
  3633. if (!bt_coex_active)
  3634. bt_cmd.flags = BT_COEX_DISABLE;
  3635. else
  3636. bt_cmd.flags = BT_COEX_ENABLE;
  3637. D_INFO("BT coex %s\n",
  3638. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3639. if (il_send_cmd_pdu(il, C_BT_CONFIG,
  3640. sizeof(struct il_bt_cmd), &bt_cmd))
  3641. IL_ERR("failed to send BT Coex Config\n");
  3642. }
  3643. EXPORT_SYMBOL(il_send_bt_config);
  3644. int il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3645. {
  3646. struct il_stats_cmd stats_cmd = {
  3647. .configuration_flags =
  3648. clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3649. };
  3650. if (flags & CMD_ASYNC)
  3651. return il_send_cmd_pdu_async(il, C_STATS,
  3652. sizeof(struct il_stats_cmd),
  3653. &stats_cmd, NULL);
  3654. else
  3655. return il_send_cmd_pdu(il, C_STATS,
  3656. sizeof(struct il_stats_cmd),
  3657. &stats_cmd);
  3658. }
  3659. EXPORT_SYMBOL(il_send_stats_request);
  3660. void il_hdl_pm_sleep(struct il_priv *il,
  3661. struct il_rx_buf *rxb)
  3662. {
  3663. #ifdef CONFIG_IWLEGACY_DEBUG
  3664. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3665. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3666. D_RX("sleep mode: %d, src: %d\n",
  3667. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3668. #endif
  3669. }
  3670. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3671. void il_hdl_pm_debug_stats(struct il_priv *il,
  3672. struct il_rx_buf *rxb)
  3673. {
  3674. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3675. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3676. D_RADIO("Dumping %d bytes of unhandled "
  3677. "notification for %s:\n", len,
  3678. il_get_cmd_string(pkt->hdr.cmd));
  3679. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3680. }
  3681. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3682. void il_hdl_error(struct il_priv *il,
  3683. struct il_rx_buf *rxb)
  3684. {
  3685. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3686. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3687. "seq 0x%04X ser 0x%08X\n",
  3688. le32_to_cpu(pkt->u.err_resp.error_type),
  3689. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3690. pkt->u.err_resp.cmd_id,
  3691. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3692. le32_to_cpu(pkt->u.err_resp.error_info));
  3693. }
  3694. EXPORT_SYMBOL(il_hdl_error);
  3695. void il_clear_isr_stats(struct il_priv *il)
  3696. {
  3697. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3698. }
  3699. int il_mac_conf_tx(struct ieee80211_hw *hw,
  3700. struct ieee80211_vif *vif, u16 queue,
  3701. const struct ieee80211_tx_queue_params *params)
  3702. {
  3703. struct il_priv *il = hw->priv;
  3704. unsigned long flags;
  3705. int q;
  3706. D_MAC80211("enter\n");
  3707. if (!il_is_ready_rf(il)) {
  3708. D_MAC80211("leave - RF not ready\n");
  3709. return -EIO;
  3710. }
  3711. if (queue >= AC_NUM) {
  3712. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3713. return 0;
  3714. }
  3715. q = AC_NUM - 1 - queue;
  3716. spin_lock_irqsave(&il->lock, flags);
  3717. il->ctx.qos_data.def_qos_parm.ac[q].cw_min =
  3718. cpu_to_le16(params->cw_min);
  3719. il->ctx.qos_data.def_qos_parm.ac[q].cw_max =
  3720. cpu_to_le16(params->cw_max);
  3721. il->ctx.qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3722. il->ctx.qos_data.def_qos_parm.ac[q].edca_txop =
  3723. cpu_to_le16((params->txop * 32));
  3724. il->ctx.qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3725. spin_unlock_irqrestore(&il->lock, flags);
  3726. D_MAC80211("leave\n");
  3727. return 0;
  3728. }
  3729. EXPORT_SYMBOL(il_mac_conf_tx);
  3730. int il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3731. {
  3732. struct il_priv *il = hw->priv;
  3733. return il->ibss_manager == IL_IBSS_MANAGER;
  3734. }
  3735. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3736. static int
  3737. il_set_mode(struct il_priv *il, struct il_rxon_context *ctx)
  3738. {
  3739. il_connection_init_rx_config(il, ctx);
  3740. if (il->cfg->ops->hcmd->set_rxon_chain)
  3741. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  3742. return il_commit_rxon(il, ctx);
  3743. }
  3744. static int il_setup_interface(struct il_priv *il,
  3745. struct il_rxon_context *ctx)
  3746. {
  3747. struct ieee80211_vif *vif = ctx->vif;
  3748. int err;
  3749. lockdep_assert_held(&il->mutex);
  3750. /*
  3751. * This variable will be correct only when there's just
  3752. * a single context, but all code using it is for hardware
  3753. * that supports only one context.
  3754. */
  3755. il->iw_mode = vif->type;
  3756. ctx->is_active = true;
  3757. err = il_set_mode(il, ctx);
  3758. if (err) {
  3759. if (!ctx->always_active)
  3760. ctx->is_active = false;
  3761. return err;
  3762. }
  3763. return 0;
  3764. }
  3765. int
  3766. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3767. {
  3768. struct il_priv *il = hw->priv;
  3769. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  3770. int err;
  3771. u32 modes;
  3772. D_MAC80211("enter: type %d, addr %pM\n",
  3773. vif->type, vif->addr);
  3774. mutex_lock(&il->mutex);
  3775. if (!il_is_ready_rf(il)) {
  3776. IL_WARN("Try to add interface when device not ready\n");
  3777. err = -EINVAL;
  3778. goto out;
  3779. }
  3780. /* check if busy context is exclusive */
  3781. if (il->ctx.vif &&
  3782. (il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type))) {
  3783. err = -EINVAL;
  3784. goto out;
  3785. }
  3786. modes = il->ctx.interface_modes | il->ctx.exclusive_interface_modes;
  3787. if (!(modes & BIT(vif->type))) {
  3788. err = -EOPNOTSUPP;
  3789. goto out;
  3790. }
  3791. vif_priv->ctx = &il->ctx;
  3792. il->ctx.vif = vif;
  3793. err = il_setup_interface(il, &il->ctx);
  3794. if (err) {
  3795. il->ctx.vif = NULL;
  3796. il->iw_mode = NL80211_IFTYPE_STATION;
  3797. }
  3798. out:
  3799. mutex_unlock(&il->mutex);
  3800. D_MAC80211("leave\n");
  3801. return err;
  3802. }
  3803. EXPORT_SYMBOL(il_mac_add_interface);
  3804. static void il_teardown_interface(struct il_priv *il,
  3805. struct ieee80211_vif *vif,
  3806. bool mode_change)
  3807. {
  3808. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  3809. lockdep_assert_held(&il->mutex);
  3810. if (il->scan_vif == vif) {
  3811. il_scan_cancel_timeout(il, 200);
  3812. il_force_scan_end(il);
  3813. }
  3814. if (!mode_change) {
  3815. il_set_mode(il, ctx);
  3816. if (!ctx->always_active)
  3817. ctx->is_active = false;
  3818. }
  3819. }
  3820. void il_mac_remove_interface(struct ieee80211_hw *hw,
  3821. struct ieee80211_vif *vif)
  3822. {
  3823. struct il_priv *il = hw->priv;
  3824. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  3825. D_MAC80211("enter\n");
  3826. mutex_lock(&il->mutex);
  3827. WARN_ON(ctx->vif != vif);
  3828. ctx->vif = NULL;
  3829. il_teardown_interface(il, vif, false);
  3830. memset(il->bssid, 0, ETH_ALEN);
  3831. mutex_unlock(&il->mutex);
  3832. D_MAC80211("leave\n");
  3833. }
  3834. EXPORT_SYMBOL(il_mac_remove_interface);
  3835. int il_alloc_txq_mem(struct il_priv *il)
  3836. {
  3837. if (!il->txq)
  3838. il->txq = kzalloc(
  3839. sizeof(struct il_tx_queue) *
  3840. il->cfg->base_params->num_of_queues,
  3841. GFP_KERNEL);
  3842. if (!il->txq) {
  3843. IL_ERR("Not enough memory for txq\n");
  3844. return -ENOMEM;
  3845. }
  3846. return 0;
  3847. }
  3848. EXPORT_SYMBOL(il_alloc_txq_mem);
  3849. void il_txq_mem(struct il_priv *il)
  3850. {
  3851. kfree(il->txq);
  3852. il->txq = NULL;
  3853. }
  3854. EXPORT_SYMBOL(il_txq_mem);
  3855. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3856. #define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
  3857. void il_reset_traffic_log(struct il_priv *il)
  3858. {
  3859. il->tx_traffic_idx = 0;
  3860. il->rx_traffic_idx = 0;
  3861. if (il->tx_traffic)
  3862. memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
  3863. if (il->rx_traffic)
  3864. memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
  3865. }
  3866. int il_alloc_traffic_mem(struct il_priv *il)
  3867. {
  3868. u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
  3869. if (il_debug_level & IL_DL_TX) {
  3870. if (!il->tx_traffic) {
  3871. il->tx_traffic =
  3872. kzalloc(traffic_size, GFP_KERNEL);
  3873. if (!il->tx_traffic)
  3874. return -ENOMEM;
  3875. }
  3876. }
  3877. if (il_debug_level & IL_DL_RX) {
  3878. if (!il->rx_traffic) {
  3879. il->rx_traffic =
  3880. kzalloc(traffic_size, GFP_KERNEL);
  3881. if (!il->rx_traffic)
  3882. return -ENOMEM;
  3883. }
  3884. }
  3885. il_reset_traffic_log(il);
  3886. return 0;
  3887. }
  3888. EXPORT_SYMBOL(il_alloc_traffic_mem);
  3889. void il_free_traffic_mem(struct il_priv *il)
  3890. {
  3891. kfree(il->tx_traffic);
  3892. il->tx_traffic = NULL;
  3893. kfree(il->rx_traffic);
  3894. il->rx_traffic = NULL;
  3895. }
  3896. EXPORT_SYMBOL(il_free_traffic_mem);
  3897. void il_dbg_log_tx_data_frame(struct il_priv *il,
  3898. u16 length, struct ieee80211_hdr *header)
  3899. {
  3900. __le16 fc;
  3901. u16 len;
  3902. if (likely(!(il_debug_level & IL_DL_TX)))
  3903. return;
  3904. if (!il->tx_traffic)
  3905. return;
  3906. fc = header->frame_control;
  3907. if (ieee80211_is_data(fc)) {
  3908. len = (length > IL_TRAFFIC_ENTRY_SIZE)
  3909. ? IL_TRAFFIC_ENTRY_SIZE : length;
  3910. memcpy((il->tx_traffic +
  3911. (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)),
  3912. header, len);
  3913. il->tx_traffic_idx =
  3914. (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
  3915. }
  3916. }
  3917. EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
  3918. void il_dbg_log_rx_data_frame(struct il_priv *il,
  3919. u16 length, struct ieee80211_hdr *header)
  3920. {
  3921. __le16 fc;
  3922. u16 len;
  3923. if (likely(!(il_debug_level & IL_DL_RX)))
  3924. return;
  3925. if (!il->rx_traffic)
  3926. return;
  3927. fc = header->frame_control;
  3928. if (ieee80211_is_data(fc)) {
  3929. len = (length > IL_TRAFFIC_ENTRY_SIZE)
  3930. ? IL_TRAFFIC_ENTRY_SIZE : length;
  3931. memcpy((il->rx_traffic +
  3932. (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)),
  3933. header, len);
  3934. il->rx_traffic_idx =
  3935. (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
  3936. }
  3937. }
  3938. EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
  3939. const char *il_get_mgmt_string(int cmd)
  3940. {
  3941. switch (cmd) {
  3942. IL_CMD(MANAGEMENT_ASSOC_REQ);
  3943. IL_CMD(MANAGEMENT_ASSOC_RESP);
  3944. IL_CMD(MANAGEMENT_REASSOC_REQ);
  3945. IL_CMD(MANAGEMENT_REASSOC_RESP);
  3946. IL_CMD(MANAGEMENT_PROBE_REQ);
  3947. IL_CMD(MANAGEMENT_PROBE_RESP);
  3948. IL_CMD(MANAGEMENT_BEACON);
  3949. IL_CMD(MANAGEMENT_ATIM);
  3950. IL_CMD(MANAGEMENT_DISASSOC);
  3951. IL_CMD(MANAGEMENT_AUTH);
  3952. IL_CMD(MANAGEMENT_DEAUTH);
  3953. IL_CMD(MANAGEMENT_ACTION);
  3954. default:
  3955. return "UNKNOWN";
  3956. }
  3957. }
  3958. const char *il_get_ctrl_string(int cmd)
  3959. {
  3960. switch (cmd) {
  3961. IL_CMD(CONTROL_BACK_REQ);
  3962. IL_CMD(CONTROL_BACK);
  3963. IL_CMD(CONTROL_PSPOLL);
  3964. IL_CMD(CONTROL_RTS);
  3965. IL_CMD(CONTROL_CTS);
  3966. IL_CMD(CONTROL_ACK);
  3967. IL_CMD(CONTROL_CFEND);
  3968. IL_CMD(CONTROL_CFENDACK);
  3969. default:
  3970. return "UNKNOWN";
  3971. }
  3972. }
  3973. void il_clear_traffic_stats(struct il_priv *il)
  3974. {
  3975. memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
  3976. memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
  3977. }
  3978. /*
  3979. * if CONFIG_IWLEGACY_DEBUGFS defined,
  3980. * il_update_stats function will
  3981. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
  3982. * Use debugFs to display the rx/rx_stats
  3983. * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
  3984. * information will be recorded, but DATA pkt still will be recorded
  3985. * for the reason of il_led.c need to control the led blinking based on
  3986. * number of tx and rx data.
  3987. *
  3988. */
  3989. void
  3990. il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
  3991. {
  3992. struct traffic_stats *stats;
  3993. if (is_tx)
  3994. stats = &il->tx_stats;
  3995. else
  3996. stats = &il->rx_stats;
  3997. if (ieee80211_is_mgmt(fc)) {
  3998. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  3999. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4000. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  4001. break;
  4002. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  4003. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  4004. break;
  4005. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4006. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  4007. break;
  4008. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  4009. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  4010. break;
  4011. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  4012. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  4013. break;
  4014. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  4015. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  4016. break;
  4017. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  4018. stats->mgmt[MANAGEMENT_BEACON]++;
  4019. break;
  4020. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  4021. stats->mgmt[MANAGEMENT_ATIM]++;
  4022. break;
  4023. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  4024. stats->mgmt[MANAGEMENT_DISASSOC]++;
  4025. break;
  4026. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4027. stats->mgmt[MANAGEMENT_AUTH]++;
  4028. break;
  4029. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4030. stats->mgmt[MANAGEMENT_DEAUTH]++;
  4031. break;
  4032. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  4033. stats->mgmt[MANAGEMENT_ACTION]++;
  4034. break;
  4035. }
  4036. } else if (ieee80211_is_ctl(fc)) {
  4037. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4038. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  4039. stats->ctrl[CONTROL_BACK_REQ]++;
  4040. break;
  4041. case cpu_to_le16(IEEE80211_STYPE_BACK):
  4042. stats->ctrl[CONTROL_BACK]++;
  4043. break;
  4044. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  4045. stats->ctrl[CONTROL_PSPOLL]++;
  4046. break;
  4047. case cpu_to_le16(IEEE80211_STYPE_RTS):
  4048. stats->ctrl[CONTROL_RTS]++;
  4049. break;
  4050. case cpu_to_le16(IEEE80211_STYPE_CTS):
  4051. stats->ctrl[CONTROL_CTS]++;
  4052. break;
  4053. case cpu_to_le16(IEEE80211_STYPE_ACK):
  4054. stats->ctrl[CONTROL_ACK]++;
  4055. break;
  4056. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  4057. stats->ctrl[CONTROL_CFEND]++;
  4058. break;
  4059. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  4060. stats->ctrl[CONTROL_CFENDACK]++;
  4061. break;
  4062. }
  4063. } else {
  4064. /* data */
  4065. stats->data_cnt++;
  4066. stats->data_bytes += len;
  4067. }
  4068. }
  4069. EXPORT_SYMBOL(il_update_stats);
  4070. #endif
  4071. int il_force_reset(struct il_priv *il, bool external)
  4072. {
  4073. struct il_force_reset *force_reset;
  4074. if (test_bit(S_EXIT_PENDING, &il->status))
  4075. return -EINVAL;
  4076. force_reset = &il->force_reset;
  4077. force_reset->reset_request_count++;
  4078. if (!external) {
  4079. if (force_reset->last_force_reset_jiffies &&
  4080. time_after(force_reset->last_force_reset_jiffies +
  4081. force_reset->reset_duration, jiffies)) {
  4082. D_INFO("force reset rejected\n");
  4083. force_reset->reset_reject_count++;
  4084. return -EAGAIN;
  4085. }
  4086. }
  4087. force_reset->reset_success_count++;
  4088. force_reset->last_force_reset_jiffies = jiffies;
  4089. /*
  4090. * if the request is from external(ex: debugfs),
  4091. * then always perform the request in regardless the module
  4092. * parameter setting
  4093. * if the request is from internal (uCode error or driver
  4094. * detect failure), then fw_restart module parameter
  4095. * need to be check before performing firmware reload
  4096. */
  4097. if (!external && !il->cfg->mod_params->restart_fw) {
  4098. D_INFO("Cancel firmware reload based on "
  4099. "module parameter setting\n");
  4100. return 0;
  4101. }
  4102. IL_ERR("On demand firmware reload\n");
  4103. /* Set the FW error flag -- cleared on il_down */
  4104. set_bit(S_FW_ERROR, &il->status);
  4105. wake_up(&il->wait_command_queue);
  4106. /*
  4107. * Keep the restart process from trying to send host
  4108. * commands by clearing the INIT status bit
  4109. */
  4110. clear_bit(S_READY, &il->status);
  4111. queue_work(il->workqueue, &il->restart);
  4112. return 0;
  4113. }
  4114. int
  4115. il_mac_change_interface(struct ieee80211_hw *hw,
  4116. struct ieee80211_vif *vif,
  4117. enum nl80211_iftype newtype, bool newp2p)
  4118. {
  4119. struct il_priv *il = hw->priv;
  4120. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4121. u32 modes;
  4122. int err;
  4123. newtype = ieee80211_iftype_p2p(newtype, newp2p);
  4124. mutex_lock(&il->mutex);
  4125. if (!ctx->vif || !il_is_ready_rf(il)) {
  4126. /*
  4127. * Huh? But wait ... this can maybe happen when
  4128. * we're in the middle of a firmware restart!
  4129. */
  4130. err = -EBUSY;
  4131. goto out;
  4132. }
  4133. modes = ctx->interface_modes | ctx->exclusive_interface_modes;
  4134. if (!(modes & BIT(newtype))) {
  4135. err = -EOPNOTSUPP;
  4136. goto out;
  4137. }
  4138. if ((il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type)) ||
  4139. (il->ctx.exclusive_interface_modes & BIT(newtype))) {
  4140. err = -EINVAL;
  4141. goto out;
  4142. }
  4143. /* success */
  4144. il_teardown_interface(il, vif, true);
  4145. vif->type = newtype;
  4146. vif->p2p = newp2p;
  4147. err = il_setup_interface(il, ctx);
  4148. WARN_ON(err);
  4149. /*
  4150. * We've switched internally, but submitting to the
  4151. * device may have failed for some reason. Mask this
  4152. * error, because otherwise mac80211 will not switch
  4153. * (and set the interface type back) and we'll be
  4154. * out of sync with it.
  4155. */
  4156. err = 0;
  4157. out:
  4158. mutex_unlock(&il->mutex);
  4159. return err;
  4160. }
  4161. EXPORT_SYMBOL(il_mac_change_interface);
  4162. /*
  4163. * On every watchdog tick we check (latest) time stamp. If it does not
  4164. * change during timeout period and queue is not empty we reset firmware.
  4165. */
  4166. static int il_check_stuck_queue(struct il_priv *il, int cnt)
  4167. {
  4168. struct il_tx_queue *txq = &il->txq[cnt];
  4169. struct il_queue *q = &txq->q;
  4170. unsigned long timeout;
  4171. int ret;
  4172. if (q->read_ptr == q->write_ptr) {
  4173. txq->time_stamp = jiffies;
  4174. return 0;
  4175. }
  4176. timeout = txq->time_stamp +
  4177. msecs_to_jiffies(il->cfg->base_params->wd_timeout);
  4178. if (time_after(jiffies, timeout)) {
  4179. IL_ERR("Queue %d stuck for %u ms.\n",
  4180. q->id, il->cfg->base_params->wd_timeout);
  4181. ret = il_force_reset(il, false);
  4182. return (ret == -EAGAIN) ? 0 : 1;
  4183. }
  4184. return 0;
  4185. }
  4186. /*
  4187. * Making watchdog tick be a quarter of timeout assure we will
  4188. * discover the queue hung between timeout and 1.25*timeout
  4189. */
  4190. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4191. /*
  4192. * Watchdog timer callback, we check each tx queue for stuck, if if hung
  4193. * we reset the firmware. If everything is fine just rearm the timer.
  4194. */
  4195. void il_bg_watchdog(unsigned long data)
  4196. {
  4197. struct il_priv *il = (struct il_priv *)data;
  4198. int cnt;
  4199. unsigned long timeout;
  4200. if (test_bit(S_EXIT_PENDING, &il->status))
  4201. return;
  4202. timeout = il->cfg->base_params->wd_timeout;
  4203. if (timeout == 0)
  4204. return;
  4205. /* monitor and check for stuck cmd queue */
  4206. if (il_check_stuck_queue(il, il->cmd_queue))
  4207. return;
  4208. /* monitor and check for other stuck queues */
  4209. if (il_is_any_associated(il)) {
  4210. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4211. /* skip as we already checked the command queue */
  4212. if (cnt == il->cmd_queue)
  4213. continue;
  4214. if (il_check_stuck_queue(il, cnt))
  4215. return;
  4216. }
  4217. }
  4218. mod_timer(&il->watchdog, jiffies +
  4219. msecs_to_jiffies(IL_WD_TICK(timeout)));
  4220. }
  4221. EXPORT_SYMBOL(il_bg_watchdog);
  4222. void il_setup_watchdog(struct il_priv *il)
  4223. {
  4224. unsigned int timeout = il->cfg->base_params->wd_timeout;
  4225. if (timeout)
  4226. mod_timer(&il->watchdog,
  4227. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4228. else
  4229. del_timer(&il->watchdog);
  4230. }
  4231. EXPORT_SYMBOL(il_setup_watchdog);
  4232. /*
  4233. * extended beacon time format
  4234. * time in usec will be changed into a 32-bit value in extended:internal format
  4235. * the extended part is the beacon counts
  4236. * the internal part is the time in usec within one beacon interval
  4237. */
  4238. u32
  4239. il_usecs_to_beacons(struct il_priv *il,
  4240. u32 usec, u32 beacon_interval)
  4241. {
  4242. u32 quot;
  4243. u32 rem;
  4244. u32 interval = beacon_interval * TIME_UNIT;
  4245. if (!interval || !usec)
  4246. return 0;
  4247. quot = (usec / interval) &
  4248. (il_beacon_time_mask_high(il,
  4249. il->hw_params.beacon_time_tsf_bits) >>
  4250. il->hw_params.beacon_time_tsf_bits);
  4251. rem = (usec % interval) & il_beacon_time_mask_low(il,
  4252. il->hw_params.beacon_time_tsf_bits);
  4253. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4254. }
  4255. EXPORT_SYMBOL(il_usecs_to_beacons);
  4256. /* base is usually what we get from ucode with each received frame,
  4257. * the same as HW timer counter counting down
  4258. */
  4259. __le32 il_add_beacon_time(struct il_priv *il, u32 base,
  4260. u32 addon, u32 beacon_interval)
  4261. {
  4262. u32 base_low = base & il_beacon_time_mask_low(il,
  4263. il->hw_params.beacon_time_tsf_bits);
  4264. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4265. il->hw_params.beacon_time_tsf_bits);
  4266. u32 interval = beacon_interval * TIME_UNIT;
  4267. u32 res = (base & il_beacon_time_mask_high(il,
  4268. il->hw_params.beacon_time_tsf_bits)) +
  4269. (addon & il_beacon_time_mask_high(il,
  4270. il->hw_params.beacon_time_tsf_bits));
  4271. if (base_low > addon_low)
  4272. res += base_low - addon_low;
  4273. else if (base_low < addon_low) {
  4274. res += interval + base_low - addon_low;
  4275. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4276. } else
  4277. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4278. return cpu_to_le32(res);
  4279. }
  4280. EXPORT_SYMBOL(il_add_beacon_time);
  4281. #ifdef CONFIG_PM
  4282. int il_pci_suspend(struct device *device)
  4283. {
  4284. struct pci_dev *pdev = to_pci_dev(device);
  4285. struct il_priv *il = pci_get_drvdata(pdev);
  4286. /*
  4287. * This function is called when system goes into suspend state
  4288. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4289. * first but since il_mac_stop() has no knowledge of who the caller is,
  4290. * it will not call apm_ops.stop() to stop the DMA operation.
  4291. * Calling apm_ops.stop here to make sure we stop the DMA.
  4292. */
  4293. il_apm_stop(il);
  4294. return 0;
  4295. }
  4296. EXPORT_SYMBOL(il_pci_suspend);
  4297. int il_pci_resume(struct device *device)
  4298. {
  4299. struct pci_dev *pdev = to_pci_dev(device);
  4300. struct il_priv *il = pci_get_drvdata(pdev);
  4301. bool hw_rfkill = false;
  4302. /*
  4303. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4304. * PCI Tx retries from interfering with C3 CPU state.
  4305. */
  4306. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4307. il_enable_interrupts(il);
  4308. if (!(_il_rd(il, CSR_GP_CNTRL) &
  4309. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4310. hw_rfkill = true;
  4311. if (hw_rfkill)
  4312. set_bit(S_RF_KILL_HW, &il->status);
  4313. else
  4314. clear_bit(S_RF_KILL_HW, &il->status);
  4315. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4316. return 0;
  4317. }
  4318. EXPORT_SYMBOL(il_pci_resume);
  4319. const struct dev_pm_ops il_pm_ops = {
  4320. .suspend = il_pci_suspend,
  4321. .resume = il_pci_resume,
  4322. .freeze = il_pci_suspend,
  4323. .thaw = il_pci_resume,
  4324. .poweroff = il_pci_suspend,
  4325. .restore = il_pci_resume,
  4326. };
  4327. EXPORT_SYMBOL(il_pm_ops);
  4328. #endif /* CONFIG_PM */
  4329. static void
  4330. il_update_qos(struct il_priv *il, struct il_rxon_context *ctx)
  4331. {
  4332. if (test_bit(S_EXIT_PENDING, &il->status))
  4333. return;
  4334. if (!ctx->is_active)
  4335. return;
  4336. ctx->qos_data.def_qos_parm.qos_flags = 0;
  4337. if (ctx->qos_data.qos_active)
  4338. ctx->qos_data.def_qos_parm.qos_flags |=
  4339. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4340. if (ctx->ht.enabled)
  4341. ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4342. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4343. ctx->qos_data.qos_active,
  4344. ctx->qos_data.def_qos_parm.qos_flags);
  4345. il_send_cmd_pdu_async(il, ctx->qos_cmd,
  4346. sizeof(struct il_qosparam_cmd),
  4347. &ctx->qos_data.def_qos_parm, NULL);
  4348. }
  4349. /**
  4350. * il_mac_config - mac80211 config callback
  4351. */
  4352. int il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4353. {
  4354. struct il_priv *il = hw->priv;
  4355. const struct il_channel_info *ch_info;
  4356. struct ieee80211_conf *conf = &hw->conf;
  4357. struct ieee80211_channel *channel = conf->channel;
  4358. struct il_ht_config *ht_conf = &il->current_ht_config;
  4359. struct il_rxon_context *ctx = &il->ctx;
  4360. unsigned long flags = 0;
  4361. int ret = 0;
  4362. u16 ch;
  4363. int scan_active = 0;
  4364. bool ht_changed = false;
  4365. if (WARN_ON(!il->cfg->ops->legacy))
  4366. return -EOPNOTSUPP;
  4367. mutex_lock(&il->mutex);
  4368. D_MAC80211("enter to channel %d changed 0x%X\n",
  4369. channel->hw_value, changed);
  4370. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4371. scan_active = 1;
  4372. D_MAC80211("scan active\n");
  4373. }
  4374. if (changed & (IEEE80211_CONF_CHANGE_SMPS |
  4375. IEEE80211_CONF_CHANGE_CHANNEL)) {
  4376. /* mac80211 uses static for non-HT which is what we want */
  4377. il->current_ht_config.smps = conf->smps_mode;
  4378. /*
  4379. * Recalculate chain counts.
  4380. *
  4381. * If monitor mode is enabled then mac80211 will
  4382. * set up the SM PS mode to OFF if an HT channel is
  4383. * configured.
  4384. */
  4385. if (il->cfg->ops->hcmd->set_rxon_chain)
  4386. il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
  4387. }
  4388. /* during scanning mac80211 will delay channel setting until
  4389. * scan finish with changed = 0
  4390. */
  4391. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4392. if (scan_active)
  4393. goto set_ch_out;
  4394. ch = channel->hw_value;
  4395. ch_info = il_get_channel_info(il, channel->band, ch);
  4396. if (!il_is_channel_valid(ch_info)) {
  4397. D_MAC80211("leave - invalid channel\n");
  4398. ret = -EINVAL;
  4399. goto set_ch_out;
  4400. }
  4401. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4402. !il_is_channel_ibss(ch_info)) {
  4403. D_MAC80211("leave - not IBSS channel\n");
  4404. ret = -EINVAL;
  4405. goto set_ch_out;
  4406. }
  4407. spin_lock_irqsave(&il->lock, flags);
  4408. /* Configure HT40 channels */
  4409. if (ctx->ht.enabled != conf_is_ht(conf)) {
  4410. ctx->ht.enabled = conf_is_ht(conf);
  4411. ht_changed = true;
  4412. }
  4413. if (ctx->ht.enabled) {
  4414. if (conf_is_ht40_minus(conf)) {
  4415. ctx->ht.extension_chan_offset =
  4416. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4417. ctx->ht.is_40mhz = true;
  4418. } else if (conf_is_ht40_plus(conf)) {
  4419. ctx->ht.extension_chan_offset =
  4420. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4421. ctx->ht.is_40mhz = true;
  4422. } else {
  4423. ctx->ht.extension_chan_offset =
  4424. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4425. ctx->ht.is_40mhz = false;
  4426. }
  4427. } else
  4428. ctx->ht.is_40mhz = false;
  4429. /*
  4430. * Default to no protection. Protection mode will
  4431. * later be set from BSS config in il_ht_conf
  4432. */
  4433. ctx->ht.protection =
  4434. IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4435. /* if we are switching from ht to 2.4 clear flags
  4436. * from any ht related info since 2.4 does not
  4437. * support ht */
  4438. if ((le16_to_cpu(ctx->staging.channel) != ch))
  4439. ctx->staging.flags = 0;
  4440. il_set_rxon_channel(il, channel, ctx);
  4441. il_set_rxon_ht(il, ht_conf);
  4442. il_set_flags_for_band(il, ctx, channel->band,
  4443. ctx->vif);
  4444. spin_unlock_irqrestore(&il->lock, flags);
  4445. if (il->cfg->ops->legacy->update_bcast_stations)
  4446. ret =
  4447. il->cfg->ops->legacy->update_bcast_stations(il);
  4448. set_ch_out:
  4449. /* The list of supported rates and rate mask can be different
  4450. * for each band; since the band may have changed, reset
  4451. * the rate mask to what mac80211 lists */
  4452. il_set_rate(il);
  4453. }
  4454. if (changed & (IEEE80211_CONF_CHANGE_PS |
  4455. IEEE80211_CONF_CHANGE_IDLE)) {
  4456. ret = il_power_update_mode(il, false);
  4457. if (ret)
  4458. D_MAC80211("Error setting sleep level\n");
  4459. }
  4460. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4461. D_MAC80211("TX Power old=%d new=%d\n",
  4462. il->tx_power_user_lmt, conf->power_level);
  4463. il_set_tx_power(il, conf->power_level, false);
  4464. }
  4465. if (!il_is_ready(il)) {
  4466. D_MAC80211("leave - not ready\n");
  4467. goto out;
  4468. }
  4469. if (scan_active)
  4470. goto out;
  4471. if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
  4472. il_commit_rxon(il, ctx);
  4473. else
  4474. D_INFO("Not re-sending same RXON configuration.\n");
  4475. if (ht_changed)
  4476. il_update_qos(il, ctx);
  4477. out:
  4478. D_MAC80211("leave\n");
  4479. mutex_unlock(&il->mutex);
  4480. return ret;
  4481. }
  4482. EXPORT_SYMBOL(il_mac_config);
  4483. void il_mac_reset_tsf(struct ieee80211_hw *hw,
  4484. struct ieee80211_vif *vif)
  4485. {
  4486. struct il_priv *il = hw->priv;
  4487. unsigned long flags;
  4488. struct il_rxon_context *ctx = &il->ctx;
  4489. if (WARN_ON(!il->cfg->ops->legacy))
  4490. return;
  4491. mutex_lock(&il->mutex);
  4492. D_MAC80211("enter\n");
  4493. spin_lock_irqsave(&il->lock, flags);
  4494. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4495. spin_unlock_irqrestore(&il->lock, flags);
  4496. spin_lock_irqsave(&il->lock, flags);
  4497. /* new association get rid of ibss beacon skb */
  4498. if (il->beacon_skb)
  4499. dev_kfree_skb(il->beacon_skb);
  4500. il->beacon_skb = NULL;
  4501. il->timestamp = 0;
  4502. spin_unlock_irqrestore(&il->lock, flags);
  4503. il_scan_cancel_timeout(il, 100);
  4504. if (!il_is_ready_rf(il)) {
  4505. D_MAC80211("leave - not ready\n");
  4506. mutex_unlock(&il->mutex);
  4507. return;
  4508. }
  4509. /* we are restarting association process
  4510. * clear RXON_FILTER_ASSOC_MSK bit
  4511. */
  4512. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4513. il_commit_rxon(il, ctx);
  4514. il_set_rate(il);
  4515. mutex_unlock(&il->mutex);
  4516. D_MAC80211("leave\n");
  4517. }
  4518. EXPORT_SYMBOL(il_mac_reset_tsf);
  4519. static void il_ht_conf(struct il_priv *il,
  4520. struct ieee80211_vif *vif)
  4521. {
  4522. struct il_ht_config *ht_conf = &il->current_ht_config;
  4523. struct ieee80211_sta *sta;
  4524. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4525. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4526. D_ASSOC("enter:\n");
  4527. if (!ctx->ht.enabled)
  4528. return;
  4529. ctx->ht.protection =
  4530. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4531. ctx->ht.non_gf_sta_present =
  4532. !!(bss_conf->ht_operation_mode &
  4533. IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4534. ht_conf->single_chain_sufficient = false;
  4535. switch (vif->type) {
  4536. case NL80211_IFTYPE_STATION:
  4537. rcu_read_lock();
  4538. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4539. if (sta) {
  4540. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  4541. int maxstreams;
  4542. maxstreams = (ht_cap->mcs.tx_params &
  4543. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4544. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4545. maxstreams += 1;
  4546. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4547. ht_cap->mcs.rx_mask[2] == 0)
  4548. ht_conf->single_chain_sufficient = true;
  4549. if (maxstreams <= 1)
  4550. ht_conf->single_chain_sufficient = true;
  4551. } else {
  4552. /*
  4553. * If at all, this can only happen through a race
  4554. * when the AP disconnects us while we're still
  4555. * setting up the connection, in that case mac80211
  4556. * will soon tell us about that.
  4557. */
  4558. ht_conf->single_chain_sufficient = true;
  4559. }
  4560. rcu_read_unlock();
  4561. break;
  4562. case NL80211_IFTYPE_ADHOC:
  4563. ht_conf->single_chain_sufficient = true;
  4564. break;
  4565. default:
  4566. break;
  4567. }
  4568. D_ASSOC("leave\n");
  4569. }
  4570. static inline void il_set_no_assoc(struct il_priv *il,
  4571. struct ieee80211_vif *vif)
  4572. {
  4573. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4574. /*
  4575. * inform the ucode that there is no longer an
  4576. * association and that no more packets should be
  4577. * sent
  4578. */
  4579. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4580. ctx->staging.assoc_id = 0;
  4581. il_commit_rxon(il, ctx);
  4582. }
  4583. static void il_beacon_update(struct ieee80211_hw *hw,
  4584. struct ieee80211_vif *vif)
  4585. {
  4586. struct il_priv *il = hw->priv;
  4587. unsigned long flags;
  4588. __le64 timestamp;
  4589. struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
  4590. if (!skb)
  4591. return;
  4592. D_MAC80211("enter\n");
  4593. lockdep_assert_held(&il->mutex);
  4594. if (!il->beacon_ctx) {
  4595. IL_ERR("update beacon but no beacon context!\n");
  4596. dev_kfree_skb(skb);
  4597. return;
  4598. }
  4599. spin_lock_irqsave(&il->lock, flags);
  4600. if (il->beacon_skb)
  4601. dev_kfree_skb(il->beacon_skb);
  4602. il->beacon_skb = skb;
  4603. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4604. il->timestamp = le64_to_cpu(timestamp);
  4605. D_MAC80211("leave\n");
  4606. spin_unlock_irqrestore(&il->lock, flags);
  4607. if (!il_is_ready_rf(il)) {
  4608. D_MAC80211("leave - RF not ready\n");
  4609. return;
  4610. }
  4611. il->cfg->ops->legacy->post_associate(il);
  4612. }
  4613. void il_mac_bss_info_changed(struct ieee80211_hw *hw,
  4614. struct ieee80211_vif *vif,
  4615. struct ieee80211_bss_conf *bss_conf,
  4616. u32 changes)
  4617. {
  4618. struct il_priv *il = hw->priv;
  4619. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4620. int ret;
  4621. if (WARN_ON(!il->cfg->ops->legacy))
  4622. return;
  4623. D_MAC80211("changes = 0x%X\n", changes);
  4624. mutex_lock(&il->mutex);
  4625. if (!il_is_alive(il)) {
  4626. mutex_unlock(&il->mutex);
  4627. return;
  4628. }
  4629. if (changes & BSS_CHANGED_QOS) {
  4630. unsigned long flags;
  4631. spin_lock_irqsave(&il->lock, flags);
  4632. ctx->qos_data.qos_active = bss_conf->qos;
  4633. il_update_qos(il, ctx);
  4634. spin_unlock_irqrestore(&il->lock, flags);
  4635. }
  4636. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4637. /*
  4638. * the add_interface code must make sure we only ever
  4639. * have a single interface that could be beaconing at
  4640. * any time.
  4641. */
  4642. if (vif->bss_conf.enable_beacon)
  4643. il->beacon_ctx = ctx;
  4644. else
  4645. il->beacon_ctx = NULL;
  4646. }
  4647. if (changes & BSS_CHANGED_BSSID) {
  4648. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4649. /*
  4650. * If there is currently a HW scan going on in the
  4651. * background then we need to cancel it else the RXON
  4652. * below/in post_associate will fail.
  4653. */
  4654. if (il_scan_cancel_timeout(il, 100)) {
  4655. IL_WARN(
  4656. "Aborted scan still in progress after 100ms\n");
  4657. D_MAC80211(
  4658. "leaving - scan abort failed.\n");
  4659. mutex_unlock(&il->mutex);
  4660. return;
  4661. }
  4662. /* mac80211 only sets assoc when in STATION mode */
  4663. if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
  4664. memcpy(ctx->staging.bssid_addr,
  4665. bss_conf->bssid, ETH_ALEN);
  4666. /* currently needed in a few places */
  4667. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4668. } else {
  4669. ctx->staging.filter_flags &=
  4670. ~RXON_FILTER_ASSOC_MSK;
  4671. }
  4672. }
  4673. /*
  4674. * This needs to be after setting the BSSID in case
  4675. * mac80211 decides to do both changes at once because
  4676. * it will invoke post_associate.
  4677. */
  4678. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4679. il_beacon_update(hw, vif);
  4680. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4681. D_MAC80211("ERP_PREAMBLE %d\n",
  4682. bss_conf->use_short_preamble);
  4683. if (bss_conf->use_short_preamble)
  4684. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4685. else
  4686. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4687. }
  4688. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4689. D_MAC80211(
  4690. "ERP_CTS %d\n", bss_conf->use_cts_prot);
  4691. if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
  4692. ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4693. else
  4694. ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4695. if (bss_conf->use_cts_prot)
  4696. ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4697. else
  4698. ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4699. }
  4700. if (changes & BSS_CHANGED_BASIC_RATES) {
  4701. /* XXX use this information
  4702. *
  4703. * To do that, remove code from il_set_rate() and put something
  4704. * like this here:
  4705. *
  4706. if (A-band)
  4707. ctx->staging.ofdm_basic_rates =
  4708. bss_conf->basic_rates;
  4709. else
  4710. ctx->staging.ofdm_basic_rates =
  4711. bss_conf->basic_rates >> 4;
  4712. ctx->staging.cck_basic_rates =
  4713. bss_conf->basic_rates & 0xF;
  4714. */
  4715. }
  4716. if (changes & BSS_CHANGED_HT) {
  4717. il_ht_conf(il, vif);
  4718. if (il->cfg->ops->hcmd->set_rxon_chain)
  4719. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  4720. }
  4721. if (changes & BSS_CHANGED_ASSOC) {
  4722. D_MAC80211("ASSOC %d\n", bss_conf->assoc);
  4723. if (bss_conf->assoc) {
  4724. il->timestamp = bss_conf->timestamp;
  4725. if (!il_is_rfkill(il))
  4726. il->cfg->ops->legacy->post_associate(il);
  4727. } else
  4728. il_set_no_assoc(il, vif);
  4729. }
  4730. if (changes && il_is_associated_ctx(ctx) && bss_conf->aid) {
  4731. D_MAC80211("Changes (%#x) while associated\n",
  4732. changes);
  4733. ret = il_send_rxon_assoc(il, ctx);
  4734. if (!ret) {
  4735. /* Sync active_rxon with latest change. */
  4736. memcpy((void *)&ctx->active,
  4737. &ctx->staging,
  4738. sizeof(struct il_rxon_cmd));
  4739. }
  4740. }
  4741. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4742. if (vif->bss_conf.enable_beacon) {
  4743. memcpy(ctx->staging.bssid_addr,
  4744. bss_conf->bssid, ETH_ALEN);
  4745. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4746. il->cfg->ops->legacy->config_ap(il);
  4747. } else
  4748. il_set_no_assoc(il, vif);
  4749. }
  4750. if (changes & BSS_CHANGED_IBSS) {
  4751. ret = il->cfg->ops->legacy->manage_ibss_station(il, vif,
  4752. bss_conf->ibss_joined);
  4753. if (ret)
  4754. IL_ERR("failed to %s IBSS station %pM\n",
  4755. bss_conf->ibss_joined ? "add" : "remove",
  4756. bss_conf->bssid);
  4757. }
  4758. mutex_unlock(&il->mutex);
  4759. D_MAC80211("leave\n");
  4760. }
  4761. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4762. irqreturn_t il_isr(int irq, void *data)
  4763. {
  4764. struct il_priv *il = data;
  4765. u32 inta, inta_mask;
  4766. u32 inta_fh;
  4767. unsigned long flags;
  4768. if (!il)
  4769. return IRQ_NONE;
  4770. spin_lock_irqsave(&il->lock, flags);
  4771. /* Disable (but don't clear!) interrupts here to avoid
  4772. * back-to-back ISRs and sporadic interrupts from our NIC.
  4773. * If we have something to service, the tasklet will re-enable ints.
  4774. * If we *don't* have something, we'll re-enable before leaving here. */
  4775. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4776. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4777. /* Discover which interrupts are active/pending */
  4778. inta = _il_rd(il, CSR_INT);
  4779. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4780. /* Ignore interrupt if there's nothing in NIC to service.
  4781. * This may be due to IRQ shared with another device,
  4782. * or due to sporadic interrupts thrown from our NIC. */
  4783. if (!inta && !inta_fh) {
  4784. D_ISR(
  4785. "Ignore interrupt, inta == 0, inta_fh == 0\n");
  4786. goto none;
  4787. }
  4788. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4789. /* Hardware disappeared. It might have already raised
  4790. * an interrupt */
  4791. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4792. goto unplugged;
  4793. }
  4794. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4795. inta, inta_mask, inta_fh);
  4796. inta &= ~CSR_INT_BIT_SCD;
  4797. /* il_irq_tasklet() will service interrupts and re-enable them */
  4798. if (likely(inta || inta_fh))
  4799. tasklet_schedule(&il->irq_tasklet);
  4800. unplugged:
  4801. spin_unlock_irqrestore(&il->lock, flags);
  4802. return IRQ_HANDLED;
  4803. none:
  4804. /* re-enable interrupts here since we don't have anything to service. */
  4805. /* only Re-enable if disabled by irq */
  4806. if (test_bit(S_INT_ENABLED, &il->status))
  4807. il_enable_interrupts(il);
  4808. spin_unlock_irqrestore(&il->lock, flags);
  4809. return IRQ_NONE;
  4810. }
  4811. EXPORT_SYMBOL(il_isr);
  4812. /*
  4813. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4814. * function.
  4815. */
  4816. void il_tx_cmd_protection(struct il_priv *il,
  4817. struct ieee80211_tx_info *info,
  4818. __le16 fc, __le32 *tx_flags)
  4819. {
  4820. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4821. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4822. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4823. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4824. if (!ieee80211_is_mgmt(fc))
  4825. return;
  4826. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4827. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4828. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4829. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4830. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4831. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4832. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4833. break;
  4834. }
  4835. } else if (info->control.rates[0].flags &
  4836. IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4837. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4838. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4839. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4840. }
  4841. }
  4842. EXPORT_SYMBOL(il_tx_cmd_protection);