piix.c 14 KB

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  1. /*
  2. * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
  3. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  4. * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
  5. * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  6. *
  7. * May be copied or modified under the terms of the GNU General Public License
  8. *
  9. * Documentation:
  10. *
  11. * Publically available from Intel web site. Errata documentation
  12. * is also publically available. As an aide to anyone hacking on this
  13. * driver the list of errata that are relevant is below.going back to
  14. * PIIX4. Older device documentation is now a bit tricky to find.
  15. *
  16. * Errata of note:
  17. *
  18. * Unfixable
  19. * PIIX4 errata #9 - Only on ultra obscure hw
  20. * ICH3 errata #13 - Not observed to affect real hw
  21. * by Intel
  22. *
  23. * Things we must deal with
  24. * PIIX4 errata #10 - BM IDE hang with non UDMA
  25. * (must stop/start dma to recover)
  26. * 440MX errata #15 - As PIIX4 errata #10
  27. * PIIX4 errata #15 - Must not read control registers
  28. * during a PIO transfer
  29. * 440MX errata #13 - As PIIX4 errata #15
  30. * ICH2 errata #21 - DMA mode 0 doesn't work right
  31. * ICH0/1 errata #55 - As ICH2 errata #21
  32. * ICH2 spec c #9 - Extra operations needed to handle
  33. * drive hotswap [NOT YET SUPPORTED]
  34. * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
  35. * and must be dword aligned
  36. * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  37. *
  38. * Should have been BIOS fixed:
  39. * 450NX: errata #19 - DMA hangs on old 450NX
  40. * 450NX: errata #20 - DMA hangs on old 450NX
  41. * 450NX: errata #25 - Corruption with DMA on old 450NX
  42. * ICH3 errata #15 - IDE deadlock under high load
  43. * (BIOS must set dev 31 fn 0 bit 23)
  44. * ICH3 errata #18 - Don't use native mode
  45. */
  46. #include <linux/types.h>
  47. #include <linux/module.h>
  48. #include <linux/kernel.h>
  49. #include <linux/pci.h>
  50. #include <linux/hdreg.h>
  51. #include <linux/ide.h>
  52. #include <linux/init.h>
  53. #include <asm/io.h>
  54. static int no_piix_dma;
  55. /**
  56. * piix_set_pio_mode - set host controller for PIO mode
  57. * @drive: drive
  58. * @pio: PIO mode number
  59. *
  60. * Set the interface PIO mode based upon the settings done by AMI BIOS.
  61. */
  62. static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
  63. {
  64. ide_hwif_t *hwif = HWIF(drive);
  65. struct pci_dev *dev = to_pci_dev(hwif->dev);
  66. int is_slave = drive->dn & 1;
  67. int master_port = hwif->channel ? 0x42 : 0x40;
  68. int slave_port = 0x44;
  69. unsigned long flags;
  70. u16 master_data;
  71. u8 slave_data;
  72. static DEFINE_SPINLOCK(tune_lock);
  73. int control = 0;
  74. /* ISP RTC */
  75. static const u8 timings[][2]= {
  76. { 0, 0 },
  77. { 0, 0 },
  78. { 1, 0 },
  79. { 2, 1 },
  80. { 2, 3 }, };
  81. /*
  82. * Master vs slave is synchronized above us but the slave register is
  83. * shared by the two hwifs so the corner case of two slave timeouts in
  84. * parallel must be locked.
  85. */
  86. spin_lock_irqsave(&tune_lock, flags);
  87. pci_read_config_word(dev, master_port, &master_data);
  88. if (pio > 1)
  89. control |= 1; /* Programmable timing on */
  90. if (drive->media == ide_disk)
  91. control |= 4; /* Prefetch, post write */
  92. if (pio > 2)
  93. control |= 2; /* IORDY */
  94. if (is_slave) {
  95. master_data |= 0x4000;
  96. master_data &= ~0x0070;
  97. if (pio > 1) {
  98. /* Set PPE, IE and TIME */
  99. master_data |= control << 4;
  100. }
  101. pci_read_config_byte(dev, slave_port, &slave_data);
  102. slave_data &= hwif->channel ? 0x0f : 0xf0;
  103. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  104. (hwif->channel ? 4 : 0);
  105. } else {
  106. master_data &= ~0x3307;
  107. if (pio > 1) {
  108. /* enable PPE, IE and TIME */
  109. master_data |= control;
  110. }
  111. master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  112. }
  113. pci_write_config_word(dev, master_port, master_data);
  114. if (is_slave)
  115. pci_write_config_byte(dev, slave_port, slave_data);
  116. spin_unlock_irqrestore(&tune_lock, flags);
  117. }
  118. /**
  119. * piix_set_dma_mode - set host controller for DMA mode
  120. * @drive: drive
  121. * @speed: DMA mode
  122. *
  123. * Set a PIIX host controller to the desired DMA mode. This involves
  124. * programming the right timing data into the PCI configuration space.
  125. */
  126. static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
  127. {
  128. ide_hwif_t *hwif = HWIF(drive);
  129. struct pci_dev *dev = to_pci_dev(hwif->dev);
  130. u8 maslave = hwif->channel ? 0x42 : 0x40;
  131. int a_speed = 3 << (drive->dn * 4);
  132. int u_flag = 1 << drive->dn;
  133. int v_flag = 0x01 << drive->dn;
  134. int w_flag = 0x10 << drive->dn;
  135. int u_speed = 0;
  136. int sitre;
  137. u16 reg4042, reg4a;
  138. u8 reg48, reg54, reg55;
  139. pci_read_config_word(dev, maslave, &reg4042);
  140. sitre = (reg4042 & 0x4000) ? 1 : 0;
  141. pci_read_config_byte(dev, 0x48, &reg48);
  142. pci_read_config_word(dev, 0x4a, &reg4a);
  143. pci_read_config_byte(dev, 0x54, &reg54);
  144. pci_read_config_byte(dev, 0x55, &reg55);
  145. if (speed >= XFER_UDMA_0) {
  146. u8 udma = speed - XFER_UDMA_0;
  147. u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
  148. if (!(reg48 & u_flag))
  149. pci_write_config_byte(dev, 0x48, reg48 | u_flag);
  150. if (speed == XFER_UDMA_5) {
  151. pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
  152. } else {
  153. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  154. }
  155. if ((reg4a & a_speed) != u_speed)
  156. pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
  157. if (speed > XFER_UDMA_2) {
  158. if (!(reg54 & v_flag))
  159. pci_write_config_byte(dev, 0x54, reg54 | v_flag);
  160. } else
  161. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  162. } else {
  163. const u8 mwdma_to_pio[] = { 0, 3, 4 };
  164. u8 pio;
  165. if (reg48 & u_flag)
  166. pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
  167. if (reg4a & a_speed)
  168. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  169. if (reg54 & v_flag)
  170. pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
  171. if (reg55 & w_flag)
  172. pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
  173. if (speed >= XFER_MW_DMA_0)
  174. pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  175. else
  176. pio = 2; /* only SWDMA2 is allowed */
  177. piix_set_pio_mode(drive, pio);
  178. }
  179. }
  180. /**
  181. * init_chipset_ich - set up the ICH chipset
  182. * @dev: PCI device to set up
  183. * @name: Name of the device
  184. *
  185. * Initialize the PCI device as required. For the ICH this turns
  186. * out to be nice and simple.
  187. */
  188. static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
  189. {
  190. u32 extra = 0;
  191. pci_read_config_dword(dev, 0x54, &extra);
  192. pci_write_config_dword(dev, 0x54, extra | 0x400);
  193. return 0;
  194. }
  195. /**
  196. * piix_dma_clear_irq - clear BMDMA status
  197. * @drive: IDE drive to clear
  198. *
  199. * Called from ide_intr() for PIO interrupts
  200. * to clear BMDMA status as needed by ICHx
  201. */
  202. static void piix_dma_clear_irq(ide_drive_t *drive)
  203. {
  204. ide_hwif_t *hwif = HWIF(drive);
  205. u8 dma_stat;
  206. /* clear the INTR & ERROR bits */
  207. dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
  208. /* Should we force the bit as well ? */
  209. outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
  210. }
  211. struct ich_laptop {
  212. u16 device;
  213. u16 subvendor;
  214. u16 subdevice;
  215. };
  216. /*
  217. * List of laptops that use short cables rather than 80 wire
  218. */
  219. static const struct ich_laptop ich_laptop[] = {
  220. /* devid, subvendor, subdev */
  221. { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
  222. { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
  223. { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
  224. { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
  225. { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
  226. { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
  227. { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
  228. /* end marker */
  229. { 0, }
  230. };
  231. static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
  232. {
  233. struct pci_dev *pdev = to_pci_dev(hwif->dev);
  234. const struct ich_laptop *lap = &ich_laptop[0];
  235. u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
  236. /* check for specials */
  237. while (lap->device) {
  238. if (lap->device == pdev->device &&
  239. lap->subvendor == pdev->subsystem_vendor &&
  240. lap->subdevice == pdev->subsystem_device) {
  241. return ATA_CBL_PATA40_SHORT;
  242. }
  243. lap++;
  244. }
  245. pci_read_config_byte(pdev, 0x54, &reg54h);
  246. return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
  247. }
  248. /**
  249. * init_hwif_piix - fill in the hwif for the PIIX
  250. * @hwif: IDE interface
  251. *
  252. * Set up the ide_hwif_t for the PIIX interface according to the
  253. * capabilities of the hardware.
  254. */
  255. static void __devinit init_hwif_piix(ide_hwif_t *hwif)
  256. {
  257. if (!hwif->dma_base)
  258. return;
  259. if (no_piix_dma)
  260. hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
  261. }
  262. static void __devinit init_hwif_ich(ide_hwif_t *hwif)
  263. {
  264. init_hwif_piix(hwif);
  265. /* ICHx need to clear the BMDMA status for all interrupts */
  266. if (hwif->dma_base)
  267. hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
  268. }
  269. static const struct ide_port_ops piix_port_ops = {
  270. .set_pio_mode = piix_set_pio_mode,
  271. .set_dma_mode = piix_set_dma_mode,
  272. .cable_detect = piix_cable_detect,
  273. };
  274. #ifndef CONFIG_IA64
  275. #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
  276. #else
  277. #define IDE_HFLAGS_PIIX 0
  278. #endif
  279. #define DECLARE_PIIX_DEV(name_str, udma) \
  280. { \
  281. .name = name_str, \
  282. .init_hwif = init_hwif_piix, \
  283. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
  284. .port_ops = &piix_port_ops, \
  285. .host_flags = IDE_HFLAGS_PIIX, \
  286. .pio_mask = ATA_PIO4, \
  287. .swdma_mask = ATA_SWDMA2_ONLY, \
  288. .mwdma_mask = ATA_MWDMA12_ONLY, \
  289. .udma_mask = udma, \
  290. }
  291. #define DECLARE_ICH_DEV(name_str, udma) \
  292. { \
  293. .name = name_str, \
  294. .init_chipset = init_chipset_ich, \
  295. .init_hwif = init_hwif_ich, \
  296. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
  297. .port_ops = &piix_port_ops, \
  298. .host_flags = IDE_HFLAGS_PIIX, \
  299. .pio_mask = ATA_PIO4, \
  300. .swdma_mask = ATA_SWDMA2_ONLY, \
  301. .mwdma_mask = ATA_MWDMA12_ONLY, \
  302. .udma_mask = udma, \
  303. }
  304. static const struct ide_port_info piix_pci_info[] __devinitdata = {
  305. /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
  306. /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
  307. /* 2 */
  308. { /*
  309. * MPIIX actually has only a single IDE channel mapped to
  310. * the primary or secondary ports depending on the value
  311. * of the bit 14 of the IDETIM register at offset 0x6c
  312. */
  313. .name = "MPIIX",
  314. .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
  315. .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
  316. IDE_HFLAGS_PIIX,
  317. .pio_mask = ATA_PIO4,
  318. /* This is a painful system best to let it self tune for now */
  319. },
  320. /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
  321. /* 4 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
  322. /* 5 */ DECLARE_ICH_DEV("ICH0", ATA_UDMA2),
  323. /* 6 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
  324. /* 7 */ DECLARE_ICH_DEV("ICH", ATA_UDMA4),
  325. /* 8 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA4),
  326. /* 9 */ DECLARE_PIIX_DEV("PIIX4", ATA_UDMA2),
  327. /* 10 */ DECLARE_ICH_DEV("ICH2", ATA_UDMA5),
  328. /* 11 */ DECLARE_ICH_DEV("ICH2M", ATA_UDMA5),
  329. /* 12 */ DECLARE_ICH_DEV("ICH3M", ATA_UDMA5),
  330. /* 13 */ DECLARE_ICH_DEV("ICH3", ATA_UDMA5),
  331. /* 14 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
  332. /* 15 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
  333. /* 16 */ DECLARE_ICH_DEV("C-ICH", ATA_UDMA5),
  334. /* 17 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
  335. /* 18 */ DECLARE_ICH_DEV("ICH5-SATA", ATA_UDMA5),
  336. /* 19 */ DECLARE_ICH_DEV("ICH5", ATA_UDMA5),
  337. /* 20 */ DECLARE_ICH_DEV("ICH6", ATA_UDMA5),
  338. /* 21 */ DECLARE_ICH_DEV("ICH7", ATA_UDMA5),
  339. /* 22 */ DECLARE_ICH_DEV("ICH4", ATA_UDMA5),
  340. /* 23 */ DECLARE_ICH_DEV("ESB2", ATA_UDMA5),
  341. /* 24 */ DECLARE_ICH_DEV("ICH8M", ATA_UDMA5),
  342. };
  343. /**
  344. * piix_init_one - called when a PIIX is found
  345. * @dev: the piix device
  346. * @id: the matching pci id
  347. *
  348. * Called when the PCI registration layer (or the IDE initialization)
  349. * finds a device matching our IDE device tables.
  350. */
  351. static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  352. {
  353. return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
  354. }
  355. /**
  356. * piix_check_450nx - Check for problem 450NX setup
  357. *
  358. * Check for the present of 450NX errata #19 and errata #25. If
  359. * they are found, disable use of DMA IDE
  360. */
  361. static void __devinit piix_check_450nx(void)
  362. {
  363. struct pci_dev *pdev = NULL;
  364. u16 cfg;
  365. while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
  366. {
  367. /* Look for 450NX PXB. Check for problem configurations
  368. A PCI quirk checks bit 6 already */
  369. pci_read_config_word(pdev, 0x41, &cfg);
  370. /* Only on the original revision: IDE DMA can hang */
  371. if (pdev->revision == 0x00)
  372. no_piix_dma = 1;
  373. /* On all revisions below 5 PXB bus lock must be disabled for IDE */
  374. else if (cfg & (1<<14) && pdev->revision < 5)
  375. no_piix_dma = 2;
  376. }
  377. if(no_piix_dma)
  378. printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
  379. if(no_piix_dma == 2)
  380. printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
  381. }
  382. static const struct pci_device_id piix_pci_tbl[] = {
  383. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 0 },
  384. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
  385. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 2 },
  386. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 3 },
  387. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 4 },
  388. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 5 },
  389. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 6 },
  390. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 7 },
  391. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 8 },
  392. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 9 },
  393. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 10 },
  394. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 11 },
  395. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
  396. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
  397. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
  398. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
  399. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 16 },
  400. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
  401. #ifdef CONFIG_BLK_DEV_IDE_SATA
  402. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 18 },
  403. #endif
  404. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 19 },
  405. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 20 },
  406. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 21 },
  407. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 22 },
  408. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 23 },
  409. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 24 },
  410. { 0, },
  411. };
  412. MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
  413. static struct pci_driver driver = {
  414. .name = "PIIX_IDE",
  415. .id_table = piix_pci_tbl,
  416. .probe = piix_init_one,
  417. .remove = ide_pci_remove,
  418. };
  419. static int __init piix_ide_init(void)
  420. {
  421. piix_check_450nx();
  422. return ide_pci_register_driver(&driver);
  423. }
  424. static void __exit piix_ide_exit(void)
  425. {
  426. pci_unregister_driver(&driver);
  427. }
  428. module_init(piix_ide_init);
  429. module_exit(piix_ide_exit);
  430. MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
  431. MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
  432. MODULE_LICENSE("GPL");