intel_crt.c 17 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "drm_edid.h"
  34. #include "intel_drv.h"
  35. #include "i915_drm.h"
  36. #include "i915_drv.h"
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
  39. ADPA_CRT_HOTPLUG_WARMUP_10MS | \
  40. ADPA_CRT_HOTPLUG_SAMPLE_4S | \
  41. ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
  42. ADPA_CRT_HOTPLUG_VOLREF_325MV | \
  43. ADPA_CRT_HOTPLUG_ENABLE)
  44. struct intel_crt {
  45. struct intel_encoder base;
  46. bool force_hotplug_required;
  47. };
  48. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  49. {
  50. return container_of(intel_attached_encoder(connector),
  51. struct intel_crt, base);
  52. }
  53. static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  54. {
  55. struct drm_device *dev = encoder->dev;
  56. struct drm_i915_private *dev_priv = dev->dev_private;
  57. u32 temp, reg;
  58. if (HAS_PCH_SPLIT(dev))
  59. reg = PCH_ADPA;
  60. else
  61. reg = ADPA;
  62. temp = I915_READ(reg);
  63. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  64. temp &= ~ADPA_DAC_ENABLE;
  65. switch (mode) {
  66. case DRM_MODE_DPMS_ON:
  67. temp |= ADPA_DAC_ENABLE;
  68. break;
  69. case DRM_MODE_DPMS_STANDBY:
  70. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  71. break;
  72. case DRM_MODE_DPMS_SUSPEND:
  73. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  74. break;
  75. case DRM_MODE_DPMS_OFF:
  76. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  77. break;
  78. }
  79. I915_WRITE(reg, temp);
  80. }
  81. static int intel_crt_mode_valid(struct drm_connector *connector,
  82. struct drm_display_mode *mode)
  83. {
  84. struct drm_device *dev = connector->dev;
  85. int max_clock = 0;
  86. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  87. return MODE_NO_DBLESCAN;
  88. if (mode->clock < 25000)
  89. return MODE_CLOCK_LOW;
  90. if (IS_GEN2(dev))
  91. max_clock = 350000;
  92. else
  93. max_clock = 400000;
  94. if (mode->clock > max_clock)
  95. return MODE_CLOCK_HIGH;
  96. return MODE_OK;
  97. }
  98. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  99. struct drm_display_mode *mode,
  100. struct drm_display_mode *adjusted_mode)
  101. {
  102. return true;
  103. }
  104. static void intel_crt_mode_set(struct drm_encoder *encoder,
  105. struct drm_display_mode *mode,
  106. struct drm_display_mode *adjusted_mode)
  107. {
  108. struct drm_device *dev = encoder->dev;
  109. struct drm_crtc *crtc = encoder->crtc;
  110. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  111. struct drm_i915_private *dev_priv = dev->dev_private;
  112. int dpll_md_reg;
  113. u32 adpa, dpll_md;
  114. u32 adpa_reg;
  115. dpll_md_reg = DPLL_MD(intel_crtc->pipe);
  116. if (HAS_PCH_SPLIT(dev))
  117. adpa_reg = PCH_ADPA;
  118. else
  119. adpa_reg = ADPA;
  120. /*
  121. * Disable separate mode multiplier used when cloning SDVO to CRT
  122. * XXX this needs to be adjusted when we really are cloning
  123. */
  124. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  125. dpll_md = I915_READ(dpll_md_reg);
  126. I915_WRITE(dpll_md_reg,
  127. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  128. }
  129. adpa = ADPA_HOTPLUG_BITS;
  130. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  131. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  132. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  133. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  134. /* For CPT allow 3 pipe config, for others just use A or B */
  135. if (HAS_PCH_CPT(dev))
  136. adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  137. else if (intel_crtc->pipe == 0)
  138. adpa |= ADPA_PIPE_A_SELECT;
  139. else
  140. adpa |= ADPA_PIPE_B_SELECT;
  141. if (!HAS_PCH_SPLIT(dev))
  142. I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  143. I915_WRITE(adpa_reg, adpa);
  144. }
  145. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  146. {
  147. struct drm_device *dev = connector->dev;
  148. struct intel_crt *crt = intel_attached_crt(connector);
  149. struct drm_i915_private *dev_priv = dev->dev_private;
  150. u32 adpa;
  151. bool ret;
  152. /* The first time through, trigger an explicit detection cycle */
  153. if (crt->force_hotplug_required) {
  154. bool turn_off_dac = HAS_PCH_SPLIT(dev);
  155. u32 save_adpa;
  156. crt->force_hotplug_required = 0;
  157. save_adpa = adpa = I915_READ(PCH_ADPA);
  158. DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  159. adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  160. if (turn_off_dac)
  161. adpa &= ~ADPA_DAC_ENABLE;
  162. I915_WRITE(PCH_ADPA, adpa);
  163. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  164. 1000))
  165. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  166. if (turn_off_dac) {
  167. I915_WRITE(PCH_ADPA, save_adpa);
  168. POSTING_READ(PCH_ADPA);
  169. }
  170. }
  171. /* Check the status to see if both blue and green are on now */
  172. adpa = I915_READ(PCH_ADPA);
  173. if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  174. ret = true;
  175. else
  176. ret = false;
  177. DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  178. return ret;
  179. }
  180. /**
  181. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  182. *
  183. * Not for i915G/i915GM
  184. *
  185. * \return true if CRT is connected.
  186. * \return false if CRT is disconnected.
  187. */
  188. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  189. {
  190. struct drm_device *dev = connector->dev;
  191. struct drm_i915_private *dev_priv = dev->dev_private;
  192. u32 hotplug_en, orig, stat;
  193. bool ret = false;
  194. int i, tries = 0;
  195. if (HAS_PCH_SPLIT(dev))
  196. return intel_ironlake_crt_detect_hotplug(connector);
  197. /*
  198. * On 4 series desktop, CRT detect sequence need to be done twice
  199. * to get a reliable result.
  200. */
  201. if (IS_G4X(dev) && !IS_GM45(dev))
  202. tries = 2;
  203. else
  204. tries = 1;
  205. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  206. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  207. for (i = 0; i < tries ; i++) {
  208. /* turn on the FORCE_DETECT */
  209. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  210. /* wait for FORCE_DETECT to go off */
  211. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  212. CRT_HOTPLUG_FORCE_DETECT) == 0,
  213. 1000))
  214. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  215. }
  216. stat = I915_READ(PORT_HOTPLUG_STAT);
  217. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  218. ret = true;
  219. /* clear the interrupt we just generated, if any */
  220. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  221. /* and put the bits back */
  222. I915_WRITE(PORT_HOTPLUG_EN, orig);
  223. return ret;
  224. }
  225. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  226. {
  227. struct intel_crt *crt = intel_attached_crt(connector);
  228. struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  229. /* CRT should always be at 0, but check anyway */
  230. if (crt->base.type != INTEL_OUTPUT_ANALOG)
  231. return false;
  232. if (intel_ddc_probe(&crt->base, dev_priv->crt_ddc_pin)) {
  233. struct edid *edid;
  234. bool is_digital = false;
  235. struct i2c_adapter *i2c;
  236. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  237. edid = drm_get_edid(connector, i2c);
  238. /*
  239. * This may be a DVI-I connector with a shared DDC
  240. * link between analog and digital outputs, so we
  241. * have to check the EDID input spec of the attached device.
  242. *
  243. * On the other hand, what should we do if it is a broken EDID?
  244. */
  245. if (edid != NULL) {
  246. is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  247. connector->display_info.raw_edid = NULL;
  248. kfree(edid);
  249. }
  250. if (!is_digital) {
  251. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  252. return true;
  253. } else {
  254. DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  255. }
  256. }
  257. return false;
  258. }
  259. static enum drm_connector_status
  260. intel_crt_load_detect(struct intel_crt *crt)
  261. {
  262. struct drm_device *dev = crt->base.base.dev;
  263. struct drm_i915_private *dev_priv = dev->dev_private;
  264. uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  265. uint32_t save_bclrpat;
  266. uint32_t save_vtotal;
  267. uint32_t vtotal, vactive;
  268. uint32_t vsample;
  269. uint32_t vblank, vblank_start, vblank_end;
  270. uint32_t dsl;
  271. uint32_t bclrpat_reg;
  272. uint32_t vtotal_reg;
  273. uint32_t vblank_reg;
  274. uint32_t vsync_reg;
  275. uint32_t pipeconf_reg;
  276. uint32_t pipe_dsl_reg;
  277. uint8_t st00;
  278. enum drm_connector_status status;
  279. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  280. bclrpat_reg = BCLRPAT(pipe);
  281. vtotal_reg = VTOTAL(pipe);
  282. vblank_reg = VBLANK(pipe);
  283. vsync_reg = VSYNC(pipe);
  284. pipeconf_reg = PIPECONF(pipe);
  285. pipe_dsl_reg = PIPEDSL(pipe);
  286. save_bclrpat = I915_READ(bclrpat_reg);
  287. save_vtotal = I915_READ(vtotal_reg);
  288. vblank = I915_READ(vblank_reg);
  289. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  290. vactive = (save_vtotal & 0x7ff) + 1;
  291. vblank_start = (vblank & 0xfff) + 1;
  292. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  293. /* Set the border color to purple. */
  294. I915_WRITE(bclrpat_reg, 0x500050);
  295. if (!IS_GEN2(dev)) {
  296. uint32_t pipeconf = I915_READ(pipeconf_reg);
  297. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  298. POSTING_READ(pipeconf_reg);
  299. /* Wait for next Vblank to substitue
  300. * border color for Color info */
  301. intel_wait_for_vblank(dev, pipe);
  302. st00 = I915_READ8(VGA_MSR_WRITE);
  303. status = ((st00 & (1 << 4)) != 0) ?
  304. connector_status_connected :
  305. connector_status_disconnected;
  306. I915_WRITE(pipeconf_reg, pipeconf);
  307. } else {
  308. bool restore_vblank = false;
  309. int count, detect;
  310. /*
  311. * If there isn't any border, add some.
  312. * Yes, this will flicker
  313. */
  314. if (vblank_start <= vactive && vblank_end >= vtotal) {
  315. uint32_t vsync = I915_READ(vsync_reg);
  316. uint32_t vsync_start = (vsync & 0xffff) + 1;
  317. vblank_start = vsync_start;
  318. I915_WRITE(vblank_reg,
  319. (vblank_start - 1) |
  320. ((vblank_end - 1) << 16));
  321. restore_vblank = true;
  322. }
  323. /* sample in the vertical border, selecting the larger one */
  324. if (vblank_start - vactive >= vtotal - vblank_end)
  325. vsample = (vblank_start + vactive) >> 1;
  326. else
  327. vsample = (vtotal + vblank_end) >> 1;
  328. /*
  329. * Wait for the border to be displayed
  330. */
  331. while (I915_READ(pipe_dsl_reg) >= vactive)
  332. ;
  333. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  334. ;
  335. /*
  336. * Watch ST00 for an entire scanline
  337. */
  338. detect = 0;
  339. count = 0;
  340. do {
  341. count++;
  342. /* Read the ST00 VGA status register */
  343. st00 = I915_READ8(VGA_MSR_WRITE);
  344. if (st00 & (1 << 4))
  345. detect++;
  346. } while ((I915_READ(pipe_dsl_reg) == dsl));
  347. /* restore vblank if necessary */
  348. if (restore_vblank)
  349. I915_WRITE(vblank_reg, vblank);
  350. /*
  351. * If more than 3/4 of the scanline detected a monitor,
  352. * then it is assumed to be present. This works even on i830,
  353. * where there isn't any way to force the border color across
  354. * the screen
  355. */
  356. status = detect * 4 > count * 3 ?
  357. connector_status_connected :
  358. connector_status_disconnected;
  359. }
  360. /* Restore previous settings */
  361. I915_WRITE(bclrpat_reg, save_bclrpat);
  362. return status;
  363. }
  364. static enum drm_connector_status
  365. intel_crt_detect(struct drm_connector *connector, bool force)
  366. {
  367. struct drm_device *dev = connector->dev;
  368. struct intel_crt *crt = intel_attached_crt(connector);
  369. struct drm_crtc *crtc;
  370. enum drm_connector_status status;
  371. if (I915_HAS_HOTPLUG(dev)) {
  372. if (intel_crt_detect_hotplug(connector)) {
  373. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  374. return connector_status_connected;
  375. } else {
  376. DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  377. return connector_status_disconnected;
  378. }
  379. }
  380. if (intel_crt_detect_ddc(connector))
  381. return connector_status_connected;
  382. if (!force)
  383. return connector->status;
  384. /* for pre-945g platforms use load detect */
  385. crtc = crt->base.base.crtc;
  386. if (crtc && crtc->enabled) {
  387. status = intel_crt_load_detect(crt);
  388. } else {
  389. struct intel_load_detect_pipe tmp;
  390. if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
  391. &tmp)) {
  392. if (intel_crt_detect_ddc(connector))
  393. status = connector_status_connected;
  394. else
  395. status = intel_crt_load_detect(crt);
  396. intel_release_load_detect_pipe(&crt->base, connector,
  397. &tmp);
  398. } else
  399. status = connector_status_unknown;
  400. }
  401. return status;
  402. }
  403. static void intel_crt_destroy(struct drm_connector *connector)
  404. {
  405. drm_sysfs_connector_remove(connector);
  406. drm_connector_cleanup(connector);
  407. kfree(connector);
  408. }
  409. static int intel_crt_get_modes(struct drm_connector *connector)
  410. {
  411. struct drm_device *dev = connector->dev;
  412. struct drm_i915_private *dev_priv = dev->dev_private;
  413. int ret;
  414. struct i2c_adapter *i2c;
  415. i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  416. ret = intel_ddc_get_modes(connector, i2c);
  417. if (ret || !IS_G4X(dev))
  418. return ret;
  419. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  420. i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  421. return intel_ddc_get_modes(connector, i2c);
  422. }
  423. static int intel_crt_set_property(struct drm_connector *connector,
  424. struct drm_property *property,
  425. uint64_t value)
  426. {
  427. return 0;
  428. }
  429. static void intel_crt_reset(struct drm_connector *connector)
  430. {
  431. struct drm_device *dev = connector->dev;
  432. struct intel_crt *crt = intel_attached_crt(connector);
  433. if (HAS_PCH_SPLIT(dev))
  434. crt->force_hotplug_required = 1;
  435. }
  436. /*
  437. * Routines for controlling stuff on the analog port
  438. */
  439. static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
  440. .dpms = intel_crt_dpms,
  441. .mode_fixup = intel_crt_mode_fixup,
  442. .prepare = intel_encoder_prepare,
  443. .commit = intel_encoder_commit,
  444. .mode_set = intel_crt_mode_set,
  445. };
  446. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  447. .reset = intel_crt_reset,
  448. .dpms = drm_helper_connector_dpms,
  449. .detect = intel_crt_detect,
  450. .fill_modes = drm_helper_probe_single_connector_modes,
  451. .destroy = intel_crt_destroy,
  452. .set_property = intel_crt_set_property,
  453. };
  454. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  455. .mode_valid = intel_crt_mode_valid,
  456. .get_modes = intel_crt_get_modes,
  457. .best_encoder = intel_best_encoder,
  458. };
  459. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  460. .destroy = intel_encoder_destroy,
  461. };
  462. static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  463. {
  464. DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  465. return 1;
  466. }
  467. static const struct dmi_system_id intel_no_crt[] = {
  468. {
  469. .callback = intel_no_crt_dmi_callback,
  470. .ident = "ACER ZGB",
  471. .matches = {
  472. DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  473. DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  474. },
  475. },
  476. { }
  477. };
  478. void intel_crt_init(struct drm_device *dev)
  479. {
  480. struct drm_connector *connector;
  481. struct intel_crt *crt;
  482. struct intel_connector *intel_connector;
  483. struct drm_i915_private *dev_priv = dev->dev_private;
  484. /* Skip machines without VGA that falsely report hotplug events */
  485. if (dmi_check_system(intel_no_crt))
  486. return;
  487. crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  488. if (!crt)
  489. return;
  490. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  491. if (!intel_connector) {
  492. kfree(crt);
  493. return;
  494. }
  495. connector = &intel_connector->base;
  496. drm_connector_init(dev, &intel_connector->base,
  497. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  498. drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  499. DRM_MODE_ENCODER_DAC);
  500. intel_connector_attach_encoder(intel_connector, &crt->base);
  501. crt->base.type = INTEL_OUTPUT_ANALOG;
  502. crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
  503. 1 << INTEL_ANALOG_CLONE_BIT |
  504. 1 << INTEL_SDVO_LVDS_CLONE_BIT);
  505. crt->base.crtc_mask = (1 << 0) | (1 << 1);
  506. if (IS_GEN2(dev))
  507. connector->interlace_allowed = 0;
  508. else
  509. connector->interlace_allowed = 1;
  510. connector->doublescan_allowed = 0;
  511. drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
  512. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  513. drm_sysfs_connector_add(connector);
  514. if (I915_HAS_HOTPLUG(dev))
  515. connector->polled = DRM_CONNECTOR_POLL_HPD;
  516. else
  517. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  518. /*
  519. * Configure the automatic hotplug detection stuff
  520. */
  521. crt->force_hotplug_required = 0;
  522. if (HAS_PCH_SPLIT(dev)) {
  523. u32 adpa;
  524. adpa = I915_READ(PCH_ADPA);
  525. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  526. adpa |= ADPA_HOTPLUG_BITS;
  527. I915_WRITE(PCH_ADPA, adpa);
  528. POSTING_READ(PCH_ADPA);
  529. DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  530. crt->force_hotplug_required = 1;
  531. }
  532. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  533. }