common.c 23 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Common Codes for EXYNOS
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/bitops.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/io.h>
  17. #include <linux/device.h>
  18. #include <linux/gpio.h>
  19. #include <clocksource/samsung_pwm.h>
  20. #include <linux/sched.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/of.h>
  23. #include <linux/of_fdt.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/export.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/of_address.h>
  28. #include <linux/clocksource.h>
  29. #include <linux/clk-provider.h>
  30. #include <linux/irqchip/arm-gic.h>
  31. #include <linux/irqchip/chained_irq.h>
  32. #include <asm/proc-fns.h>
  33. #include <asm/exception.h>
  34. #include <asm/hardware/cache-l2x0.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/mach/irq.h>
  37. #include <asm/cacheflush.h>
  38. #include <mach/regs-irq.h>
  39. #include <mach/regs-pmu.h>
  40. #include <mach/regs-gpio.h>
  41. #include <mach/irqs.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/pm.h>
  45. #include <plat/sdhci.h>
  46. #include <plat/gpio-cfg.h>
  47. #include <plat/adc-core.h>
  48. #include <plat/fb-core.h>
  49. #include <plat/fimc-core.h>
  50. #include <plat/iic-core.h>
  51. #include <plat/tv-core.h>
  52. #include <plat/spi-core.h>
  53. #include <plat/regs-serial.h>
  54. #include "common.h"
  55. #define L2_AUX_VAL 0x7C470001
  56. #define L2_AUX_MASK 0xC200ffff
  57. static const char name_exynos4210[] = "EXYNOS4210";
  58. static const char name_exynos4212[] = "EXYNOS4212";
  59. static const char name_exynos4412[] = "EXYNOS4412";
  60. static const char name_exynos5250[] = "EXYNOS5250";
  61. static const char name_exynos5420[] = "EXYNOS5420";
  62. static const char name_exynos5440[] = "EXYNOS5440";
  63. static void exynos4_map_io(void);
  64. static void exynos5_map_io(void);
  65. static void exynos5440_map_io(void);
  66. static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  67. static int exynos_init(void);
  68. unsigned long xxti_f = 0, xusbxti_f = 0;
  69. static struct cpu_table cpu_ids[] __initdata = {
  70. {
  71. .idcode = EXYNOS4210_CPU_ID,
  72. .idmask = EXYNOS4_CPU_MASK,
  73. .map_io = exynos4_map_io,
  74. .init_uarts = exynos4_init_uarts,
  75. .init = exynos_init,
  76. .name = name_exynos4210,
  77. }, {
  78. .idcode = EXYNOS4212_CPU_ID,
  79. .idmask = EXYNOS4_CPU_MASK,
  80. .map_io = exynos4_map_io,
  81. .init_uarts = exynos4_init_uarts,
  82. .init = exynos_init,
  83. .name = name_exynos4212,
  84. }, {
  85. .idcode = EXYNOS4412_CPU_ID,
  86. .idmask = EXYNOS4_CPU_MASK,
  87. .map_io = exynos4_map_io,
  88. .init_uarts = exynos4_init_uarts,
  89. .init = exynos_init,
  90. .name = name_exynos4412,
  91. }, {
  92. .idcode = EXYNOS5250_SOC_ID,
  93. .idmask = EXYNOS5_SOC_MASK,
  94. .map_io = exynos5_map_io,
  95. .init = exynos_init,
  96. .name = name_exynos5250,
  97. }, {
  98. .idcode = EXYNOS5420_SOC_ID,
  99. .idmask = EXYNOS5_SOC_MASK,
  100. .map_io = exynos5_map_io,
  101. .init = exynos_init,
  102. .name = name_exynos5420,
  103. }, {
  104. .idcode = EXYNOS5440_SOC_ID,
  105. .idmask = EXYNOS5_SOC_MASK,
  106. .map_io = exynos5440_map_io,
  107. .init = exynos_init,
  108. .name = name_exynos5440,
  109. },
  110. };
  111. /* Initial IO mappings */
  112. static struct map_desc exynos_iodesc[] __initdata = {
  113. {
  114. .virtual = (unsigned long)S5P_VA_CHIPID,
  115. .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
  116. .length = SZ_4K,
  117. .type = MT_DEVICE,
  118. },
  119. };
  120. static struct map_desc exynos4_iodesc[] __initdata = {
  121. {
  122. .virtual = (unsigned long)S3C_VA_SYS,
  123. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  124. .length = SZ_64K,
  125. .type = MT_DEVICE,
  126. }, {
  127. .virtual = (unsigned long)S3C_VA_TIMER,
  128. .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
  129. .length = SZ_16K,
  130. .type = MT_DEVICE,
  131. }, {
  132. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  133. .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  134. .length = SZ_4K,
  135. .type = MT_DEVICE,
  136. }, {
  137. .virtual = (unsigned long)S5P_VA_SROMC,
  138. .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
  139. .length = SZ_4K,
  140. .type = MT_DEVICE,
  141. }, {
  142. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  143. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  144. .length = SZ_4K,
  145. .type = MT_DEVICE,
  146. }, {
  147. .virtual = (unsigned long)S5P_VA_PMU,
  148. .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
  149. .length = SZ_64K,
  150. .type = MT_DEVICE,
  151. }, {
  152. .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
  153. .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  154. .length = SZ_4K,
  155. .type = MT_DEVICE,
  156. }, {
  157. .virtual = (unsigned long)S5P_VA_GIC_CPU,
  158. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  159. .length = SZ_64K,
  160. .type = MT_DEVICE,
  161. }, {
  162. .virtual = (unsigned long)S5P_VA_GIC_DIST,
  163. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  164. .length = SZ_64K,
  165. .type = MT_DEVICE,
  166. }, {
  167. .virtual = (unsigned long)S3C_VA_UART,
  168. .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
  169. .length = SZ_512K,
  170. .type = MT_DEVICE,
  171. }, {
  172. .virtual = (unsigned long)S5P_VA_CMU,
  173. .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
  174. .length = SZ_128K,
  175. .type = MT_DEVICE,
  176. }, {
  177. .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
  178. .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  179. .length = SZ_8K,
  180. .type = MT_DEVICE,
  181. }, {
  182. .virtual = (unsigned long)S5P_VA_L2CC,
  183. .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
  184. .length = SZ_4K,
  185. .type = MT_DEVICE,
  186. }, {
  187. .virtual = (unsigned long)S5P_VA_DMC0,
  188. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
  189. .length = SZ_64K,
  190. .type = MT_DEVICE,
  191. }, {
  192. .virtual = (unsigned long)S5P_VA_DMC1,
  193. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
  194. .length = SZ_64K,
  195. .type = MT_DEVICE,
  196. }, {
  197. .virtual = (unsigned long)S3C_VA_USB_HSPHY,
  198. .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
  199. .length = SZ_4K,
  200. .type = MT_DEVICE,
  201. },
  202. };
  203. static struct map_desc exynos4_iodesc0[] __initdata = {
  204. {
  205. .virtual = (unsigned long)S5P_VA_SYSRAM,
  206. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
  207. .length = SZ_4K,
  208. .type = MT_DEVICE,
  209. },
  210. };
  211. static struct map_desc exynos4_iodesc1[] __initdata = {
  212. {
  213. .virtual = (unsigned long)S5P_VA_SYSRAM,
  214. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
  215. .length = SZ_4K,
  216. .type = MT_DEVICE,
  217. },
  218. };
  219. static struct map_desc exynos4210_iodesc[] __initdata = {
  220. {
  221. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  222. .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
  223. .length = SZ_4K,
  224. .type = MT_DEVICE,
  225. },
  226. };
  227. static struct map_desc exynos4x12_iodesc[] __initdata = {
  228. {
  229. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  230. .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
  231. .length = SZ_4K,
  232. .type = MT_DEVICE,
  233. },
  234. };
  235. static struct map_desc exynos5250_iodesc[] __initdata = {
  236. {
  237. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  238. .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
  239. .length = SZ_4K,
  240. .type = MT_DEVICE,
  241. },
  242. };
  243. static struct map_desc exynos5_iodesc[] __initdata = {
  244. {
  245. .virtual = (unsigned long)S3C_VA_SYS,
  246. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
  247. .length = SZ_64K,
  248. .type = MT_DEVICE,
  249. }, {
  250. .virtual = (unsigned long)S3C_VA_TIMER,
  251. .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
  252. .length = SZ_16K,
  253. .type = MT_DEVICE,
  254. }, {
  255. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  256. .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
  257. .length = SZ_4K,
  258. .type = MT_DEVICE,
  259. }, {
  260. .virtual = (unsigned long)S5P_VA_SROMC,
  261. .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
  262. .length = SZ_4K,
  263. .type = MT_DEVICE,
  264. }, {
  265. .virtual = (unsigned long)S5P_VA_SYSRAM,
  266. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
  267. .length = SZ_4K,
  268. .type = MT_DEVICE,
  269. }, {
  270. .virtual = (unsigned long)S5P_VA_CMU,
  271. .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
  272. .length = 144 * SZ_1K,
  273. .type = MT_DEVICE,
  274. }, {
  275. .virtual = (unsigned long)S5P_VA_PMU,
  276. .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
  277. .length = SZ_64K,
  278. .type = MT_DEVICE,
  279. }, {
  280. .virtual = (unsigned long)S3C_VA_UART,
  281. .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
  282. .length = SZ_512K,
  283. .type = MT_DEVICE,
  284. },
  285. };
  286. static struct map_desc exynos5440_iodesc0[] __initdata = {
  287. {
  288. .virtual = (unsigned long)S3C_VA_UART,
  289. .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
  290. .length = SZ_512K,
  291. .type = MT_DEVICE,
  292. },
  293. };
  294. static struct samsung_pwm_variant exynos4_pwm_variant = {
  295. .bits = 32,
  296. .div_base = 0,
  297. .has_tint_cstat = true,
  298. .tclk_mask = 0,
  299. };
  300. void exynos4_restart(char mode, const char *cmd)
  301. {
  302. __raw_writel(0x1, S5P_SWRESET);
  303. }
  304. void exynos5_restart(char mode, const char *cmd)
  305. {
  306. struct device_node *np;
  307. u32 val;
  308. void __iomem *addr;
  309. val = 0x1;
  310. addr = EXYNOS_SWRESET;
  311. if (of_machine_is_compatible("samsung,exynos5440")) {
  312. u32 status;
  313. np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
  314. addr = of_iomap(np, 0) + 0xbc;
  315. status = __raw_readl(addr);
  316. addr = of_iomap(np, 0) + 0xcc;
  317. val = __raw_readl(addr);
  318. val = (val & 0xffff0000) | (status & 0xffff);
  319. }
  320. __raw_writel(val, addr);
  321. }
  322. void __init exynos_init_late(void)
  323. {
  324. if (of_machine_is_compatible("samsung,exynos5440"))
  325. /* to be supported later */
  326. return;
  327. exynos_pm_late_initcall();
  328. }
  329. #ifdef CONFIG_OF
  330. int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  331. int depth, void *data)
  332. {
  333. struct map_desc iodesc;
  334. __be32 *reg;
  335. unsigned long len;
  336. if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
  337. !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
  338. return 0;
  339. reg = of_get_flat_dt_prop(node, "reg", &len);
  340. if (reg == NULL || len != (sizeof(unsigned long) * 2))
  341. return 0;
  342. iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
  343. iodesc.length = be32_to_cpu(reg[1]) - 1;
  344. iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
  345. iodesc.type = MT_DEVICE;
  346. iotable_init(&iodesc, 1);
  347. return 1;
  348. }
  349. #endif
  350. /*
  351. * exynos_map_io
  352. *
  353. * register the standard cpu IO areas
  354. */
  355. void __init exynos_init_io(struct map_desc *mach_desc, int size)
  356. {
  357. debug_ll_io_init();
  358. #ifdef CONFIG_OF
  359. if (initial_boot_params)
  360. of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
  361. else
  362. #endif
  363. iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
  364. if (mach_desc)
  365. iotable_init(mach_desc, size);
  366. /* detect cpu id and rev. */
  367. s5p_init_cpu(S5P_VA_CHIPID);
  368. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  369. }
  370. static void __init exynos4_map_io(void)
  371. {
  372. iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
  373. if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
  374. iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
  375. else
  376. iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
  377. if (soc_is_exynos4210())
  378. iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
  379. if (soc_is_exynos4212() || soc_is_exynos4412())
  380. iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
  381. /* initialize device information early */
  382. exynos4_default_sdhci0();
  383. exynos4_default_sdhci1();
  384. exynos4_default_sdhci2();
  385. exynos4_default_sdhci3();
  386. s3c_adc_setname("samsung-adc-v3");
  387. s3c_fimc_setname(0, "exynos4-fimc");
  388. s3c_fimc_setname(1, "exynos4-fimc");
  389. s3c_fimc_setname(2, "exynos4-fimc");
  390. s3c_fimc_setname(3, "exynos4-fimc");
  391. s3c_sdhci_setname(0, "exynos4-sdhci");
  392. s3c_sdhci_setname(1, "exynos4-sdhci");
  393. s3c_sdhci_setname(2, "exynos4-sdhci");
  394. s3c_sdhci_setname(3, "exynos4-sdhci");
  395. /* The I2C bus controllers are directly compatible with s3c2440 */
  396. s3c_i2c0_setname("s3c2440-i2c");
  397. s3c_i2c1_setname("s3c2440-i2c");
  398. s3c_i2c2_setname("s3c2440-i2c");
  399. s5p_fb_setname(0, "exynos4-fb");
  400. s5p_hdmi_setname("exynos4-hdmi");
  401. s3c64xx_spi_setname("exynos4210-spi");
  402. }
  403. static void __init exynos5_map_io(void)
  404. {
  405. iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
  406. if (soc_is_exynos5250())
  407. iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
  408. }
  409. static void __init exynos5440_map_io(void)
  410. {
  411. iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
  412. }
  413. void __init exynos_set_timer_source(u8 channels)
  414. {
  415. exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
  416. exynos4_pwm_variant.output_mask &= ~channels;
  417. }
  418. void __init exynos_init_time(void)
  419. {
  420. unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
  421. EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
  422. EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
  423. EXYNOS4_IRQ_TIMER4_VIC,
  424. };
  425. if (of_have_populated_dt()) {
  426. #ifdef CONFIG_OF
  427. of_clk_init(NULL);
  428. clocksource_of_init();
  429. #endif
  430. } else {
  431. /* todo: remove after migrating legacy E4 platforms to dt */
  432. #ifdef CONFIG_ARCH_EXYNOS4
  433. exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
  434. exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
  435. #endif
  436. #ifdef CONFIG_CLKSRC_SAMSUNG_PWM
  437. if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
  438. samsung_pwm_clocksource_init(S3C_VA_TIMER,
  439. timer_irqs, &exynos4_pwm_variant);
  440. else
  441. #endif
  442. mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
  443. EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
  444. }
  445. }
  446. static unsigned int max_combiner_nr(void)
  447. {
  448. if (soc_is_exynos5250())
  449. return EXYNOS5_MAX_COMBINER_NR;
  450. else if (soc_is_exynos4412())
  451. return EXYNOS4412_MAX_COMBINER_NR;
  452. else if (soc_is_exynos4212())
  453. return EXYNOS4212_MAX_COMBINER_NR;
  454. else
  455. return EXYNOS4210_MAX_COMBINER_NR;
  456. }
  457. void __init exynos4_init_irq(void)
  458. {
  459. unsigned int gic_bank_offset;
  460. gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
  461. if (!of_have_populated_dt())
  462. gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
  463. #ifdef CONFIG_OF
  464. else
  465. irqchip_init();
  466. #endif
  467. if (!of_have_populated_dt())
  468. combiner_init(S5P_VA_COMBINER_BASE, NULL,
  469. max_combiner_nr(), COMBINER_IRQ(0, 0));
  470. gic_arch_extn.irq_set_wake = s3c_irq_wake;
  471. }
  472. void __init exynos5_init_irq(void)
  473. {
  474. #ifdef CONFIG_OF
  475. irqchip_init();
  476. #endif
  477. gic_arch_extn.irq_set_wake = s3c_irq_wake;
  478. }
  479. struct bus_type exynos_subsys = {
  480. .name = "exynos-core",
  481. .dev_name = "exynos-core",
  482. };
  483. static struct device exynos4_dev = {
  484. .bus = &exynos_subsys,
  485. };
  486. static int __init exynos_core_init(void)
  487. {
  488. return subsys_system_register(&exynos_subsys, NULL);
  489. }
  490. core_initcall(exynos_core_init);
  491. #ifdef CONFIG_CACHE_L2X0
  492. static int __init exynos4_l2x0_cache_init(void)
  493. {
  494. int ret;
  495. if (soc_is_exynos5250() || soc_is_exynos5440())
  496. return 0;
  497. ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
  498. if (!ret) {
  499. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  500. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  501. return 0;
  502. }
  503. if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
  504. l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
  505. /* TAG, Data Latency Control: 2 cycles */
  506. l2x0_saved_regs.tag_latency = 0x110;
  507. if (soc_is_exynos4212() || soc_is_exynos4412())
  508. l2x0_saved_regs.data_latency = 0x120;
  509. else
  510. l2x0_saved_regs.data_latency = 0x110;
  511. l2x0_saved_regs.prefetch_ctrl = 0x30000007;
  512. l2x0_saved_regs.pwr_ctrl =
  513. (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
  514. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  515. __raw_writel(l2x0_saved_regs.tag_latency,
  516. S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
  517. __raw_writel(l2x0_saved_regs.data_latency,
  518. S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
  519. /* L2X0 Prefetch Control */
  520. __raw_writel(l2x0_saved_regs.prefetch_ctrl,
  521. S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
  522. /* L2X0 Power Control */
  523. __raw_writel(l2x0_saved_regs.pwr_ctrl,
  524. S5P_VA_L2CC + L2X0_POWER_CTRL);
  525. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  526. clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
  527. }
  528. l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
  529. return 0;
  530. }
  531. early_initcall(exynos4_l2x0_cache_init);
  532. #endif
  533. static int __init exynos_init(void)
  534. {
  535. printk(KERN_INFO "EXYNOS: Initializing architecture\n");
  536. return device_register(&exynos4_dev);
  537. }
  538. /* uart registration process */
  539. static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  540. {
  541. struct s3c2410_uartcfg *tcfg = cfg;
  542. u32 ucnt;
  543. for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
  544. tcfg->has_fracval = 1;
  545. s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
  546. }
  547. static void __iomem *exynos_eint_base;
  548. static DEFINE_SPINLOCK(eint_lock);
  549. static unsigned int eint0_15_data[16];
  550. static inline int exynos4_irq_to_gpio(unsigned int irq)
  551. {
  552. if (irq < IRQ_EINT(0))
  553. return -EINVAL;
  554. irq -= IRQ_EINT(0);
  555. if (irq < 8)
  556. return EXYNOS4_GPX0(irq);
  557. irq -= 8;
  558. if (irq < 8)
  559. return EXYNOS4_GPX1(irq);
  560. irq -= 8;
  561. if (irq < 8)
  562. return EXYNOS4_GPX2(irq);
  563. irq -= 8;
  564. if (irq < 8)
  565. return EXYNOS4_GPX3(irq);
  566. return -EINVAL;
  567. }
  568. static inline int exynos5_irq_to_gpio(unsigned int irq)
  569. {
  570. if (irq < IRQ_EINT(0))
  571. return -EINVAL;
  572. irq -= IRQ_EINT(0);
  573. if (irq < 8)
  574. return EXYNOS5_GPX0(irq);
  575. irq -= 8;
  576. if (irq < 8)
  577. return EXYNOS5_GPX1(irq);
  578. irq -= 8;
  579. if (irq < 8)
  580. return EXYNOS5_GPX2(irq);
  581. irq -= 8;
  582. if (irq < 8)
  583. return EXYNOS5_GPX3(irq);
  584. return -EINVAL;
  585. }
  586. static unsigned int exynos4_eint0_15_src_int[16] = {
  587. EXYNOS4_IRQ_EINT0,
  588. EXYNOS4_IRQ_EINT1,
  589. EXYNOS4_IRQ_EINT2,
  590. EXYNOS4_IRQ_EINT3,
  591. EXYNOS4_IRQ_EINT4,
  592. EXYNOS4_IRQ_EINT5,
  593. EXYNOS4_IRQ_EINT6,
  594. EXYNOS4_IRQ_EINT7,
  595. EXYNOS4_IRQ_EINT8,
  596. EXYNOS4_IRQ_EINT9,
  597. EXYNOS4_IRQ_EINT10,
  598. EXYNOS4_IRQ_EINT11,
  599. EXYNOS4_IRQ_EINT12,
  600. EXYNOS4_IRQ_EINT13,
  601. EXYNOS4_IRQ_EINT14,
  602. EXYNOS4_IRQ_EINT15,
  603. };
  604. static unsigned int exynos5_eint0_15_src_int[16] = {
  605. EXYNOS5_IRQ_EINT0,
  606. EXYNOS5_IRQ_EINT1,
  607. EXYNOS5_IRQ_EINT2,
  608. EXYNOS5_IRQ_EINT3,
  609. EXYNOS5_IRQ_EINT4,
  610. EXYNOS5_IRQ_EINT5,
  611. EXYNOS5_IRQ_EINT6,
  612. EXYNOS5_IRQ_EINT7,
  613. EXYNOS5_IRQ_EINT8,
  614. EXYNOS5_IRQ_EINT9,
  615. EXYNOS5_IRQ_EINT10,
  616. EXYNOS5_IRQ_EINT11,
  617. EXYNOS5_IRQ_EINT12,
  618. EXYNOS5_IRQ_EINT13,
  619. EXYNOS5_IRQ_EINT14,
  620. EXYNOS5_IRQ_EINT15,
  621. };
  622. static inline void exynos_irq_eint_mask(struct irq_data *data)
  623. {
  624. u32 mask;
  625. spin_lock(&eint_lock);
  626. mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
  627. mask |= EINT_OFFSET_BIT(data->irq);
  628. __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
  629. spin_unlock(&eint_lock);
  630. }
  631. static void exynos_irq_eint_unmask(struct irq_data *data)
  632. {
  633. u32 mask;
  634. spin_lock(&eint_lock);
  635. mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
  636. mask &= ~(EINT_OFFSET_BIT(data->irq));
  637. __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
  638. spin_unlock(&eint_lock);
  639. }
  640. static inline void exynos_irq_eint_ack(struct irq_data *data)
  641. {
  642. __raw_writel(EINT_OFFSET_BIT(data->irq),
  643. EINT_PEND(exynos_eint_base, data->irq));
  644. }
  645. static void exynos_irq_eint_maskack(struct irq_data *data)
  646. {
  647. exynos_irq_eint_mask(data);
  648. exynos_irq_eint_ack(data);
  649. }
  650. static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
  651. {
  652. int offs = EINT_OFFSET(data->irq);
  653. int shift;
  654. u32 ctrl, mask;
  655. u32 newvalue = 0;
  656. switch (type) {
  657. case IRQ_TYPE_EDGE_RISING:
  658. newvalue = S5P_IRQ_TYPE_EDGE_RISING;
  659. break;
  660. case IRQ_TYPE_EDGE_FALLING:
  661. newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
  662. break;
  663. case IRQ_TYPE_EDGE_BOTH:
  664. newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
  665. break;
  666. case IRQ_TYPE_LEVEL_LOW:
  667. newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
  668. break;
  669. case IRQ_TYPE_LEVEL_HIGH:
  670. newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
  671. break;
  672. default:
  673. printk(KERN_ERR "No such irq type %d", type);
  674. return -EINVAL;
  675. }
  676. shift = (offs & 0x7) * 4;
  677. mask = 0x7 << shift;
  678. spin_lock(&eint_lock);
  679. ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
  680. ctrl &= ~mask;
  681. ctrl |= newvalue << shift;
  682. __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
  683. spin_unlock(&eint_lock);
  684. if (soc_is_exynos5250())
  685. s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
  686. else
  687. s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
  688. return 0;
  689. }
  690. static struct irq_chip exynos_irq_eint = {
  691. .name = "exynos-eint",
  692. .irq_mask = exynos_irq_eint_mask,
  693. .irq_unmask = exynos_irq_eint_unmask,
  694. .irq_mask_ack = exynos_irq_eint_maskack,
  695. .irq_ack = exynos_irq_eint_ack,
  696. .irq_set_type = exynos_irq_eint_set_type,
  697. #ifdef CONFIG_PM
  698. .irq_set_wake = s3c_irqext_wake,
  699. #endif
  700. };
  701. /*
  702. * exynos4_irq_demux_eint
  703. *
  704. * This function demuxes the IRQ from from EINTs 16 to 31.
  705. * It is designed to be inlined into the specific handler
  706. * s5p_irq_demux_eintX_Y.
  707. *
  708. * Each EINT pend/mask registers handle eight of them.
  709. */
  710. static inline void exynos_irq_demux_eint(unsigned int start)
  711. {
  712. unsigned int irq;
  713. u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
  714. u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
  715. status &= ~mask;
  716. status &= 0xff;
  717. while (status) {
  718. irq = fls(status) - 1;
  719. generic_handle_irq(irq + start);
  720. status &= ~(1 << irq);
  721. }
  722. }
  723. static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
  724. {
  725. struct irq_chip *chip = irq_get_chip(irq);
  726. chained_irq_enter(chip, desc);
  727. exynos_irq_demux_eint(IRQ_EINT(16));
  728. exynos_irq_demux_eint(IRQ_EINT(24));
  729. chained_irq_exit(chip, desc);
  730. }
  731. static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
  732. {
  733. u32 *irq_data = irq_get_handler_data(irq);
  734. struct irq_chip *chip = irq_get_chip(irq);
  735. chained_irq_enter(chip, desc);
  736. generic_handle_irq(*irq_data);
  737. chained_irq_exit(chip, desc);
  738. }
  739. static int __init exynos_init_irq_eint(void)
  740. {
  741. int irq;
  742. #ifdef CONFIG_PINCTRL_SAMSUNG
  743. /*
  744. * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
  745. * functionality along with support for external gpio and wakeup
  746. * interrupts. If the samsung pinctrl driver is enabled and includes
  747. * the wakeup interrupt support, then the setting up external wakeup
  748. * interrupts here can be skipped. This check here is temporary to
  749. * allow exynos4 platforms that do not use Samsung pinctrl driver to
  750. * co-exist with platforms that do. When all of the Samsung Exynos4
  751. * platforms switch over to using the pinctrl driver, the wakeup
  752. * interrupt support code here can be completely removed.
  753. */
  754. static const struct of_device_id exynos_pinctrl_ids[] = {
  755. { .compatible = "samsung,exynos4210-pinctrl", },
  756. { .compatible = "samsung,exynos4x12-pinctrl", },
  757. { .compatible = "samsung,exynos5250-pinctrl", },
  758. };
  759. struct device_node *pctrl_np, *wkup_np;
  760. const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
  761. for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
  762. if (of_device_is_available(pctrl_np)) {
  763. wkup_np = of_find_compatible_node(pctrl_np, NULL,
  764. wkup_compat);
  765. if (wkup_np)
  766. return -ENODEV;
  767. }
  768. }
  769. #endif
  770. if (soc_is_exynos5440())
  771. return 0;
  772. if (soc_is_exynos5250())
  773. exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
  774. else
  775. exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
  776. if (exynos_eint_base == NULL) {
  777. pr_err("unable to ioremap for EINT base address\n");
  778. return -ENOMEM;
  779. }
  780. for (irq = 0 ; irq <= 31 ; irq++) {
  781. irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
  782. handle_level_irq);
  783. set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
  784. }
  785. irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
  786. for (irq = 0 ; irq <= 15 ; irq++) {
  787. eint0_15_data[irq] = IRQ_EINT(irq);
  788. if (soc_is_exynos5250()) {
  789. irq_set_handler_data(exynos5_eint0_15_src_int[irq],
  790. &eint0_15_data[irq]);
  791. irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
  792. exynos_irq_eint0_15);
  793. } else {
  794. irq_set_handler_data(exynos4_eint0_15_src_int[irq],
  795. &eint0_15_data[irq]);
  796. irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
  797. exynos_irq_eint0_15);
  798. }
  799. }
  800. return 0;
  801. }
  802. arch_initcall(exynos_init_irq_eint);
  803. static struct resource exynos4_pmu_resource[] = {
  804. DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
  805. DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
  806. #if defined(CONFIG_SOC_EXYNOS4412)
  807. DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
  808. DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
  809. #endif
  810. };
  811. static struct platform_device exynos4_device_pmu = {
  812. .name = "arm-pmu",
  813. .num_resources = ARRAY_SIZE(exynos4_pmu_resource),
  814. .resource = exynos4_pmu_resource,
  815. };
  816. static int __init exynos_armpmu_init(void)
  817. {
  818. if (!of_have_populated_dt()) {
  819. if (soc_is_exynos4210() || soc_is_exynos4212())
  820. exynos4_device_pmu.num_resources = 2;
  821. platform_device_register(&exynos4_device_pmu);
  822. }
  823. return 0;
  824. }
  825. arch_initcall(exynos_armpmu_init);