am33xx.dtsi 5.0 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,am33xx";
  13. aliases {
  14. serial0 = &uart1;
  15. serial1 = &uart2;
  16. serial2 = &uart3;
  17. serial3 = &uart4;
  18. serial4 = &uart5;
  19. serial5 = &uart6;
  20. };
  21. cpus {
  22. cpu@0 {
  23. compatible = "arm,cortex-a8";
  24. /*
  25. * To consider voltage drop between PMIC and SoC,
  26. * tolerance value is reduced to 2% from 4% and
  27. * voltage value is increased as a precaution.
  28. */
  29. operating-points = <
  30. /* kHz uV */
  31. 720000 1285000
  32. 600000 1225000
  33. 500000 1125000
  34. 275000 1125000
  35. >;
  36. voltage-tolerance = <2>; /* 2 percentage */
  37. clock-latency = <300000>; /* From omap-cpufreq driver */
  38. };
  39. };
  40. /*
  41. * The soc node represents the soc top level view. It is uses for IPs
  42. * that are not memory mapped in the MPU view or for the MPU itself.
  43. */
  44. soc {
  45. compatible = "ti,omap-infra";
  46. mpu {
  47. compatible = "ti,omap3-mpu";
  48. ti,hwmods = "mpu";
  49. };
  50. };
  51. /*
  52. * XXX: Use a flat representation of the AM33XX interconnect.
  53. * The real AM33XX interconnect network is quite complex.Since
  54. * that will not bring real advantage to represent that in DT
  55. * for the moment, just use a fake OCP bus entry to represent
  56. * the whole bus hierarchy.
  57. */
  58. ocp {
  59. compatible = "simple-bus";
  60. #address-cells = <1>;
  61. #size-cells = <1>;
  62. ranges;
  63. ti,hwmods = "l3_main";
  64. intc: interrupt-controller@48200000 {
  65. compatible = "ti,omap2-intc";
  66. interrupt-controller;
  67. #interrupt-cells = <1>;
  68. ti,intc-size = <128>;
  69. reg = <0x48200000 0x1000>;
  70. };
  71. gpio1: gpio@44e07000 {
  72. compatible = "ti,omap4-gpio";
  73. ti,hwmods = "gpio1";
  74. gpio-controller;
  75. #gpio-cells = <2>;
  76. interrupt-controller;
  77. #interrupt-cells = <1>;
  78. reg = <0x44e07000 0x1000>;
  79. interrupt-parent = <&intc>;
  80. interrupts = <96>;
  81. };
  82. gpio2: gpio@4804c000 {
  83. compatible = "ti,omap4-gpio";
  84. ti,hwmods = "gpio2";
  85. gpio-controller;
  86. #gpio-cells = <2>;
  87. interrupt-controller;
  88. #interrupt-cells = <1>;
  89. reg = <0x4804c000 0x1000>;
  90. interrupt-parent = <&intc>;
  91. interrupts = <98>;
  92. };
  93. gpio3: gpio@481ac000 {
  94. compatible = "ti,omap4-gpio";
  95. ti,hwmods = "gpio3";
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. interrupt-controller;
  99. #interrupt-cells = <1>;
  100. reg = <0x481ac000 0x1000>;
  101. interrupt-parent = <&intc>;
  102. interrupts = <32>;
  103. };
  104. gpio4: gpio@481ae000 {
  105. compatible = "ti,omap4-gpio";
  106. ti,hwmods = "gpio4";
  107. gpio-controller;
  108. #gpio-cells = <2>;
  109. interrupt-controller;
  110. #interrupt-cells = <1>;
  111. reg = <0x481ae000 0x1000>;
  112. interrupt-parent = <&intc>;
  113. interrupts = <62>;
  114. };
  115. uart1: serial@44e09000 {
  116. compatible = "ti,omap3-uart";
  117. ti,hwmods = "uart1";
  118. clock-frequency = <48000000>;
  119. reg = <0x44e09000 0x2000>;
  120. interrupt-parent = <&intc>;
  121. interrupts = <72>;
  122. status = "disabled";
  123. };
  124. uart2: serial@48022000 {
  125. compatible = "ti,omap3-uart";
  126. ti,hwmods = "uart2";
  127. clock-frequency = <48000000>;
  128. reg = <0x48022000 0x2000>;
  129. interrupt-parent = <&intc>;
  130. interrupts = <73>;
  131. status = "disabled";
  132. };
  133. uart3: serial@48024000 {
  134. compatible = "ti,omap3-uart";
  135. ti,hwmods = "uart3";
  136. clock-frequency = <48000000>;
  137. reg = <0x48024000 0x2000>;
  138. interrupt-parent = <&intc>;
  139. interrupts = <74>;
  140. status = "disabled";
  141. };
  142. uart4: serial@481a6000 {
  143. compatible = "ti,omap3-uart";
  144. ti,hwmods = "uart4";
  145. clock-frequency = <48000000>;
  146. reg = <0x481a6000 0x2000>;
  147. interrupt-parent = <&intc>;
  148. interrupts = <44>;
  149. status = "disabled";
  150. };
  151. uart5: serial@481a8000 {
  152. compatible = "ti,omap3-uart";
  153. ti,hwmods = "uart5";
  154. clock-frequency = <48000000>;
  155. reg = <0x481a8000 0x2000>;
  156. interrupt-parent = <&intc>;
  157. interrupts = <45>;
  158. status = "disabled";
  159. };
  160. uart6: serial@481aa000 {
  161. compatible = "ti,omap3-uart";
  162. ti,hwmods = "uart6";
  163. clock-frequency = <48000000>;
  164. reg = <0x481aa000 0x2000>;
  165. interrupt-parent = <&intc>;
  166. interrupts = <46>;
  167. status = "disabled";
  168. };
  169. i2c1: i2c@44e0b000 {
  170. compatible = "ti,omap4-i2c";
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. ti,hwmods = "i2c1";
  174. reg = <0x44e0b000 0x1000>;
  175. interrupt-parent = <&intc>;
  176. interrupts = <70>;
  177. status = "disabled";
  178. };
  179. i2c2: i2c@4802a000 {
  180. compatible = "ti,omap4-i2c";
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. ti,hwmods = "i2c2";
  184. reg = <0x4802a000 0x1000>;
  185. interrupt-parent = <&intc>;
  186. interrupts = <71>;
  187. status = "disabled";
  188. };
  189. i2c3: i2c@4819c000 {
  190. compatible = "ti,omap4-i2c";
  191. #address-cells = <1>;
  192. #size-cells = <0>;
  193. ti,hwmods = "i2c3";
  194. reg = <0x4819c000 0x1000>;
  195. interrupt-parent = <&intc>;
  196. interrupts = <30>;
  197. status = "disabled";
  198. };
  199. wdt2: wdt@44e35000 {
  200. compatible = "ti,omap3-wdt";
  201. ti,hwmods = "wd_timer2";
  202. reg = <0x44e35000 0x1000>;
  203. interrupt-parent = <&intc>;
  204. interrupts = <91>;
  205. };
  206. };
  207. };