patch_hdmi.c 93 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10. *
  11. * Authors:
  12. * Wu Fengguang <wfg@linux.intel.com>
  13. *
  14. * Maintained by:
  15. * Wu Fengguang <wfg@linux.intel.com>
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the Free
  19. * Software Foundation; either version 2 of the License, or (at your option)
  20. * any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful, but
  23. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  25. * for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software Foundation,
  29. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30. */
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/slab.h>
  34. #include <linux/module.h>
  35. #include <sound/core.h>
  36. #include <sound/jack.h>
  37. #include <sound/asoundef.h>
  38. #include <sound/tlv.h>
  39. #include "hda_codec.h"
  40. #include "hda_local.h"
  41. #include "hda_jack.h"
  42. static bool static_hdmi_pcm;
  43. module_param(static_hdmi_pcm, bool, 0644);
  44. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  45. #define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
  46. #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
  47. struct hdmi_spec_per_cvt {
  48. hda_nid_t cvt_nid;
  49. int assigned;
  50. unsigned int channels_min;
  51. unsigned int channels_max;
  52. u32 rates;
  53. u64 formats;
  54. unsigned int maxbps;
  55. };
  56. /* max. connections to a widget */
  57. #define HDA_MAX_CONNECTIONS 32
  58. struct hdmi_spec_per_pin {
  59. hda_nid_t pin_nid;
  60. int num_mux_nids;
  61. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  62. hda_nid_t cvt_nid;
  63. struct hda_codec *codec;
  64. struct hdmi_eld sink_eld;
  65. struct mutex lock;
  66. struct delayed_work work;
  67. struct snd_kcontrol *eld_ctl;
  68. int repoll_count;
  69. bool setup; /* the stream has been set up by prepare callback */
  70. int channels; /* current number of channels */
  71. bool non_pcm;
  72. bool chmap_set; /* channel-map override by ALSA API? */
  73. unsigned char chmap[8]; /* ALSA API channel-map */
  74. char pcm_name[8]; /* filled in build_pcm callbacks */
  75. #ifdef CONFIG_PROC_FS
  76. struct snd_info_entry *proc_entry;
  77. #endif
  78. };
  79. struct cea_channel_speaker_allocation;
  80. /* operations used by generic code that can be overridden by patches */
  81. struct hdmi_ops {
  82. int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
  83. unsigned char *buf, int *eld_size);
  84. /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
  85. int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
  86. int asp_slot);
  87. int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
  88. int asp_slot, int channel);
  89. void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
  90. int ca, int active_channels, int conn_type);
  91. /* enable/disable HBR (HD passthrough) */
  92. int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
  93. int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
  94. hda_nid_t pin_nid, u32 stream_tag, int format);
  95. /* Helpers for producing the channel map TLVs. These can be overridden
  96. * for devices that have non-standard mapping requirements. */
  97. int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
  98. int channels);
  99. void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
  100. unsigned int *chmap, int channels);
  101. /* check that the user-given chmap is supported */
  102. int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
  103. };
  104. struct hdmi_spec {
  105. int num_cvts;
  106. struct snd_array cvts; /* struct hdmi_spec_per_cvt */
  107. hda_nid_t cvt_nids[4]; /* only for haswell fix */
  108. int num_pins;
  109. struct snd_array pins; /* struct hdmi_spec_per_pin */
  110. struct snd_array pcm_rec; /* struct hda_pcm */
  111. unsigned int channels_max; /* max over all cvts */
  112. struct hdmi_eld temp_eld;
  113. struct hdmi_ops ops;
  114. /*
  115. * Non-generic VIA/NVIDIA specific
  116. */
  117. struct hda_multi_out multiout;
  118. struct hda_pcm_stream pcm_playback;
  119. };
  120. struct hdmi_audio_infoframe {
  121. u8 type; /* 0x84 */
  122. u8 ver; /* 0x01 */
  123. u8 len; /* 0x0a */
  124. u8 checksum;
  125. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  126. u8 SS01_SF24;
  127. u8 CXT04;
  128. u8 CA;
  129. u8 LFEPBL01_LSV36_DM_INH7;
  130. };
  131. struct dp_audio_infoframe {
  132. u8 type; /* 0x84 */
  133. u8 len; /* 0x1b */
  134. u8 ver; /* 0x11 << 2 */
  135. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  136. u8 SS01_SF24;
  137. u8 CXT04;
  138. u8 CA;
  139. u8 LFEPBL01_LSV36_DM_INH7;
  140. };
  141. union audio_infoframe {
  142. struct hdmi_audio_infoframe hdmi;
  143. struct dp_audio_infoframe dp;
  144. u8 bytes[0];
  145. };
  146. /*
  147. * CEA speaker placement:
  148. *
  149. * FLH FCH FRH
  150. * FLW FL FLC FC FRC FR FRW
  151. *
  152. * LFE
  153. * TC
  154. *
  155. * RL RLC RC RRC RR
  156. *
  157. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  158. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  159. */
  160. enum cea_speaker_placement {
  161. FL = (1 << 0), /* Front Left */
  162. FC = (1 << 1), /* Front Center */
  163. FR = (1 << 2), /* Front Right */
  164. FLC = (1 << 3), /* Front Left Center */
  165. FRC = (1 << 4), /* Front Right Center */
  166. RL = (1 << 5), /* Rear Left */
  167. RC = (1 << 6), /* Rear Center */
  168. RR = (1 << 7), /* Rear Right */
  169. RLC = (1 << 8), /* Rear Left Center */
  170. RRC = (1 << 9), /* Rear Right Center */
  171. LFE = (1 << 10), /* Low Frequency Effect */
  172. FLW = (1 << 11), /* Front Left Wide */
  173. FRW = (1 << 12), /* Front Right Wide */
  174. FLH = (1 << 13), /* Front Left High */
  175. FCH = (1 << 14), /* Front Center High */
  176. FRH = (1 << 15), /* Front Right High */
  177. TC = (1 << 16), /* Top Center */
  178. };
  179. /*
  180. * ELD SA bits in the CEA Speaker Allocation data block
  181. */
  182. static int eld_speaker_allocation_bits[] = {
  183. [0] = FL | FR,
  184. [1] = LFE,
  185. [2] = FC,
  186. [3] = RL | RR,
  187. [4] = RC,
  188. [5] = FLC | FRC,
  189. [6] = RLC | RRC,
  190. /* the following are not defined in ELD yet */
  191. [7] = FLW | FRW,
  192. [8] = FLH | FRH,
  193. [9] = TC,
  194. [10] = FCH,
  195. };
  196. struct cea_channel_speaker_allocation {
  197. int ca_index;
  198. int speakers[8];
  199. /* derived values, just for convenience */
  200. int channels;
  201. int spk_mask;
  202. };
  203. /*
  204. * ALSA sequence is:
  205. *
  206. * surround40 surround41 surround50 surround51 surround71
  207. * ch0 front left = = = =
  208. * ch1 front right = = = =
  209. * ch2 rear left = = = =
  210. * ch3 rear right = = = =
  211. * ch4 LFE center center center
  212. * ch5 LFE LFE
  213. * ch6 side left
  214. * ch7 side right
  215. *
  216. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  217. */
  218. static int hdmi_channel_mapping[0x32][8] = {
  219. /* stereo */
  220. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  221. /* 2.1 */
  222. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  223. /* Dolby Surround */
  224. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  225. /* surround40 */
  226. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  227. /* 4ch */
  228. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  229. /* surround41 */
  230. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  231. /* surround50 */
  232. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  233. /* surround51 */
  234. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  235. /* 7.1 */
  236. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  237. };
  238. /*
  239. * This is an ordered list!
  240. *
  241. * The preceding ones have better chances to be selected by
  242. * hdmi_channel_allocation().
  243. */
  244. static struct cea_channel_speaker_allocation channel_allocations[] = {
  245. /* channel: 7 6 5 4 3 2 1 0 */
  246. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  247. /* 2.1 */
  248. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  249. /* Dolby Surround */
  250. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  251. /* surround40 */
  252. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  253. /* surround41 */
  254. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  255. /* surround50 */
  256. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  257. /* surround51 */
  258. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  259. /* 6.1 */
  260. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  261. /* surround71 */
  262. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  263. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  264. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  265. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  266. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  267. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  268. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  269. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  270. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  271. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  272. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  273. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  274. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  275. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  276. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  277. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  278. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  279. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  280. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  281. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  282. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  283. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  284. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  285. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  286. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  287. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  288. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  289. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  290. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  291. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  292. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  293. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  294. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  295. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  296. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  297. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  298. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  299. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  300. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  301. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  302. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  303. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  304. };
  305. /*
  306. * HDMI routines
  307. */
  308. #define get_pin(spec, idx) \
  309. ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
  310. #define get_cvt(spec, idx) \
  311. ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
  312. #define get_pcm_rec(spec, idx) \
  313. ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
  314. static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
  315. {
  316. int pin_idx;
  317. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  318. if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
  319. return pin_idx;
  320. snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
  321. return -EINVAL;
  322. }
  323. static int hinfo_to_pin_index(struct hdmi_spec *spec,
  324. struct hda_pcm_stream *hinfo)
  325. {
  326. int pin_idx;
  327. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  328. if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
  329. return pin_idx;
  330. snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
  331. return -EINVAL;
  332. }
  333. static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
  334. {
  335. int cvt_idx;
  336. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  337. if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
  338. return cvt_idx;
  339. snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
  340. return -EINVAL;
  341. }
  342. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  343. struct snd_ctl_elem_info *uinfo)
  344. {
  345. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  346. struct hdmi_spec *spec = codec->spec;
  347. struct hdmi_spec_per_pin *per_pin;
  348. struct hdmi_eld *eld;
  349. int pin_idx;
  350. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  351. pin_idx = kcontrol->private_value;
  352. per_pin = get_pin(spec, pin_idx);
  353. eld = &per_pin->sink_eld;
  354. mutex_lock(&per_pin->lock);
  355. uinfo->count = eld->eld_valid ? eld->eld_size : 0;
  356. mutex_unlock(&per_pin->lock);
  357. return 0;
  358. }
  359. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  360. struct snd_ctl_elem_value *ucontrol)
  361. {
  362. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  363. struct hdmi_spec *spec = codec->spec;
  364. struct hdmi_spec_per_pin *per_pin;
  365. struct hdmi_eld *eld;
  366. int pin_idx;
  367. pin_idx = kcontrol->private_value;
  368. per_pin = get_pin(spec, pin_idx);
  369. eld = &per_pin->sink_eld;
  370. mutex_lock(&per_pin->lock);
  371. if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
  372. mutex_unlock(&per_pin->lock);
  373. snd_BUG();
  374. return -EINVAL;
  375. }
  376. memset(ucontrol->value.bytes.data, 0,
  377. ARRAY_SIZE(ucontrol->value.bytes.data));
  378. if (eld->eld_valid)
  379. memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
  380. eld->eld_size);
  381. mutex_unlock(&per_pin->lock);
  382. return 0;
  383. }
  384. static struct snd_kcontrol_new eld_bytes_ctl = {
  385. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  386. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  387. .name = "ELD",
  388. .info = hdmi_eld_ctl_info,
  389. .get = hdmi_eld_ctl_get,
  390. };
  391. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  392. int device)
  393. {
  394. struct snd_kcontrol *kctl;
  395. struct hdmi_spec *spec = codec->spec;
  396. int err;
  397. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  398. if (!kctl)
  399. return -ENOMEM;
  400. kctl->private_value = pin_idx;
  401. kctl->id.device = device;
  402. err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
  403. if (err < 0)
  404. return err;
  405. get_pin(spec, pin_idx)->eld_ctl = kctl;
  406. return 0;
  407. }
  408. #ifdef BE_PARANOID
  409. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  410. int *packet_index, int *byte_index)
  411. {
  412. int val;
  413. val = snd_hda_codec_read(codec, pin_nid, 0,
  414. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  415. *packet_index = val >> 5;
  416. *byte_index = val & 0x1f;
  417. }
  418. #endif
  419. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  420. int packet_index, int byte_index)
  421. {
  422. int val;
  423. val = (packet_index << 5) | (byte_index & 0x1f);
  424. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  425. }
  426. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  427. unsigned char val)
  428. {
  429. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  430. }
  431. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  432. {
  433. /* Unmute */
  434. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  435. snd_hda_codec_write(codec, pin_nid, 0,
  436. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  437. /* Enable pin out: some machines with GM965 gets broken output when
  438. * the pin is disabled or changed while using with HDMI
  439. */
  440. snd_hda_codec_write(codec, pin_nid, 0,
  441. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  442. }
  443. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  444. {
  445. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  446. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  447. }
  448. static void hdmi_set_channel_count(struct hda_codec *codec,
  449. hda_nid_t cvt_nid, int chs)
  450. {
  451. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  452. snd_hda_codec_write(codec, cvt_nid, 0,
  453. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  454. }
  455. /*
  456. * ELD proc files
  457. */
  458. #ifdef CONFIG_PROC_FS
  459. static void print_eld_info(struct snd_info_entry *entry,
  460. struct snd_info_buffer *buffer)
  461. {
  462. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  463. mutex_lock(&per_pin->lock);
  464. snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
  465. mutex_unlock(&per_pin->lock);
  466. }
  467. static void write_eld_info(struct snd_info_entry *entry,
  468. struct snd_info_buffer *buffer)
  469. {
  470. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  471. mutex_lock(&per_pin->lock);
  472. snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
  473. mutex_unlock(&per_pin->lock);
  474. }
  475. static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
  476. {
  477. char name[32];
  478. struct hda_codec *codec = per_pin->codec;
  479. struct snd_info_entry *entry;
  480. int err;
  481. snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
  482. err = snd_card_proc_new(codec->bus->card, name, &entry);
  483. if (err < 0)
  484. return err;
  485. snd_info_set_text_ops(entry, per_pin, print_eld_info);
  486. entry->c.text.write = write_eld_info;
  487. entry->mode |= S_IWUSR;
  488. per_pin->proc_entry = entry;
  489. return 0;
  490. }
  491. static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  492. {
  493. if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
  494. snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
  495. per_pin->proc_entry = NULL;
  496. }
  497. }
  498. #else
  499. static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
  500. int index)
  501. {
  502. return 0;
  503. }
  504. static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  505. {
  506. }
  507. #endif
  508. /*
  509. * Channel mapping routines
  510. */
  511. /*
  512. * Compute derived values in channel_allocations[].
  513. */
  514. static void init_channel_allocations(void)
  515. {
  516. int i, j;
  517. struct cea_channel_speaker_allocation *p;
  518. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  519. p = channel_allocations + i;
  520. p->channels = 0;
  521. p->spk_mask = 0;
  522. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  523. if (p->speakers[j]) {
  524. p->channels++;
  525. p->spk_mask |= p->speakers[j];
  526. }
  527. }
  528. }
  529. static int get_channel_allocation_order(int ca)
  530. {
  531. int i;
  532. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  533. if (channel_allocations[i].ca_index == ca)
  534. break;
  535. }
  536. return i;
  537. }
  538. /*
  539. * The transformation takes two steps:
  540. *
  541. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  542. * spk_mask => (channel_allocations[]) => ai->CA
  543. *
  544. * TODO: it could select the wrong CA from multiple candidates.
  545. */
  546. static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
  547. {
  548. int i;
  549. int ca = 0;
  550. int spk_mask = 0;
  551. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  552. /*
  553. * CA defaults to 0 for basic stereo audio
  554. */
  555. if (channels <= 2)
  556. return 0;
  557. /*
  558. * expand ELD's speaker allocation mask
  559. *
  560. * ELD tells the speaker mask in a compact(paired) form,
  561. * expand ELD's notions to match the ones used by Audio InfoFrame.
  562. */
  563. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  564. if (eld->info.spk_alloc & (1 << i))
  565. spk_mask |= eld_speaker_allocation_bits[i];
  566. }
  567. /* search for the first working match in the CA table */
  568. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  569. if (channels == channel_allocations[i].channels &&
  570. (spk_mask & channel_allocations[i].spk_mask) ==
  571. channel_allocations[i].spk_mask) {
  572. ca = channel_allocations[i].ca_index;
  573. break;
  574. }
  575. }
  576. if (!ca) {
  577. /* if there was no match, select the regular ALSA channel
  578. * allocation with the matching number of channels */
  579. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  580. if (channels == channel_allocations[i].channels) {
  581. ca = channel_allocations[i].ca_index;
  582. break;
  583. }
  584. }
  585. }
  586. snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
  587. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  588. ca, channels, buf);
  589. return ca;
  590. }
  591. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  592. hda_nid_t pin_nid)
  593. {
  594. #ifdef CONFIG_SND_DEBUG_VERBOSE
  595. struct hdmi_spec *spec = codec->spec;
  596. int i;
  597. int channel;
  598. for (i = 0; i < 8; i++) {
  599. channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
  600. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  601. channel, i);
  602. }
  603. #endif
  604. }
  605. static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
  606. hda_nid_t pin_nid,
  607. bool non_pcm,
  608. int ca)
  609. {
  610. struct hdmi_spec *spec = codec->spec;
  611. struct cea_channel_speaker_allocation *ch_alloc;
  612. int i;
  613. int err;
  614. int order;
  615. int non_pcm_mapping[8];
  616. order = get_channel_allocation_order(ca);
  617. ch_alloc = &channel_allocations[order];
  618. if (hdmi_channel_mapping[ca][1] == 0) {
  619. int hdmi_slot = 0;
  620. /* fill actual channel mappings in ALSA channel (i) order */
  621. for (i = 0; i < ch_alloc->channels; i++) {
  622. while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
  623. hdmi_slot++; /* skip zero slots */
  624. hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
  625. }
  626. /* fill the rest of the slots with ALSA channel 0xf */
  627. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
  628. if (!ch_alloc->speakers[7 - hdmi_slot])
  629. hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
  630. }
  631. if (non_pcm) {
  632. for (i = 0; i < ch_alloc->channels; i++)
  633. non_pcm_mapping[i] = (i << 4) | i;
  634. for (; i < 8; i++)
  635. non_pcm_mapping[i] = (0xf << 4) | i;
  636. }
  637. for (i = 0; i < 8; i++) {
  638. int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
  639. int hdmi_slot = slotsetup & 0x0f;
  640. int channel = (slotsetup & 0xf0) >> 4;
  641. err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
  642. if (err) {
  643. snd_printdd(KERN_NOTICE
  644. "HDMI: channel mapping failed\n");
  645. break;
  646. }
  647. }
  648. }
  649. struct channel_map_table {
  650. unsigned char map; /* ALSA API channel map position */
  651. int spk_mask; /* speaker position bit mask */
  652. };
  653. static struct channel_map_table map_tables[] = {
  654. { SNDRV_CHMAP_FL, FL },
  655. { SNDRV_CHMAP_FR, FR },
  656. { SNDRV_CHMAP_RL, RL },
  657. { SNDRV_CHMAP_RR, RR },
  658. { SNDRV_CHMAP_LFE, LFE },
  659. { SNDRV_CHMAP_FC, FC },
  660. { SNDRV_CHMAP_RLC, RLC },
  661. { SNDRV_CHMAP_RRC, RRC },
  662. { SNDRV_CHMAP_RC, RC },
  663. { SNDRV_CHMAP_FLC, FLC },
  664. { SNDRV_CHMAP_FRC, FRC },
  665. { SNDRV_CHMAP_FLH, FLH },
  666. { SNDRV_CHMAP_FRH, FRH },
  667. { SNDRV_CHMAP_FLW, FLW },
  668. { SNDRV_CHMAP_FRW, FRW },
  669. { SNDRV_CHMAP_TC, TC },
  670. { SNDRV_CHMAP_FCH, FCH },
  671. {} /* terminator */
  672. };
  673. /* from ALSA API channel position to speaker bit mask */
  674. static int to_spk_mask(unsigned char c)
  675. {
  676. struct channel_map_table *t = map_tables;
  677. for (; t->map; t++) {
  678. if (t->map == c)
  679. return t->spk_mask;
  680. }
  681. return 0;
  682. }
  683. /* from ALSA API channel position to CEA slot */
  684. static int to_cea_slot(int ordered_ca, unsigned char pos)
  685. {
  686. int mask = to_spk_mask(pos);
  687. int i;
  688. if (mask) {
  689. for (i = 0; i < 8; i++) {
  690. if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
  691. return i;
  692. }
  693. }
  694. return -1;
  695. }
  696. /* from speaker bit mask to ALSA API channel position */
  697. static int spk_to_chmap(int spk)
  698. {
  699. struct channel_map_table *t = map_tables;
  700. for (; t->map; t++) {
  701. if (t->spk_mask == spk)
  702. return t->map;
  703. }
  704. return 0;
  705. }
  706. /* from CEA slot to ALSA API channel position */
  707. static int from_cea_slot(int ordered_ca, unsigned char slot)
  708. {
  709. int mask = channel_allocations[ordered_ca].speakers[7 - slot];
  710. return spk_to_chmap(mask);
  711. }
  712. /* get the CA index corresponding to the given ALSA API channel map */
  713. static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
  714. {
  715. int i, spks = 0, spk_mask = 0;
  716. for (i = 0; i < chs; i++) {
  717. int mask = to_spk_mask(map[i]);
  718. if (mask) {
  719. spk_mask |= mask;
  720. spks++;
  721. }
  722. }
  723. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  724. if ((chs == channel_allocations[i].channels ||
  725. spks == channel_allocations[i].channels) &&
  726. (spk_mask & channel_allocations[i].spk_mask) ==
  727. channel_allocations[i].spk_mask)
  728. return channel_allocations[i].ca_index;
  729. }
  730. return -1;
  731. }
  732. /* set up the channel slots for the given ALSA API channel map */
  733. static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
  734. hda_nid_t pin_nid,
  735. int chs, unsigned char *map,
  736. int ca)
  737. {
  738. struct hdmi_spec *spec = codec->spec;
  739. int ordered_ca = get_channel_allocation_order(ca);
  740. int alsa_pos, hdmi_slot;
  741. int assignments[8] = {[0 ... 7] = 0xf};
  742. for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
  743. hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
  744. if (hdmi_slot < 0)
  745. continue; /* unassigned channel */
  746. assignments[hdmi_slot] = alsa_pos;
  747. }
  748. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
  749. int err;
  750. err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
  751. assignments[hdmi_slot]);
  752. if (err)
  753. return -EINVAL;
  754. }
  755. return 0;
  756. }
  757. /* store ALSA API channel map from the current default map */
  758. static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
  759. {
  760. int i;
  761. int ordered_ca = get_channel_allocation_order(ca);
  762. for (i = 0; i < 8; i++) {
  763. if (i < channel_allocations[ordered_ca].channels)
  764. map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
  765. else
  766. map[i] = 0;
  767. }
  768. }
  769. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  770. hda_nid_t pin_nid, bool non_pcm, int ca,
  771. int channels, unsigned char *map,
  772. bool chmap_set)
  773. {
  774. if (!non_pcm && chmap_set) {
  775. hdmi_manual_setup_channel_mapping(codec, pin_nid,
  776. channels, map, ca);
  777. } else {
  778. hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
  779. hdmi_setup_fake_chmap(map, ca);
  780. }
  781. hdmi_debug_channel_mapping(codec, pin_nid);
  782. }
  783. static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  784. int asp_slot, int channel)
  785. {
  786. return snd_hda_codec_write(codec, pin_nid, 0,
  787. AC_VERB_SET_HDMI_CHAN_SLOT,
  788. (channel << 4) | asp_slot);
  789. }
  790. static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  791. int asp_slot)
  792. {
  793. return (snd_hda_codec_read(codec, pin_nid, 0,
  794. AC_VERB_GET_HDMI_CHAN_SLOT,
  795. asp_slot) & 0xf0) >> 4;
  796. }
  797. /*
  798. * Audio InfoFrame routines
  799. */
  800. /*
  801. * Enable Audio InfoFrame Transmission
  802. */
  803. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  804. hda_nid_t pin_nid)
  805. {
  806. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  807. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  808. AC_DIPXMIT_BEST);
  809. }
  810. /*
  811. * Disable Audio InfoFrame Transmission
  812. */
  813. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  814. hda_nid_t pin_nid)
  815. {
  816. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  817. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  818. AC_DIPXMIT_DISABLE);
  819. }
  820. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  821. {
  822. #ifdef CONFIG_SND_DEBUG_VERBOSE
  823. int i;
  824. int size;
  825. size = snd_hdmi_get_eld_size(codec, pin_nid);
  826. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  827. for (i = 0; i < 8; i++) {
  828. size = snd_hda_codec_read(codec, pin_nid, 0,
  829. AC_VERB_GET_HDMI_DIP_SIZE, i);
  830. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  831. }
  832. #endif
  833. }
  834. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  835. {
  836. #ifdef BE_PARANOID
  837. int i, j;
  838. int size;
  839. int pi, bi;
  840. for (i = 0; i < 8; i++) {
  841. size = snd_hda_codec_read(codec, pin_nid, 0,
  842. AC_VERB_GET_HDMI_DIP_SIZE, i);
  843. if (size == 0)
  844. continue;
  845. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  846. for (j = 1; j < 1000; j++) {
  847. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  848. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  849. if (pi != i)
  850. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  851. bi, pi, i);
  852. if (bi == 0) /* byte index wrapped around */
  853. break;
  854. }
  855. snd_printd(KERN_INFO
  856. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  857. i, size, j);
  858. }
  859. #endif
  860. }
  861. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  862. {
  863. u8 *bytes = (u8 *)hdmi_ai;
  864. u8 sum = 0;
  865. int i;
  866. hdmi_ai->checksum = 0;
  867. for (i = 0; i < sizeof(*hdmi_ai); i++)
  868. sum += bytes[i];
  869. hdmi_ai->checksum = -sum;
  870. }
  871. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  872. hda_nid_t pin_nid,
  873. u8 *dip, int size)
  874. {
  875. int i;
  876. hdmi_debug_dip_size(codec, pin_nid);
  877. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  878. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  879. for (i = 0; i < size; i++)
  880. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  881. }
  882. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  883. u8 *dip, int size)
  884. {
  885. u8 val;
  886. int i;
  887. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  888. != AC_DIPXMIT_BEST)
  889. return false;
  890. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  891. for (i = 0; i < size; i++) {
  892. val = snd_hda_codec_read(codec, pin_nid, 0,
  893. AC_VERB_GET_HDMI_DIP_DATA, 0);
  894. if (val != dip[i])
  895. return false;
  896. }
  897. return true;
  898. }
  899. static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
  900. hda_nid_t pin_nid,
  901. int ca, int active_channels,
  902. int conn_type)
  903. {
  904. union audio_infoframe ai;
  905. if (conn_type == 0) { /* HDMI */
  906. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  907. hdmi_ai->type = 0x84;
  908. hdmi_ai->ver = 0x01;
  909. hdmi_ai->len = 0x0a;
  910. hdmi_ai->CC02_CT47 = active_channels - 1;
  911. hdmi_ai->CA = ca;
  912. hdmi_checksum_audio_infoframe(hdmi_ai);
  913. } else if (conn_type == 1) { /* DisplayPort */
  914. struct dp_audio_infoframe *dp_ai = &ai.dp;
  915. dp_ai->type = 0x84;
  916. dp_ai->len = 0x1b;
  917. dp_ai->ver = 0x11 << 2;
  918. dp_ai->CC02_CT47 = active_channels - 1;
  919. dp_ai->CA = ca;
  920. } else {
  921. snd_printd("HDMI: unknown connection type at pin %d\n",
  922. pin_nid);
  923. return;
  924. }
  925. /*
  926. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  927. * sizeof(*dp_ai) to avoid partial match/update problems when
  928. * the user switches between HDMI/DP monitors.
  929. */
  930. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  931. sizeof(ai))) {
  932. snd_printdd("hdmi_pin_setup_infoframe: "
  933. "pin=%d channels=%d ca=0x%02x\n",
  934. pin_nid,
  935. active_channels, ca);
  936. hdmi_stop_infoframe_trans(codec, pin_nid);
  937. hdmi_fill_audio_infoframe(codec, pin_nid,
  938. ai.bytes, sizeof(ai));
  939. hdmi_start_infoframe_trans(codec, pin_nid);
  940. }
  941. }
  942. static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
  943. struct hdmi_spec_per_pin *per_pin,
  944. bool non_pcm)
  945. {
  946. struct hdmi_spec *spec = codec->spec;
  947. hda_nid_t pin_nid = per_pin->pin_nid;
  948. int channels = per_pin->channels;
  949. int active_channels;
  950. struct hdmi_eld *eld;
  951. int ca, ordered_ca;
  952. if (!channels)
  953. return;
  954. if (is_haswell(codec))
  955. snd_hda_codec_write(codec, pin_nid, 0,
  956. AC_VERB_SET_AMP_GAIN_MUTE,
  957. AMP_OUT_UNMUTE);
  958. eld = &per_pin->sink_eld;
  959. if (!eld->monitor_present)
  960. return;
  961. if (!non_pcm && per_pin->chmap_set)
  962. ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
  963. else
  964. ca = hdmi_channel_allocation(eld, channels);
  965. if (ca < 0)
  966. ca = 0;
  967. ordered_ca = get_channel_allocation_order(ca);
  968. active_channels = channel_allocations[ordered_ca].channels;
  969. hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
  970. /*
  971. * always configure channel mapping, it may have been changed by the
  972. * user in the meantime
  973. */
  974. hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
  975. channels, per_pin->chmap,
  976. per_pin->chmap_set);
  977. spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
  978. eld->info.conn_type);
  979. per_pin->non_pcm = non_pcm;
  980. }
  981. /*
  982. * Unsolicited events
  983. */
  984. static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  985. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  986. {
  987. struct hdmi_spec *spec = codec->spec;
  988. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  989. int pin_nid;
  990. int pin_idx;
  991. struct hda_jack_tbl *jack;
  992. int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
  993. jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
  994. if (!jack)
  995. return;
  996. pin_nid = jack->nid;
  997. jack->jack_dirty = 1;
  998. _snd_printd(SND_PR_VERBOSE,
  999. "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
  1000. codec->addr, pin_nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
  1001. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  1002. pin_idx = pin_nid_to_pin_index(spec, pin_nid);
  1003. if (pin_idx < 0)
  1004. return;
  1005. if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
  1006. snd_hda_jack_report_sync(codec);
  1007. }
  1008. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  1009. {
  1010. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  1011. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  1012. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  1013. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  1014. printk(KERN_INFO
  1015. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  1016. codec->addr,
  1017. tag,
  1018. subtag,
  1019. cp_state,
  1020. cp_ready);
  1021. /* TODO */
  1022. if (cp_state)
  1023. ;
  1024. if (cp_ready)
  1025. ;
  1026. }
  1027. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  1028. {
  1029. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  1030. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  1031. if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
  1032. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  1033. return;
  1034. }
  1035. if (subtag == 0)
  1036. hdmi_intrinsic_event(codec, res);
  1037. else
  1038. hdmi_non_intrinsic_event(codec, res);
  1039. }
  1040. static void haswell_verify_D0(struct hda_codec *codec,
  1041. hda_nid_t cvt_nid, hda_nid_t nid)
  1042. {
  1043. int pwr;
  1044. /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
  1045. * thus pins could only choose converter 0 for use. Make sure the
  1046. * converters are in correct power state */
  1047. if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
  1048. snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
  1049. if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
  1050. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
  1051. AC_PWRST_D0);
  1052. msleep(40);
  1053. pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
  1054. pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
  1055. snd_printd("Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
  1056. }
  1057. }
  1058. /*
  1059. * Callbacks
  1060. */
  1061. /* HBR should be Non-PCM, 8 channels */
  1062. #define is_hbr_format(format) \
  1063. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  1064. static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  1065. bool hbr)
  1066. {
  1067. int pinctl, new_pinctl;
  1068. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  1069. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  1070. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1071. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  1072. if (hbr)
  1073. new_pinctl |= AC_PINCTL_EPT_HBR;
  1074. else
  1075. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  1076. snd_printdd("hdmi_pin_hbr_setup: "
  1077. "NID=0x%x, %spinctl=0x%x\n",
  1078. pin_nid,
  1079. pinctl == new_pinctl ? "" : "new-",
  1080. new_pinctl);
  1081. if (pinctl != new_pinctl)
  1082. snd_hda_codec_write(codec, pin_nid, 0,
  1083. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1084. new_pinctl);
  1085. } else if (hbr)
  1086. return -EINVAL;
  1087. return 0;
  1088. }
  1089. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  1090. hda_nid_t pin_nid, u32 stream_tag, int format)
  1091. {
  1092. struct hdmi_spec *spec = codec->spec;
  1093. int err;
  1094. if (is_haswell(codec))
  1095. haswell_verify_D0(codec, cvt_nid, pin_nid);
  1096. err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
  1097. if (err) {
  1098. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  1099. return err;
  1100. }
  1101. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  1102. return 0;
  1103. }
  1104. static int hdmi_choose_cvt(struct hda_codec *codec,
  1105. int pin_idx, int *cvt_id, int *mux_id)
  1106. {
  1107. struct hdmi_spec *spec = codec->spec;
  1108. struct hdmi_spec_per_pin *per_pin;
  1109. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1110. int cvt_idx, mux_idx = 0;
  1111. per_pin = get_pin(spec, pin_idx);
  1112. /* Dynamically assign converter to stream */
  1113. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  1114. per_cvt = get_cvt(spec, cvt_idx);
  1115. /* Must not already be assigned */
  1116. if (per_cvt->assigned)
  1117. continue;
  1118. /* Must be in pin's mux's list of converters */
  1119. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  1120. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  1121. break;
  1122. /* Not in mux list */
  1123. if (mux_idx == per_pin->num_mux_nids)
  1124. continue;
  1125. break;
  1126. }
  1127. /* No free converters */
  1128. if (cvt_idx == spec->num_cvts)
  1129. return -ENODEV;
  1130. if (cvt_id)
  1131. *cvt_id = cvt_idx;
  1132. if (mux_id)
  1133. *mux_id = mux_idx;
  1134. return 0;
  1135. }
  1136. /* Intel HDMI workaround to fix audio routing issue:
  1137. * For some Intel display codecs, pins share the same connection list.
  1138. * So a conveter can be selected by multiple pins and playback on any of these
  1139. * pins will generate sound on the external display, because audio flows from
  1140. * the same converter to the display pipeline. Also muting one pin may make
  1141. * other pins have no sound output.
  1142. * So this function assures that an assigned converter for a pin is not selected
  1143. * by any other pins.
  1144. */
  1145. static void intel_not_share_assigned_cvt(struct hda_codec *codec,
  1146. hda_nid_t pin_nid, int mux_idx)
  1147. {
  1148. struct hdmi_spec *spec = codec->spec;
  1149. hda_nid_t nid, end_nid;
  1150. int cvt_idx, curr;
  1151. struct hdmi_spec_per_cvt *per_cvt;
  1152. /* configure all pins, including "no physical connection" ones */
  1153. end_nid = codec->start_nid + codec->num_nodes;
  1154. for (nid = codec->start_nid; nid < end_nid; nid++) {
  1155. unsigned int wid_caps = get_wcaps(codec, nid);
  1156. unsigned int wid_type = get_wcaps_type(wid_caps);
  1157. if (wid_type != AC_WID_PIN)
  1158. continue;
  1159. if (nid == pin_nid)
  1160. continue;
  1161. curr = snd_hda_codec_read(codec, nid, 0,
  1162. AC_VERB_GET_CONNECT_SEL, 0);
  1163. if (curr != mux_idx)
  1164. continue;
  1165. /* choose an unassigned converter. The conveters in the
  1166. * connection list are in the same order as in the codec.
  1167. */
  1168. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  1169. per_cvt = get_cvt(spec, cvt_idx);
  1170. if (!per_cvt->assigned) {
  1171. snd_printdd("choose cvt %d for pin nid %d\n",
  1172. cvt_idx, nid);
  1173. snd_hda_codec_write_cache(codec, nid, 0,
  1174. AC_VERB_SET_CONNECT_SEL,
  1175. cvt_idx);
  1176. break;
  1177. }
  1178. }
  1179. }
  1180. }
  1181. /*
  1182. * HDA PCM callbacks
  1183. */
  1184. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  1185. struct hda_codec *codec,
  1186. struct snd_pcm_substream *substream)
  1187. {
  1188. struct hdmi_spec *spec = codec->spec;
  1189. struct snd_pcm_runtime *runtime = substream->runtime;
  1190. int pin_idx, cvt_idx, mux_idx = 0;
  1191. struct hdmi_spec_per_pin *per_pin;
  1192. struct hdmi_eld *eld;
  1193. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1194. int err;
  1195. /* Validate hinfo */
  1196. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1197. if (snd_BUG_ON(pin_idx < 0))
  1198. return -EINVAL;
  1199. per_pin = get_pin(spec, pin_idx);
  1200. eld = &per_pin->sink_eld;
  1201. err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
  1202. if (err < 0)
  1203. return err;
  1204. per_cvt = get_cvt(spec, cvt_idx);
  1205. /* Claim converter */
  1206. per_cvt->assigned = 1;
  1207. per_pin->cvt_nid = per_cvt->cvt_nid;
  1208. hinfo->nid = per_cvt->cvt_nid;
  1209. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1210. AC_VERB_SET_CONNECT_SEL,
  1211. mux_idx);
  1212. /* configure unused pins to choose other converters */
  1213. if (is_haswell(codec) || is_valleyview(codec))
  1214. intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
  1215. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  1216. /* Initially set the converter's capabilities */
  1217. hinfo->channels_min = per_cvt->channels_min;
  1218. hinfo->channels_max = per_cvt->channels_max;
  1219. hinfo->rates = per_cvt->rates;
  1220. hinfo->formats = per_cvt->formats;
  1221. hinfo->maxbps = per_cvt->maxbps;
  1222. /* Restrict capabilities by ELD if this isn't disabled */
  1223. if (!static_hdmi_pcm && eld->eld_valid) {
  1224. snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
  1225. if (hinfo->channels_min > hinfo->channels_max ||
  1226. !hinfo->rates || !hinfo->formats) {
  1227. per_cvt->assigned = 0;
  1228. hinfo->nid = 0;
  1229. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1230. return -ENODEV;
  1231. }
  1232. }
  1233. /* Store the updated parameters */
  1234. runtime->hw.channels_min = hinfo->channels_min;
  1235. runtime->hw.channels_max = hinfo->channels_max;
  1236. runtime->hw.formats = hinfo->formats;
  1237. runtime->hw.rates = hinfo->rates;
  1238. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1239. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1240. return 0;
  1241. }
  1242. /*
  1243. * HDA/HDMI auto parsing
  1244. */
  1245. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  1246. {
  1247. struct hdmi_spec *spec = codec->spec;
  1248. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1249. hda_nid_t pin_nid = per_pin->pin_nid;
  1250. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  1251. snd_printk(KERN_WARNING
  1252. "HDMI: pin %d wcaps %#x "
  1253. "does not support connection list\n",
  1254. pin_nid, get_wcaps(codec, pin_nid));
  1255. return -EINVAL;
  1256. }
  1257. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  1258. per_pin->mux_nids,
  1259. HDA_MAX_CONNECTIONS);
  1260. return 0;
  1261. }
  1262. static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  1263. {
  1264. struct hda_codec *codec = per_pin->codec;
  1265. struct hdmi_spec *spec = codec->spec;
  1266. struct hdmi_eld *eld = &spec->temp_eld;
  1267. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  1268. hda_nid_t pin_nid = per_pin->pin_nid;
  1269. /*
  1270. * Always execute a GetPinSense verb here, even when called from
  1271. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  1272. * response's PD bit is not the real PD value, but indicates that
  1273. * the real PD value changed. An older version of the HD-audio
  1274. * specification worked this way. Hence, we just ignore the data in
  1275. * the unsolicited response to avoid custom WARs.
  1276. */
  1277. int present = snd_hda_pin_sense(codec, pin_nid);
  1278. bool update_eld = false;
  1279. bool eld_changed = false;
  1280. bool ret;
  1281. mutex_lock(&per_pin->lock);
  1282. pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  1283. if (pin_eld->monitor_present)
  1284. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  1285. else
  1286. eld->eld_valid = false;
  1287. _snd_printd(SND_PR_VERBOSE,
  1288. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  1289. codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
  1290. if (eld->eld_valid) {
  1291. if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
  1292. &eld->eld_size) < 0)
  1293. eld->eld_valid = false;
  1294. else {
  1295. memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
  1296. if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
  1297. eld->eld_size) < 0)
  1298. eld->eld_valid = false;
  1299. }
  1300. if (eld->eld_valid) {
  1301. snd_hdmi_show_eld(&eld->info);
  1302. update_eld = true;
  1303. }
  1304. else if (repoll) {
  1305. queue_delayed_work(codec->bus->workq,
  1306. &per_pin->work,
  1307. msecs_to_jiffies(300));
  1308. goto unlock;
  1309. }
  1310. }
  1311. if (pin_eld->eld_valid && !eld->eld_valid) {
  1312. update_eld = true;
  1313. eld_changed = true;
  1314. }
  1315. if (update_eld) {
  1316. bool old_eld_valid = pin_eld->eld_valid;
  1317. pin_eld->eld_valid = eld->eld_valid;
  1318. eld_changed = pin_eld->eld_size != eld->eld_size ||
  1319. memcmp(pin_eld->eld_buffer, eld->eld_buffer,
  1320. eld->eld_size) != 0;
  1321. if (eld_changed)
  1322. memcpy(pin_eld->eld_buffer, eld->eld_buffer,
  1323. eld->eld_size);
  1324. pin_eld->eld_size = eld->eld_size;
  1325. pin_eld->info = eld->info;
  1326. /*
  1327. * Re-setup pin and infoframe. This is needed e.g. when
  1328. * - sink is first plugged-in (infoframe is not set up if !monitor_present)
  1329. * - transcoder can change during stream playback on Haswell
  1330. */
  1331. if (eld->eld_valid && !old_eld_valid && per_pin->setup)
  1332. hdmi_setup_audio_infoframe(codec, per_pin,
  1333. per_pin->non_pcm);
  1334. }
  1335. if (eld_changed)
  1336. snd_ctl_notify(codec->bus->card,
  1337. SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
  1338. &per_pin->eld_ctl->id);
  1339. unlock:
  1340. if ((codec->vendor_id & 0xffff0000) == 0x10020000)
  1341. ret = true; /* AMD codecs create ELD by itself */
  1342. else
  1343. ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
  1344. mutex_unlock(&per_pin->lock);
  1345. return ret;
  1346. }
  1347. static void hdmi_repoll_eld(struct work_struct *work)
  1348. {
  1349. struct hdmi_spec_per_pin *per_pin =
  1350. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  1351. if (per_pin->repoll_count++ > 6)
  1352. per_pin->repoll_count = 0;
  1353. if (hdmi_present_sense(per_pin, per_pin->repoll_count))
  1354. snd_hda_jack_report_sync(per_pin->codec);
  1355. }
  1356. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1357. hda_nid_t nid);
  1358. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  1359. {
  1360. struct hdmi_spec *spec = codec->spec;
  1361. unsigned int caps, config;
  1362. int pin_idx;
  1363. struct hdmi_spec_per_pin *per_pin;
  1364. int err;
  1365. caps = snd_hda_query_pin_caps(codec, pin_nid);
  1366. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  1367. return 0;
  1368. config = snd_hda_codec_get_pincfg(codec, pin_nid);
  1369. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  1370. return 0;
  1371. if (is_haswell(codec))
  1372. intel_haswell_fixup_connect_list(codec, pin_nid);
  1373. pin_idx = spec->num_pins;
  1374. per_pin = snd_array_new(&spec->pins);
  1375. if (!per_pin)
  1376. return -ENOMEM;
  1377. per_pin->pin_nid = pin_nid;
  1378. per_pin->non_pcm = false;
  1379. err = hdmi_read_pin_conn(codec, pin_idx);
  1380. if (err < 0)
  1381. return err;
  1382. spec->num_pins++;
  1383. return 0;
  1384. }
  1385. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1386. {
  1387. struct hdmi_spec *spec = codec->spec;
  1388. struct hdmi_spec_per_cvt *per_cvt;
  1389. unsigned int chans;
  1390. int err;
  1391. chans = get_wcaps(codec, cvt_nid);
  1392. chans = get_wcaps_channels(chans);
  1393. per_cvt = snd_array_new(&spec->cvts);
  1394. if (!per_cvt)
  1395. return -ENOMEM;
  1396. per_cvt->cvt_nid = cvt_nid;
  1397. per_cvt->channels_min = 2;
  1398. if (chans <= 16) {
  1399. per_cvt->channels_max = chans;
  1400. if (chans > spec->channels_max)
  1401. spec->channels_max = chans;
  1402. }
  1403. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  1404. &per_cvt->rates,
  1405. &per_cvt->formats,
  1406. &per_cvt->maxbps);
  1407. if (err < 0)
  1408. return err;
  1409. if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
  1410. spec->cvt_nids[spec->num_cvts] = cvt_nid;
  1411. spec->num_cvts++;
  1412. return 0;
  1413. }
  1414. static int hdmi_parse_codec(struct hda_codec *codec)
  1415. {
  1416. hda_nid_t nid;
  1417. int i, nodes;
  1418. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  1419. if (!nid || nodes < 0) {
  1420. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  1421. return -EINVAL;
  1422. }
  1423. for (i = 0; i < nodes; i++, nid++) {
  1424. unsigned int caps;
  1425. unsigned int type;
  1426. caps = get_wcaps(codec, nid);
  1427. type = get_wcaps_type(caps);
  1428. if (!(caps & AC_WCAP_DIGITAL))
  1429. continue;
  1430. switch (type) {
  1431. case AC_WID_AUD_OUT:
  1432. hdmi_add_cvt(codec, nid);
  1433. break;
  1434. case AC_WID_PIN:
  1435. hdmi_add_pin(codec, nid);
  1436. break;
  1437. }
  1438. }
  1439. #ifdef CONFIG_PM
  1440. /* We're seeing some problems with unsolicited hot plug events on
  1441. * PantherPoint after S3, if this is not enabled */
  1442. if (codec->vendor_id == 0x80862806)
  1443. codec->bus->power_keep_link_on = 1;
  1444. /*
  1445. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  1446. * can be lost and presence sense verb will become inaccurate if the
  1447. * HDA link is powered off at hot plug or hw initialization time.
  1448. */
  1449. else if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  1450. AC_PWRST_EPSS))
  1451. codec->bus->power_keep_link_on = 1;
  1452. #endif
  1453. return 0;
  1454. }
  1455. /*
  1456. */
  1457. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1458. {
  1459. struct hda_spdif_out *spdif;
  1460. bool non_pcm;
  1461. mutex_lock(&codec->spdif_mutex);
  1462. spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
  1463. non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
  1464. mutex_unlock(&codec->spdif_mutex);
  1465. return non_pcm;
  1466. }
  1467. /*
  1468. * HDMI callbacks
  1469. */
  1470. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1471. struct hda_codec *codec,
  1472. unsigned int stream_tag,
  1473. unsigned int format,
  1474. struct snd_pcm_substream *substream)
  1475. {
  1476. hda_nid_t cvt_nid = hinfo->nid;
  1477. struct hdmi_spec *spec = codec->spec;
  1478. int pin_idx = hinfo_to_pin_index(spec, hinfo);
  1479. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1480. hda_nid_t pin_nid = per_pin->pin_nid;
  1481. bool non_pcm;
  1482. non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
  1483. mutex_lock(&per_pin->lock);
  1484. per_pin->channels = substream->runtime->channels;
  1485. per_pin->setup = true;
  1486. hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
  1487. mutex_unlock(&per_pin->lock);
  1488. return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  1489. }
  1490. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  1491. struct hda_codec *codec,
  1492. struct snd_pcm_substream *substream)
  1493. {
  1494. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  1495. return 0;
  1496. }
  1497. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  1498. struct hda_codec *codec,
  1499. struct snd_pcm_substream *substream)
  1500. {
  1501. struct hdmi_spec *spec = codec->spec;
  1502. int cvt_idx, pin_idx;
  1503. struct hdmi_spec_per_cvt *per_cvt;
  1504. struct hdmi_spec_per_pin *per_pin;
  1505. if (hinfo->nid) {
  1506. cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
  1507. if (snd_BUG_ON(cvt_idx < 0))
  1508. return -EINVAL;
  1509. per_cvt = get_cvt(spec, cvt_idx);
  1510. snd_BUG_ON(!per_cvt->assigned);
  1511. per_cvt->assigned = 0;
  1512. hinfo->nid = 0;
  1513. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1514. if (snd_BUG_ON(pin_idx < 0))
  1515. return -EINVAL;
  1516. per_pin = get_pin(spec, pin_idx);
  1517. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1518. mutex_lock(&per_pin->lock);
  1519. per_pin->chmap_set = false;
  1520. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1521. per_pin->setup = false;
  1522. per_pin->channels = 0;
  1523. mutex_unlock(&per_pin->lock);
  1524. }
  1525. return 0;
  1526. }
  1527. static const struct hda_pcm_ops generic_ops = {
  1528. .open = hdmi_pcm_open,
  1529. .close = hdmi_pcm_close,
  1530. .prepare = generic_hdmi_playback_pcm_prepare,
  1531. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1532. };
  1533. /*
  1534. * ALSA API channel-map control callbacks
  1535. */
  1536. static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_info *uinfo)
  1538. {
  1539. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1540. struct hda_codec *codec = info->private_data;
  1541. struct hdmi_spec *spec = codec->spec;
  1542. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1543. uinfo->count = spec->channels_max;
  1544. uinfo->value.integer.min = 0;
  1545. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  1546. return 0;
  1547. }
  1548. static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  1549. int channels)
  1550. {
  1551. /* If the speaker allocation matches the channel count, it is OK.*/
  1552. if (cap->channels != channels)
  1553. return -1;
  1554. /* all channels are remappable freely */
  1555. return SNDRV_CTL_TLVT_CHMAP_VAR;
  1556. }
  1557. static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
  1558. unsigned int *chmap, int channels)
  1559. {
  1560. int count = 0;
  1561. int c;
  1562. for (c = 7; c >= 0; c--) {
  1563. int spk = cap->speakers[c];
  1564. if (!spk)
  1565. continue;
  1566. chmap[count++] = spk_to_chmap(spk);
  1567. }
  1568. WARN_ON(count != channels);
  1569. }
  1570. static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
  1571. unsigned int size, unsigned int __user *tlv)
  1572. {
  1573. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1574. struct hda_codec *codec = info->private_data;
  1575. struct hdmi_spec *spec = codec->spec;
  1576. unsigned int __user *dst;
  1577. int chs, count = 0;
  1578. if (size < 8)
  1579. return -ENOMEM;
  1580. if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
  1581. return -EFAULT;
  1582. size -= 8;
  1583. dst = tlv + 2;
  1584. for (chs = 2; chs <= spec->channels_max; chs++) {
  1585. int i;
  1586. struct cea_channel_speaker_allocation *cap;
  1587. cap = channel_allocations;
  1588. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
  1589. int chs_bytes = chs * 4;
  1590. int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
  1591. unsigned int tlv_chmap[8];
  1592. if (type < 0)
  1593. continue;
  1594. if (size < 8)
  1595. return -ENOMEM;
  1596. if (put_user(type, dst) ||
  1597. put_user(chs_bytes, dst + 1))
  1598. return -EFAULT;
  1599. dst += 2;
  1600. size -= 8;
  1601. count += 8;
  1602. if (size < chs_bytes)
  1603. return -ENOMEM;
  1604. size -= chs_bytes;
  1605. count += chs_bytes;
  1606. spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
  1607. if (copy_to_user(dst, tlv_chmap, chs_bytes))
  1608. return -EFAULT;
  1609. dst += chs;
  1610. }
  1611. }
  1612. if (put_user(count, tlv + 1))
  1613. return -EFAULT;
  1614. return 0;
  1615. }
  1616. static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  1617. struct snd_ctl_elem_value *ucontrol)
  1618. {
  1619. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1620. struct hda_codec *codec = info->private_data;
  1621. struct hdmi_spec *spec = codec->spec;
  1622. int pin_idx = kcontrol->private_value;
  1623. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1624. int i;
  1625. for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
  1626. ucontrol->value.integer.value[i] = per_pin->chmap[i];
  1627. return 0;
  1628. }
  1629. static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
  1630. struct snd_ctl_elem_value *ucontrol)
  1631. {
  1632. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1633. struct hda_codec *codec = info->private_data;
  1634. struct hdmi_spec *spec = codec->spec;
  1635. int pin_idx = kcontrol->private_value;
  1636. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1637. unsigned int ctl_idx;
  1638. struct snd_pcm_substream *substream;
  1639. unsigned char chmap[8];
  1640. int i, err, ca, prepared = 0;
  1641. ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1642. substream = snd_pcm_chmap_substream(info, ctl_idx);
  1643. if (!substream || !substream->runtime)
  1644. return 0; /* just for avoiding error from alsactl restore */
  1645. switch (substream->runtime->status->state) {
  1646. case SNDRV_PCM_STATE_OPEN:
  1647. case SNDRV_PCM_STATE_SETUP:
  1648. break;
  1649. case SNDRV_PCM_STATE_PREPARED:
  1650. prepared = 1;
  1651. break;
  1652. default:
  1653. return -EBUSY;
  1654. }
  1655. memset(chmap, 0, sizeof(chmap));
  1656. for (i = 0; i < ARRAY_SIZE(chmap); i++)
  1657. chmap[i] = ucontrol->value.integer.value[i];
  1658. if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
  1659. return 0;
  1660. ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
  1661. if (ca < 0)
  1662. return -EINVAL;
  1663. if (spec->ops.chmap_validate) {
  1664. err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
  1665. if (err)
  1666. return err;
  1667. }
  1668. mutex_lock(&per_pin->lock);
  1669. per_pin->chmap_set = true;
  1670. memcpy(per_pin->chmap, chmap, sizeof(chmap));
  1671. if (prepared)
  1672. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1673. mutex_unlock(&per_pin->lock);
  1674. return 0;
  1675. }
  1676. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1677. {
  1678. struct hdmi_spec *spec = codec->spec;
  1679. int pin_idx;
  1680. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1681. struct hda_pcm *info;
  1682. struct hda_pcm_stream *pstr;
  1683. struct hdmi_spec_per_pin *per_pin;
  1684. per_pin = get_pin(spec, pin_idx);
  1685. sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
  1686. info = snd_array_new(&spec->pcm_rec);
  1687. if (!info)
  1688. return -ENOMEM;
  1689. info->name = per_pin->pcm_name;
  1690. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1691. info->own_chmap = true;
  1692. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1693. pstr->substreams = 1;
  1694. pstr->ops = generic_ops;
  1695. /* other pstr fields are set in open */
  1696. }
  1697. codec->num_pcms = spec->num_pins;
  1698. codec->pcm_info = spec->pcm_rec.list;
  1699. return 0;
  1700. }
  1701. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1702. {
  1703. char hdmi_str[32] = "HDMI/DP";
  1704. struct hdmi_spec *spec = codec->spec;
  1705. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1706. int pcmdev = get_pcm_rec(spec, pin_idx)->device;
  1707. if (pcmdev > 0)
  1708. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1709. if (!is_jack_detectable(codec, per_pin->pin_nid))
  1710. strncat(hdmi_str, " Phantom",
  1711. sizeof(hdmi_str) - strlen(hdmi_str) - 1);
  1712. return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
  1713. }
  1714. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1715. {
  1716. struct hdmi_spec *spec = codec->spec;
  1717. int err;
  1718. int pin_idx;
  1719. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1720. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1721. err = generic_hdmi_build_jack(codec, pin_idx);
  1722. if (err < 0)
  1723. return err;
  1724. err = snd_hda_create_dig_out_ctls(codec,
  1725. per_pin->pin_nid,
  1726. per_pin->mux_nids[0],
  1727. HDA_PCM_TYPE_HDMI);
  1728. if (err < 0)
  1729. return err;
  1730. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1731. /* add control for ELD Bytes */
  1732. err = hdmi_create_eld_ctl(codec, pin_idx,
  1733. get_pcm_rec(spec, pin_idx)->device);
  1734. if (err < 0)
  1735. return err;
  1736. hdmi_present_sense(per_pin, 0);
  1737. }
  1738. /* add channel maps */
  1739. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1740. struct snd_pcm_chmap *chmap;
  1741. struct snd_kcontrol *kctl;
  1742. int i;
  1743. if (!codec->pcm_info[pin_idx].pcm)
  1744. break;
  1745. err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
  1746. SNDRV_PCM_STREAM_PLAYBACK,
  1747. NULL, 0, pin_idx, &chmap);
  1748. if (err < 0)
  1749. return err;
  1750. /* override handlers */
  1751. chmap->private_data = codec;
  1752. kctl = chmap->kctl;
  1753. for (i = 0; i < kctl->count; i++)
  1754. kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
  1755. kctl->info = hdmi_chmap_ctl_info;
  1756. kctl->get = hdmi_chmap_ctl_get;
  1757. kctl->put = hdmi_chmap_ctl_put;
  1758. kctl->tlv.c = hdmi_chmap_ctl_tlv;
  1759. }
  1760. return 0;
  1761. }
  1762. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  1763. {
  1764. struct hdmi_spec *spec = codec->spec;
  1765. int pin_idx;
  1766. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1767. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1768. per_pin->codec = codec;
  1769. mutex_init(&per_pin->lock);
  1770. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  1771. eld_proc_new(per_pin, pin_idx);
  1772. }
  1773. return 0;
  1774. }
  1775. static int generic_hdmi_init(struct hda_codec *codec)
  1776. {
  1777. struct hdmi_spec *spec = codec->spec;
  1778. int pin_idx;
  1779. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1780. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1781. hda_nid_t pin_nid = per_pin->pin_nid;
  1782. hdmi_init_pin(codec, pin_nid);
  1783. snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
  1784. }
  1785. return 0;
  1786. }
  1787. static void hdmi_array_init(struct hdmi_spec *spec, int nums)
  1788. {
  1789. snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
  1790. snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
  1791. snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
  1792. }
  1793. static void hdmi_array_free(struct hdmi_spec *spec)
  1794. {
  1795. snd_array_free(&spec->pins);
  1796. snd_array_free(&spec->cvts);
  1797. snd_array_free(&spec->pcm_rec);
  1798. }
  1799. static void generic_hdmi_free(struct hda_codec *codec)
  1800. {
  1801. struct hdmi_spec *spec = codec->spec;
  1802. int pin_idx;
  1803. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1804. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1805. cancel_delayed_work(&per_pin->work);
  1806. eld_proc_free(per_pin);
  1807. }
  1808. flush_workqueue(codec->bus->workq);
  1809. hdmi_array_free(spec);
  1810. kfree(spec);
  1811. }
  1812. #ifdef CONFIG_PM
  1813. static int generic_hdmi_resume(struct hda_codec *codec)
  1814. {
  1815. struct hdmi_spec *spec = codec->spec;
  1816. int pin_idx;
  1817. generic_hdmi_init(codec);
  1818. snd_hda_codec_resume_amp(codec);
  1819. snd_hda_codec_resume_cache(codec);
  1820. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1821. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1822. hdmi_present_sense(per_pin, 1);
  1823. }
  1824. return 0;
  1825. }
  1826. #endif
  1827. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1828. .init = generic_hdmi_init,
  1829. .free = generic_hdmi_free,
  1830. .build_pcms = generic_hdmi_build_pcms,
  1831. .build_controls = generic_hdmi_build_controls,
  1832. .unsol_event = hdmi_unsol_event,
  1833. #ifdef CONFIG_PM
  1834. .resume = generic_hdmi_resume,
  1835. #endif
  1836. };
  1837. static const struct hdmi_ops generic_standard_hdmi_ops = {
  1838. .pin_get_eld = snd_hdmi_get_eld,
  1839. .pin_get_slot_channel = hdmi_pin_get_slot_channel,
  1840. .pin_set_slot_channel = hdmi_pin_set_slot_channel,
  1841. .pin_setup_infoframe = hdmi_pin_setup_infoframe,
  1842. .pin_hbr_setup = hdmi_pin_hbr_setup,
  1843. .setup_stream = hdmi_setup_stream,
  1844. .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
  1845. .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
  1846. };
  1847. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1848. hda_nid_t nid)
  1849. {
  1850. struct hdmi_spec *spec = codec->spec;
  1851. hda_nid_t conns[4];
  1852. int nconns;
  1853. nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
  1854. if (nconns == spec->num_cvts &&
  1855. !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
  1856. return;
  1857. /* override pins connection list */
  1858. snd_printdd("hdmi: haswell: override pin connection 0x%x\n", nid);
  1859. snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
  1860. }
  1861. #define INTEL_VENDOR_NID 0x08
  1862. #define INTEL_GET_VENDOR_VERB 0xf81
  1863. #define INTEL_SET_VENDOR_VERB 0x781
  1864. #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
  1865. #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
  1866. static void intel_haswell_enable_all_pins(struct hda_codec *codec,
  1867. bool update_tree)
  1868. {
  1869. unsigned int vendor_param;
  1870. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1871. INTEL_GET_VENDOR_VERB, 0);
  1872. if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
  1873. return;
  1874. vendor_param |= INTEL_EN_ALL_PIN_CVTS;
  1875. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1876. INTEL_SET_VENDOR_VERB, vendor_param);
  1877. if (vendor_param == -1)
  1878. return;
  1879. if (update_tree)
  1880. snd_hda_codec_update_widgets(codec);
  1881. }
  1882. static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
  1883. {
  1884. unsigned int vendor_param;
  1885. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1886. INTEL_GET_VENDOR_VERB, 0);
  1887. if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
  1888. return;
  1889. /* enable DP1.2 mode */
  1890. vendor_param |= INTEL_EN_DP12;
  1891. snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
  1892. INTEL_SET_VENDOR_VERB, vendor_param);
  1893. }
  1894. /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
  1895. * Otherwise you may get severe h/w communication errors.
  1896. */
  1897. static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
  1898. unsigned int power_state)
  1899. {
  1900. if (power_state == AC_PWRST_D0) {
  1901. intel_haswell_enable_all_pins(codec, false);
  1902. intel_haswell_fixup_enable_dp12(codec);
  1903. }
  1904. snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
  1905. snd_hda_codec_set_power_to_all(codec, fg, power_state);
  1906. }
  1907. static int patch_generic_hdmi(struct hda_codec *codec)
  1908. {
  1909. struct hdmi_spec *spec;
  1910. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1911. if (spec == NULL)
  1912. return -ENOMEM;
  1913. spec->ops = generic_standard_hdmi_ops;
  1914. codec->spec = spec;
  1915. hdmi_array_init(spec, 4);
  1916. if (is_haswell(codec)) {
  1917. intel_haswell_enable_all_pins(codec, true);
  1918. intel_haswell_fixup_enable_dp12(codec);
  1919. }
  1920. if (hdmi_parse_codec(codec) < 0) {
  1921. codec->spec = NULL;
  1922. kfree(spec);
  1923. return -EINVAL;
  1924. }
  1925. codec->patch_ops = generic_hdmi_patch_ops;
  1926. if (is_haswell(codec)) {
  1927. codec->patch_ops.set_power_state = haswell_set_power_state;
  1928. codec->dp_mst = true;
  1929. }
  1930. generic_hdmi_init_per_pins(codec);
  1931. init_channel_allocations();
  1932. return 0;
  1933. }
  1934. /*
  1935. * Shared non-generic implementations
  1936. */
  1937. static int simple_playback_build_pcms(struct hda_codec *codec)
  1938. {
  1939. struct hdmi_spec *spec = codec->spec;
  1940. struct hda_pcm *info;
  1941. unsigned int chans;
  1942. struct hda_pcm_stream *pstr;
  1943. struct hdmi_spec_per_cvt *per_cvt;
  1944. per_cvt = get_cvt(spec, 0);
  1945. chans = get_wcaps(codec, per_cvt->cvt_nid);
  1946. chans = get_wcaps_channels(chans);
  1947. info = snd_array_new(&spec->pcm_rec);
  1948. if (!info)
  1949. return -ENOMEM;
  1950. info->name = get_pin(spec, 0)->pcm_name;
  1951. sprintf(info->name, "HDMI 0");
  1952. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1953. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1954. *pstr = spec->pcm_playback;
  1955. pstr->nid = per_cvt->cvt_nid;
  1956. if (pstr->channels_max <= 2 && chans && chans <= 16)
  1957. pstr->channels_max = chans;
  1958. codec->num_pcms = 1;
  1959. codec->pcm_info = info;
  1960. return 0;
  1961. }
  1962. /* unsolicited event for jack sensing */
  1963. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  1964. unsigned int res)
  1965. {
  1966. snd_hda_jack_set_dirty_all(codec);
  1967. snd_hda_jack_report_sync(codec);
  1968. }
  1969. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  1970. * as long as spec->pins[] is set correctly
  1971. */
  1972. #define simple_hdmi_build_jack generic_hdmi_build_jack
  1973. static int simple_playback_build_controls(struct hda_codec *codec)
  1974. {
  1975. struct hdmi_spec *spec = codec->spec;
  1976. struct hdmi_spec_per_cvt *per_cvt;
  1977. int err;
  1978. per_cvt = get_cvt(spec, 0);
  1979. err = snd_hda_create_spdif_out_ctls(codec, per_cvt->cvt_nid,
  1980. per_cvt->cvt_nid);
  1981. if (err < 0)
  1982. return err;
  1983. return simple_hdmi_build_jack(codec, 0);
  1984. }
  1985. static int simple_playback_init(struct hda_codec *codec)
  1986. {
  1987. struct hdmi_spec *spec = codec->spec;
  1988. struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
  1989. hda_nid_t pin = per_pin->pin_nid;
  1990. snd_hda_codec_write(codec, pin, 0,
  1991. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  1992. /* some codecs require to unmute the pin */
  1993. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  1994. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  1995. AMP_OUT_UNMUTE);
  1996. snd_hda_jack_detect_enable(codec, pin, pin);
  1997. return 0;
  1998. }
  1999. static void simple_playback_free(struct hda_codec *codec)
  2000. {
  2001. struct hdmi_spec *spec = codec->spec;
  2002. hdmi_array_free(spec);
  2003. kfree(spec);
  2004. }
  2005. /*
  2006. * Nvidia specific implementations
  2007. */
  2008. #define Nv_VERB_SET_Channel_Allocation 0xF79
  2009. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  2010. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  2011. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  2012. #define nvhdmi_master_con_nid_7x 0x04
  2013. #define nvhdmi_master_pin_nid_7x 0x05
  2014. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  2015. /*front, rear, clfe, rear_surr */
  2016. 0x6, 0x8, 0xa, 0xc,
  2017. };
  2018. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  2019. /* set audio protect on */
  2020. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2021. /* enable digital output on pin widget */
  2022. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2023. {} /* terminator */
  2024. };
  2025. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  2026. /* set audio protect on */
  2027. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2028. /* enable digital output on pin widget */
  2029. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2030. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2031. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2032. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2033. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2034. {} /* terminator */
  2035. };
  2036. #ifdef LIMITED_RATE_FMT_SUPPORT
  2037. /* support only the safe format and rate */
  2038. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  2039. #define SUPPORTED_MAXBPS 16
  2040. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  2041. #else
  2042. /* support all rates and formats */
  2043. #define SUPPORTED_RATES \
  2044. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  2045. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  2046. SNDRV_PCM_RATE_192000)
  2047. #define SUPPORTED_MAXBPS 24
  2048. #define SUPPORTED_FORMATS \
  2049. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2050. #endif
  2051. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  2052. {
  2053. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  2054. return 0;
  2055. }
  2056. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  2057. {
  2058. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  2059. return 0;
  2060. }
  2061. static unsigned int channels_2_6_8[] = {
  2062. 2, 6, 8
  2063. };
  2064. static unsigned int channels_2_8[] = {
  2065. 2, 8
  2066. };
  2067. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  2068. .count = ARRAY_SIZE(channels_2_6_8),
  2069. .list = channels_2_6_8,
  2070. .mask = 0,
  2071. };
  2072. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  2073. .count = ARRAY_SIZE(channels_2_8),
  2074. .list = channels_2_8,
  2075. .mask = 0,
  2076. };
  2077. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  2078. struct hda_codec *codec,
  2079. struct snd_pcm_substream *substream)
  2080. {
  2081. struct hdmi_spec *spec = codec->spec;
  2082. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  2083. switch (codec->preset->id) {
  2084. case 0x10de0002:
  2085. case 0x10de0003:
  2086. case 0x10de0005:
  2087. case 0x10de0006:
  2088. hw_constraints_channels = &hw_constraints_2_8_channels;
  2089. break;
  2090. case 0x10de0007:
  2091. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  2092. break;
  2093. default:
  2094. break;
  2095. }
  2096. if (hw_constraints_channels != NULL) {
  2097. snd_pcm_hw_constraint_list(substream->runtime, 0,
  2098. SNDRV_PCM_HW_PARAM_CHANNELS,
  2099. hw_constraints_channels);
  2100. } else {
  2101. snd_pcm_hw_constraint_step(substream->runtime, 0,
  2102. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  2103. }
  2104. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  2105. }
  2106. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  2107. struct hda_codec *codec,
  2108. struct snd_pcm_substream *substream)
  2109. {
  2110. struct hdmi_spec *spec = codec->spec;
  2111. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2112. }
  2113. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2114. struct hda_codec *codec,
  2115. unsigned int stream_tag,
  2116. unsigned int format,
  2117. struct snd_pcm_substream *substream)
  2118. {
  2119. struct hdmi_spec *spec = codec->spec;
  2120. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  2121. stream_tag, format, substream);
  2122. }
  2123. static const struct hda_pcm_stream simple_pcm_playback = {
  2124. .substreams = 1,
  2125. .channels_min = 2,
  2126. .channels_max = 2,
  2127. .ops = {
  2128. .open = simple_playback_pcm_open,
  2129. .close = simple_playback_pcm_close,
  2130. .prepare = simple_playback_pcm_prepare
  2131. },
  2132. };
  2133. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  2134. .build_controls = simple_playback_build_controls,
  2135. .build_pcms = simple_playback_build_pcms,
  2136. .init = simple_playback_init,
  2137. .free = simple_playback_free,
  2138. .unsol_event = simple_hdmi_unsol_event,
  2139. };
  2140. static int patch_simple_hdmi(struct hda_codec *codec,
  2141. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  2142. {
  2143. struct hdmi_spec *spec;
  2144. struct hdmi_spec_per_cvt *per_cvt;
  2145. struct hdmi_spec_per_pin *per_pin;
  2146. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  2147. if (!spec)
  2148. return -ENOMEM;
  2149. codec->spec = spec;
  2150. hdmi_array_init(spec, 1);
  2151. spec->multiout.num_dacs = 0; /* no analog */
  2152. spec->multiout.max_channels = 2;
  2153. spec->multiout.dig_out_nid = cvt_nid;
  2154. spec->num_cvts = 1;
  2155. spec->num_pins = 1;
  2156. per_pin = snd_array_new(&spec->pins);
  2157. per_cvt = snd_array_new(&spec->cvts);
  2158. if (!per_pin || !per_cvt) {
  2159. simple_playback_free(codec);
  2160. return -ENOMEM;
  2161. }
  2162. per_cvt->cvt_nid = cvt_nid;
  2163. per_pin->pin_nid = pin_nid;
  2164. spec->pcm_playback = simple_pcm_playback;
  2165. codec->patch_ops = simple_hdmi_patch_ops;
  2166. return 0;
  2167. }
  2168. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  2169. int channels)
  2170. {
  2171. unsigned int chanmask;
  2172. int chan = channels ? (channels - 1) : 1;
  2173. switch (channels) {
  2174. default:
  2175. case 0:
  2176. case 2:
  2177. chanmask = 0x00;
  2178. break;
  2179. case 4:
  2180. chanmask = 0x08;
  2181. break;
  2182. case 6:
  2183. chanmask = 0x0b;
  2184. break;
  2185. case 8:
  2186. chanmask = 0x13;
  2187. break;
  2188. }
  2189. /* Set the audio infoframe channel allocation and checksum fields. The
  2190. * channel count is computed implicitly by the hardware. */
  2191. snd_hda_codec_write(codec, 0x1, 0,
  2192. Nv_VERB_SET_Channel_Allocation, chanmask);
  2193. snd_hda_codec_write(codec, 0x1, 0,
  2194. Nv_VERB_SET_Info_Frame_Checksum,
  2195. (0x71 - chan - chanmask));
  2196. }
  2197. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  2198. struct hda_codec *codec,
  2199. struct snd_pcm_substream *substream)
  2200. {
  2201. struct hdmi_spec *spec = codec->spec;
  2202. int i;
  2203. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  2204. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  2205. for (i = 0; i < 4; i++) {
  2206. /* set the stream id */
  2207. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2208. AC_VERB_SET_CHANNEL_STREAMID, 0);
  2209. /* set the stream format */
  2210. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2211. AC_VERB_SET_STREAM_FORMAT, 0);
  2212. }
  2213. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  2214. * streams are disabled. */
  2215. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2216. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2217. }
  2218. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  2219. struct hda_codec *codec,
  2220. unsigned int stream_tag,
  2221. unsigned int format,
  2222. struct snd_pcm_substream *substream)
  2223. {
  2224. int chs;
  2225. unsigned int dataDCC2, channel_id;
  2226. int i;
  2227. struct hdmi_spec *spec = codec->spec;
  2228. struct hda_spdif_out *spdif;
  2229. struct hdmi_spec_per_cvt *per_cvt;
  2230. mutex_lock(&codec->spdif_mutex);
  2231. per_cvt = get_cvt(spec, 0);
  2232. spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
  2233. chs = substream->runtime->channels;
  2234. dataDCC2 = 0x2;
  2235. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  2236. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  2237. snd_hda_codec_write(codec,
  2238. nvhdmi_master_con_nid_7x,
  2239. 0,
  2240. AC_VERB_SET_DIGI_CONVERT_1,
  2241. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2242. /* set the stream id */
  2243. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2244. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  2245. /* set the stream format */
  2246. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2247. AC_VERB_SET_STREAM_FORMAT, format);
  2248. /* turn on again (if needed) */
  2249. /* enable and set the channel status audio/data flag */
  2250. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  2251. snd_hda_codec_write(codec,
  2252. nvhdmi_master_con_nid_7x,
  2253. 0,
  2254. AC_VERB_SET_DIGI_CONVERT_1,
  2255. spdif->ctls & 0xff);
  2256. snd_hda_codec_write(codec,
  2257. nvhdmi_master_con_nid_7x,
  2258. 0,
  2259. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2260. }
  2261. for (i = 0; i < 4; i++) {
  2262. if (chs == 2)
  2263. channel_id = 0;
  2264. else
  2265. channel_id = i * 2;
  2266. /* turn off SPDIF once;
  2267. *otherwise the IEC958 bits won't be updated
  2268. */
  2269. if (codec->spdif_status_reset &&
  2270. (spdif->ctls & AC_DIG1_ENABLE))
  2271. snd_hda_codec_write(codec,
  2272. nvhdmi_con_nids_7x[i],
  2273. 0,
  2274. AC_VERB_SET_DIGI_CONVERT_1,
  2275. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2276. /* set the stream id */
  2277. snd_hda_codec_write(codec,
  2278. nvhdmi_con_nids_7x[i],
  2279. 0,
  2280. AC_VERB_SET_CHANNEL_STREAMID,
  2281. (stream_tag << 4) | channel_id);
  2282. /* set the stream format */
  2283. snd_hda_codec_write(codec,
  2284. nvhdmi_con_nids_7x[i],
  2285. 0,
  2286. AC_VERB_SET_STREAM_FORMAT,
  2287. format);
  2288. /* turn on again (if needed) */
  2289. /* enable and set the channel status audio/data flag */
  2290. if (codec->spdif_status_reset &&
  2291. (spdif->ctls & AC_DIG1_ENABLE)) {
  2292. snd_hda_codec_write(codec,
  2293. nvhdmi_con_nids_7x[i],
  2294. 0,
  2295. AC_VERB_SET_DIGI_CONVERT_1,
  2296. spdif->ctls & 0xff);
  2297. snd_hda_codec_write(codec,
  2298. nvhdmi_con_nids_7x[i],
  2299. 0,
  2300. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2301. }
  2302. }
  2303. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  2304. mutex_unlock(&codec->spdif_mutex);
  2305. return 0;
  2306. }
  2307. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  2308. .substreams = 1,
  2309. .channels_min = 2,
  2310. .channels_max = 8,
  2311. .nid = nvhdmi_master_con_nid_7x,
  2312. .rates = SUPPORTED_RATES,
  2313. .maxbps = SUPPORTED_MAXBPS,
  2314. .formats = SUPPORTED_FORMATS,
  2315. .ops = {
  2316. .open = simple_playback_pcm_open,
  2317. .close = nvhdmi_8ch_7x_pcm_close,
  2318. .prepare = nvhdmi_8ch_7x_pcm_prepare
  2319. },
  2320. };
  2321. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  2322. {
  2323. struct hdmi_spec *spec;
  2324. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  2325. nvhdmi_master_pin_nid_7x);
  2326. if (err < 0)
  2327. return err;
  2328. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  2329. /* override the PCM rates, etc, as the codec doesn't give full list */
  2330. spec = codec->spec;
  2331. spec->pcm_playback.rates = SUPPORTED_RATES;
  2332. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  2333. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  2334. return 0;
  2335. }
  2336. static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
  2337. {
  2338. struct hdmi_spec *spec = codec->spec;
  2339. int err = simple_playback_build_pcms(codec);
  2340. if (!err) {
  2341. struct hda_pcm *info = get_pcm_rec(spec, 0);
  2342. info->own_chmap = true;
  2343. }
  2344. return err;
  2345. }
  2346. static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
  2347. {
  2348. struct hdmi_spec *spec = codec->spec;
  2349. struct hda_pcm *info;
  2350. struct snd_pcm_chmap *chmap;
  2351. int err;
  2352. err = simple_playback_build_controls(codec);
  2353. if (err < 0)
  2354. return err;
  2355. /* add channel maps */
  2356. info = get_pcm_rec(spec, 0);
  2357. err = snd_pcm_add_chmap_ctls(info->pcm,
  2358. SNDRV_PCM_STREAM_PLAYBACK,
  2359. snd_pcm_alt_chmaps, 8, 0, &chmap);
  2360. if (err < 0)
  2361. return err;
  2362. switch (codec->preset->id) {
  2363. case 0x10de0002:
  2364. case 0x10de0003:
  2365. case 0x10de0005:
  2366. case 0x10de0006:
  2367. chmap->channel_mask = (1U << 2) | (1U << 8);
  2368. break;
  2369. case 0x10de0007:
  2370. chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
  2371. }
  2372. return 0;
  2373. }
  2374. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  2375. {
  2376. struct hdmi_spec *spec;
  2377. int err = patch_nvhdmi_2ch(codec);
  2378. if (err < 0)
  2379. return err;
  2380. spec = codec->spec;
  2381. spec->multiout.max_channels = 8;
  2382. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  2383. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  2384. codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
  2385. codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
  2386. /* Initialize the audio infoframe channel mask and checksum to something
  2387. * valid */
  2388. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2389. return 0;
  2390. }
  2391. /*
  2392. * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
  2393. * - 0x10de0015
  2394. * - 0x10de0040
  2395. */
  2396. static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  2397. int channels)
  2398. {
  2399. if (cap->ca_index == 0x00 && channels == 2)
  2400. return SNDRV_CTL_TLVT_CHMAP_FIXED;
  2401. return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
  2402. }
  2403. static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
  2404. {
  2405. if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
  2406. return -EINVAL;
  2407. return 0;
  2408. }
  2409. static int patch_nvhdmi(struct hda_codec *codec)
  2410. {
  2411. struct hdmi_spec *spec;
  2412. int err;
  2413. err = patch_generic_hdmi(codec);
  2414. if (err)
  2415. return err;
  2416. spec = codec->spec;
  2417. spec->ops.chmap_cea_alloc_validate_get_type =
  2418. nvhdmi_chmap_cea_alloc_validate_get_type;
  2419. spec->ops.chmap_validate = nvhdmi_chmap_validate;
  2420. return 0;
  2421. }
  2422. /*
  2423. * ATI/AMD-specific implementations
  2424. */
  2425. #define is_amdhdmi_rev3_or_later(codec) \
  2426. ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
  2427. #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
  2428. /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
  2429. #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
  2430. #define ATI_VERB_SET_DOWNMIX_INFO 0x772
  2431. #define ATI_VERB_SET_MULTICHANNEL_01 0x777
  2432. #define ATI_VERB_SET_MULTICHANNEL_23 0x778
  2433. #define ATI_VERB_SET_MULTICHANNEL_45 0x779
  2434. #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
  2435. #define ATI_VERB_SET_HBR_CONTROL 0x77c
  2436. #define ATI_VERB_SET_MULTICHANNEL_1 0x785
  2437. #define ATI_VERB_SET_MULTICHANNEL_3 0x786
  2438. #define ATI_VERB_SET_MULTICHANNEL_5 0x787
  2439. #define ATI_VERB_SET_MULTICHANNEL_7 0x788
  2440. #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
  2441. #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
  2442. #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
  2443. #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
  2444. #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
  2445. #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
  2446. #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
  2447. #define ATI_VERB_GET_HBR_CONTROL 0xf7c
  2448. #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
  2449. #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
  2450. #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
  2451. #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
  2452. #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
  2453. /* AMD specific HDA cvt verbs */
  2454. #define ATI_VERB_SET_RAMP_RATE 0x770
  2455. #define ATI_VERB_GET_RAMP_RATE 0xf70
  2456. #define ATI_OUT_ENABLE 0x1
  2457. #define ATI_MULTICHANNEL_MODE_PAIRED 0
  2458. #define ATI_MULTICHANNEL_MODE_SINGLE 1
  2459. #define ATI_HBR_CAPABLE 0x01
  2460. #define ATI_HBR_ENABLE 0x10
  2461. static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
  2462. unsigned char *buf, int *eld_size)
  2463. {
  2464. /* call hda_eld.c ATI/AMD-specific function */
  2465. return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
  2466. is_amdhdmi_rev3_or_later(codec));
  2467. }
  2468. static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
  2469. int active_channels, int conn_type)
  2470. {
  2471. snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
  2472. }
  2473. static int atihdmi_paired_swap_fc_lfe(int pos)
  2474. {
  2475. /*
  2476. * ATI/AMD have automatic FC/LFE swap built-in
  2477. * when in pairwise mapping mode.
  2478. */
  2479. switch (pos) {
  2480. /* see channel_allocations[].speakers[] */
  2481. case 2: return 3;
  2482. case 3: return 2;
  2483. default: break;
  2484. }
  2485. return pos;
  2486. }
  2487. static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
  2488. {
  2489. struct cea_channel_speaker_allocation *cap;
  2490. int i, j;
  2491. /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
  2492. cap = &channel_allocations[get_channel_allocation_order(ca)];
  2493. for (i = 0; i < chs; ++i) {
  2494. int mask = to_spk_mask(map[i]);
  2495. bool ok = false;
  2496. bool companion_ok = false;
  2497. if (!mask)
  2498. continue;
  2499. for (j = 0 + i % 2; j < 8; j += 2) {
  2500. int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
  2501. if (cap->speakers[chan_idx] == mask) {
  2502. /* channel is in a supported position */
  2503. ok = true;
  2504. if (i % 2 == 0 && i + 1 < chs) {
  2505. /* even channel, check the odd companion */
  2506. int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
  2507. int comp_mask_req = to_spk_mask(map[i+1]);
  2508. int comp_mask_act = cap->speakers[comp_chan_idx];
  2509. if (comp_mask_req == comp_mask_act)
  2510. companion_ok = true;
  2511. else
  2512. return -EINVAL;
  2513. }
  2514. break;
  2515. }
  2516. }
  2517. if (!ok)
  2518. return -EINVAL;
  2519. if (companion_ok)
  2520. i++; /* companion channel already checked */
  2521. }
  2522. return 0;
  2523. }
  2524. static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  2525. int hdmi_slot, int stream_channel)
  2526. {
  2527. int verb;
  2528. int ati_channel_setup = 0;
  2529. if (hdmi_slot > 7)
  2530. return -EINVAL;
  2531. if (!has_amd_full_remap_support(codec)) {
  2532. hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
  2533. /* In case this is an odd slot but without stream channel, do not
  2534. * disable the slot since the corresponding even slot could have a
  2535. * channel. In case neither have a channel, the slot pair will be
  2536. * disabled when this function is called for the even slot. */
  2537. if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
  2538. return 0;
  2539. hdmi_slot -= hdmi_slot % 2;
  2540. if (stream_channel != 0xf)
  2541. stream_channel -= stream_channel % 2;
  2542. }
  2543. verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
  2544. /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
  2545. if (stream_channel != 0xf)
  2546. ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
  2547. return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
  2548. }
  2549. static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  2550. int asp_slot)
  2551. {
  2552. bool was_odd = false;
  2553. int ati_asp_slot = asp_slot;
  2554. int verb;
  2555. int ati_channel_setup;
  2556. if (asp_slot > 7)
  2557. return -EINVAL;
  2558. if (!has_amd_full_remap_support(codec)) {
  2559. ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
  2560. if (ati_asp_slot % 2 != 0) {
  2561. ati_asp_slot -= 1;
  2562. was_odd = true;
  2563. }
  2564. }
  2565. verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
  2566. ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
  2567. if (!(ati_channel_setup & ATI_OUT_ENABLE))
  2568. return 0xf;
  2569. return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
  2570. }
  2571. static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  2572. int channels)
  2573. {
  2574. int c;
  2575. /*
  2576. * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
  2577. * we need to take that into account (a single channel may take 2
  2578. * channel slots if we need to carry a silent channel next to it).
  2579. * On Rev3+ AMD codecs this function is not used.
  2580. */
  2581. int chanpairs = 0;
  2582. /* We only produce even-numbered channel count TLVs */
  2583. if ((channels % 2) != 0)
  2584. return -1;
  2585. for (c = 0; c < 7; c += 2) {
  2586. if (cap->speakers[c] || cap->speakers[c+1])
  2587. chanpairs++;
  2588. }
  2589. if (chanpairs * 2 != channels)
  2590. return -1;
  2591. return SNDRV_CTL_TLVT_CHMAP_PAIRED;
  2592. }
  2593. static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
  2594. unsigned int *chmap, int channels)
  2595. {
  2596. /* produce paired maps for pre-rev3 ATI/AMD codecs */
  2597. int count = 0;
  2598. int c;
  2599. for (c = 7; c >= 0; c--) {
  2600. int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
  2601. int spk = cap->speakers[chan];
  2602. if (!spk) {
  2603. /* add N/A channel if the companion channel is occupied */
  2604. if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
  2605. chmap[count++] = SNDRV_CHMAP_NA;
  2606. continue;
  2607. }
  2608. chmap[count++] = spk_to_chmap(spk);
  2609. }
  2610. WARN_ON(count != channels);
  2611. }
  2612. static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  2613. bool hbr)
  2614. {
  2615. int hbr_ctl, hbr_ctl_new;
  2616. hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
  2617. if (hbr_ctl & ATI_HBR_CAPABLE) {
  2618. if (hbr)
  2619. hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
  2620. else
  2621. hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
  2622. snd_printdd("atihdmi_pin_hbr_setup: "
  2623. "NID=0x%x, %shbr-ctl=0x%x\n",
  2624. pin_nid,
  2625. hbr_ctl == hbr_ctl_new ? "" : "new-",
  2626. hbr_ctl_new);
  2627. if (hbr_ctl != hbr_ctl_new)
  2628. snd_hda_codec_write(codec, pin_nid, 0,
  2629. ATI_VERB_SET_HBR_CONTROL,
  2630. hbr_ctl_new);
  2631. } else if (hbr)
  2632. return -EINVAL;
  2633. return 0;
  2634. }
  2635. static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  2636. hda_nid_t pin_nid, u32 stream_tag, int format)
  2637. {
  2638. if (is_amdhdmi_rev3_or_later(codec)) {
  2639. int ramp_rate = 180; /* default as per AMD spec */
  2640. /* disable ramp-up/down for non-pcm as per AMD spec */
  2641. if (format & AC_FMT_TYPE_NON_PCM)
  2642. ramp_rate = 0;
  2643. snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
  2644. }
  2645. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  2646. }
  2647. static int atihdmi_init(struct hda_codec *codec)
  2648. {
  2649. struct hdmi_spec *spec = codec->spec;
  2650. int pin_idx, err;
  2651. err = generic_hdmi_init(codec);
  2652. if (err)
  2653. return err;
  2654. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2655. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2656. /* make sure downmix information in infoframe is zero */
  2657. snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
  2658. /* enable channel-wise remap mode if supported */
  2659. if (has_amd_full_remap_support(codec))
  2660. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  2661. ATI_VERB_SET_MULTICHANNEL_MODE,
  2662. ATI_MULTICHANNEL_MODE_SINGLE);
  2663. }
  2664. return 0;
  2665. }
  2666. static int patch_atihdmi(struct hda_codec *codec)
  2667. {
  2668. struct hdmi_spec *spec;
  2669. struct hdmi_spec_per_cvt *per_cvt;
  2670. int err, cvt_idx;
  2671. err = patch_generic_hdmi(codec);
  2672. if (err)
  2673. return err;
  2674. codec->patch_ops.init = atihdmi_init;
  2675. spec = codec->spec;
  2676. spec->ops.pin_get_eld = atihdmi_pin_get_eld;
  2677. spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
  2678. spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
  2679. spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
  2680. spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
  2681. spec->ops.setup_stream = atihdmi_setup_stream;
  2682. if (!has_amd_full_remap_support(codec)) {
  2683. /* override to ATI/AMD-specific versions with pairwise mapping */
  2684. spec->ops.chmap_cea_alloc_validate_get_type =
  2685. atihdmi_paired_chmap_cea_alloc_validate_get_type;
  2686. spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
  2687. spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
  2688. }
  2689. /* ATI/AMD converters do not advertise all of their capabilities */
  2690. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  2691. per_cvt = get_cvt(spec, cvt_idx);
  2692. per_cvt->channels_max = max(per_cvt->channels_max, 8u);
  2693. per_cvt->rates |= SUPPORTED_RATES;
  2694. per_cvt->formats |= SUPPORTED_FORMATS;
  2695. per_cvt->maxbps = max(per_cvt->maxbps, 24u);
  2696. }
  2697. spec->channels_max = max(spec->channels_max, 8u);
  2698. return 0;
  2699. }
  2700. /* VIA HDMI Implementation */
  2701. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  2702. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  2703. static int patch_via_hdmi(struct hda_codec *codec)
  2704. {
  2705. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  2706. }
  2707. /*
  2708. * patch entries
  2709. */
  2710. static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
  2711. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2712. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  2713. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  2714. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
  2715. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  2716. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  2717. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  2718. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2719. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2720. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2721. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  2722. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  2723. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
  2724. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
  2725. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
  2726. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
  2727. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
  2728. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
  2729. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
  2730. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
  2731. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
  2732. { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
  2733. { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
  2734. /* 17 is known to be absent */
  2735. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
  2736. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
  2737. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
  2738. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
  2739. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
  2740. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
  2741. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
  2742. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
  2743. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
  2744. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
  2745. { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
  2746. { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
  2747. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  2748. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  2749. { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2750. { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  2751. { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2752. { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  2753. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2754. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  2755. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  2756. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  2757. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  2758. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  2759. { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
  2760. { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
  2761. { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
  2762. { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
  2763. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  2764. {} /* terminator */
  2765. };
  2766. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  2767. MODULE_ALIAS("snd-hda-codec-id:10027919");
  2768. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  2769. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  2770. MODULE_ALIAS("snd-hda-codec-id:10951390");
  2771. MODULE_ALIAS("snd-hda-codec-id:10951392");
  2772. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  2773. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  2774. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  2775. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  2776. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  2777. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  2778. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  2779. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  2780. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  2781. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  2782. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  2783. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  2784. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  2785. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  2786. MODULE_ALIAS("snd-hda-codec-id:10de0015");
  2787. MODULE_ALIAS("snd-hda-codec-id:10de0016");
  2788. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  2789. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  2790. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  2791. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  2792. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  2793. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  2794. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  2795. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  2796. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  2797. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  2798. MODULE_ALIAS("snd-hda-codec-id:10de0051");
  2799. MODULE_ALIAS("snd-hda-codec-id:10de0060");
  2800. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  2801. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  2802. MODULE_ALIAS("snd-hda-codec-id:11069f80");
  2803. MODULE_ALIAS("snd-hda-codec-id:11069f81");
  2804. MODULE_ALIAS("snd-hda-codec-id:11069f84");
  2805. MODULE_ALIAS("snd-hda-codec-id:11069f85");
  2806. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  2807. MODULE_ALIAS("snd-hda-codec-id:80860054");
  2808. MODULE_ALIAS("snd-hda-codec-id:80862801");
  2809. MODULE_ALIAS("snd-hda-codec-id:80862802");
  2810. MODULE_ALIAS("snd-hda-codec-id:80862803");
  2811. MODULE_ALIAS("snd-hda-codec-id:80862804");
  2812. MODULE_ALIAS("snd-hda-codec-id:80862805");
  2813. MODULE_ALIAS("snd-hda-codec-id:80862806");
  2814. MODULE_ALIAS("snd-hda-codec-id:80862807");
  2815. MODULE_ALIAS("snd-hda-codec-id:80862880");
  2816. MODULE_ALIAS("snd-hda-codec-id:80862882");
  2817. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  2818. MODULE_LICENSE("GPL");
  2819. MODULE_DESCRIPTION("HDMI HD-audio codec");
  2820. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  2821. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  2822. MODULE_ALIAS("snd-hda-codec-atihdmi");
  2823. static struct hda_codec_preset_list intel_list = {
  2824. .preset = snd_hda_preset_hdmi,
  2825. .owner = THIS_MODULE,
  2826. };
  2827. static int __init patch_hdmi_init(void)
  2828. {
  2829. return snd_hda_add_codec_preset(&intel_list);
  2830. }
  2831. static void __exit patch_hdmi_exit(void)
  2832. {
  2833. snd_hda_delete_codec_preset(&intel_list);
  2834. }
  2835. module_init(patch_hdmi_init)
  2836. module_exit(patch_hdmi_exit)