mwl8k.c 96 KB

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  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/list.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/etherdevice.h>
  21. #include <net/mac80211.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/firmware.h>
  24. #include <linux/workqueue.h>
  25. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  26. #define MWL8K_NAME KBUILD_MODNAME
  27. #define MWL8K_VERSION "0.11"
  28. /* Register definitions */
  29. #define MWL8K_HIU_GEN_PTR 0x00000c10
  30. #define MWL8K_MODE_STA 0x0000005a
  31. #define MWL8K_MODE_AP 0x000000a5
  32. #define MWL8K_HIU_INT_CODE 0x00000c14
  33. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  34. #define MWL8K_FWAP_READY 0xf1f2f4a5
  35. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  36. #define MWL8K_HIU_SCRATCH 0x00000c40
  37. /* Host->device communications */
  38. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  39. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  40. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  41. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  42. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  43. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  44. #define MWL8K_H2A_INT_RESET (1 << 15)
  45. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  46. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  47. /* Device->host communications */
  48. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  49. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  50. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  51. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  52. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  53. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  54. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  55. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  56. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  57. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  58. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  59. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  60. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  61. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  62. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  63. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  64. MWL8K_A2H_INT_CHNL_SWITCHED | \
  65. MWL8K_A2H_INT_QUEUE_EMPTY | \
  66. MWL8K_A2H_INT_RADAR_DETECT | \
  67. MWL8K_A2H_INT_RADIO_ON | \
  68. MWL8K_A2H_INT_RADIO_OFF | \
  69. MWL8K_A2H_INT_MAC_EVENT | \
  70. MWL8K_A2H_INT_OPC_DONE | \
  71. MWL8K_A2H_INT_RX_READY | \
  72. MWL8K_A2H_INT_TX_DONE)
  73. #define MWL8K_RX_QUEUES 1
  74. #define MWL8K_TX_QUEUES 4
  75. struct rxd_ops {
  76. int rxd_size;
  77. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  78. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  79. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  80. __le16 *qos);
  81. };
  82. struct mwl8k_device_info {
  83. char *part_name;
  84. char *helper_image;
  85. char *fw_image;
  86. struct rxd_ops *ap_rxd_ops;
  87. };
  88. struct mwl8k_rx_queue {
  89. int rxd_count;
  90. /* hw receives here */
  91. int head;
  92. /* refill descs here */
  93. int tail;
  94. void *rxd;
  95. dma_addr_t rxd_dma;
  96. struct {
  97. struct sk_buff *skb;
  98. DECLARE_PCI_UNMAP_ADDR(dma)
  99. } *buf;
  100. };
  101. struct mwl8k_tx_queue {
  102. /* hw transmits here */
  103. int head;
  104. /* sw appends here */
  105. int tail;
  106. struct ieee80211_tx_queue_stats stats;
  107. struct mwl8k_tx_desc *txd;
  108. dma_addr_t txd_dma;
  109. struct sk_buff **skb;
  110. };
  111. struct mwl8k_priv {
  112. struct ieee80211_hw *hw;
  113. struct pci_dev *pdev;
  114. struct mwl8k_device_info *device_info;
  115. void __iomem *sram;
  116. void __iomem *regs;
  117. /* firmware */
  118. struct firmware *fw_helper;
  119. struct firmware *fw_ucode;
  120. /* hardware/firmware parameters */
  121. bool ap_fw;
  122. struct rxd_ops *rxd_ops;
  123. /* firmware access */
  124. struct mutex fw_mutex;
  125. struct task_struct *fw_mutex_owner;
  126. int fw_mutex_depth;
  127. struct completion *hostcmd_wait;
  128. /* lock held over TX and TX reap */
  129. spinlock_t tx_lock;
  130. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  131. struct completion *tx_wait;
  132. struct ieee80211_vif *vif;
  133. struct ieee80211_channel *current_channel;
  134. /* power management status cookie from firmware */
  135. u32 *cookie;
  136. dma_addr_t cookie_dma;
  137. u16 num_mcaddrs;
  138. u8 hw_rev;
  139. u32 fw_rev;
  140. /*
  141. * Running count of TX packets in flight, to avoid
  142. * iterating over the transmit rings each time.
  143. */
  144. int pending_tx_pkts;
  145. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  146. struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
  147. /* PHY parameters */
  148. struct ieee80211_supported_band band;
  149. struct ieee80211_channel channels[14];
  150. struct ieee80211_rate rates[14];
  151. bool radio_on;
  152. bool radio_short_preamble;
  153. bool sniffer_enabled;
  154. bool wmm_enabled;
  155. struct work_struct sta_notify_worker;
  156. spinlock_t sta_notify_list_lock;
  157. struct list_head sta_notify_list;
  158. /* XXX need to convert this to handle multiple interfaces */
  159. bool capture_beacon;
  160. u8 capture_bssid[ETH_ALEN];
  161. struct sk_buff *beacon_skb;
  162. /*
  163. * This FJ worker has to be global as it is scheduled from the
  164. * RX handler. At this point we don't know which interface it
  165. * belongs to until the list of bssids waiting to complete join
  166. * is checked.
  167. */
  168. struct work_struct finalize_join_worker;
  169. /* Tasklet to reclaim TX descriptors and buffers after tx */
  170. struct tasklet_struct tx_reclaim_task;
  171. };
  172. /* Per interface specific private data */
  173. struct mwl8k_vif {
  174. /* Non AMPDU sequence number assigned by driver. */
  175. u16 seqno;
  176. };
  177. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  178. struct mwl8k_sta {
  179. /* Index into station database. Returned by UPDATE_STADB. */
  180. u8 peer_id;
  181. };
  182. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  183. static const struct ieee80211_channel mwl8k_channels[] = {
  184. { .center_freq = 2412, .hw_value = 1, },
  185. { .center_freq = 2417, .hw_value = 2, },
  186. { .center_freq = 2422, .hw_value = 3, },
  187. { .center_freq = 2427, .hw_value = 4, },
  188. { .center_freq = 2432, .hw_value = 5, },
  189. { .center_freq = 2437, .hw_value = 6, },
  190. { .center_freq = 2442, .hw_value = 7, },
  191. { .center_freq = 2447, .hw_value = 8, },
  192. { .center_freq = 2452, .hw_value = 9, },
  193. { .center_freq = 2457, .hw_value = 10, },
  194. { .center_freq = 2462, .hw_value = 11, },
  195. { .center_freq = 2467, .hw_value = 12, },
  196. { .center_freq = 2472, .hw_value = 13, },
  197. { .center_freq = 2484, .hw_value = 14, },
  198. };
  199. static const struct ieee80211_rate mwl8k_rates[] = {
  200. { .bitrate = 10, .hw_value = 2, },
  201. { .bitrate = 20, .hw_value = 4, },
  202. { .bitrate = 55, .hw_value = 11, },
  203. { .bitrate = 110, .hw_value = 22, },
  204. { .bitrate = 220, .hw_value = 44, },
  205. { .bitrate = 60, .hw_value = 12, },
  206. { .bitrate = 90, .hw_value = 18, },
  207. { .bitrate = 120, .hw_value = 24, },
  208. { .bitrate = 180, .hw_value = 36, },
  209. { .bitrate = 240, .hw_value = 48, },
  210. { .bitrate = 360, .hw_value = 72, },
  211. { .bitrate = 480, .hw_value = 96, },
  212. { .bitrate = 540, .hw_value = 108, },
  213. { .bitrate = 720, .hw_value = 144, },
  214. };
  215. /* Set or get info from Firmware */
  216. #define MWL8K_CMD_SET 0x0001
  217. #define MWL8K_CMD_GET 0x0000
  218. /* Firmware command codes */
  219. #define MWL8K_CMD_CODE_DNLD 0x0001
  220. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  221. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  222. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  223. #define MWL8K_CMD_GET_STAT 0x0014
  224. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  225. #define MWL8K_CMD_RF_TX_POWER 0x001e
  226. #define MWL8K_CMD_RF_ANTENNA 0x0020
  227. #define MWL8K_CMD_SET_BEACON 0x0100
  228. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  229. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  230. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  231. #define MWL8K_CMD_SET_AID 0x010d
  232. #define MWL8K_CMD_SET_RATE 0x0110
  233. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  234. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  235. #define MWL8K_CMD_SET_SLOT 0x0114
  236. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  237. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  238. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  239. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  240. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  241. #define MWL8K_CMD_SET_MAC_ADDR 0x0202
  242. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  243. #define MWL8K_CMD_BSS_START 0x1100
  244. #define MWL8K_CMD_SET_NEW_STN 0x1111
  245. #define MWL8K_CMD_UPDATE_STADB 0x1123
  246. static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
  247. {
  248. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  249. snprintf(buf, bufsize, "%s", #x);\
  250. return buf;\
  251. } while (0)
  252. switch (cmd & ~0x8000) {
  253. MWL8K_CMDNAME(CODE_DNLD);
  254. MWL8K_CMDNAME(GET_HW_SPEC);
  255. MWL8K_CMDNAME(SET_HW_SPEC);
  256. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  257. MWL8K_CMDNAME(GET_STAT);
  258. MWL8K_CMDNAME(RADIO_CONTROL);
  259. MWL8K_CMDNAME(RF_TX_POWER);
  260. MWL8K_CMDNAME(RF_ANTENNA);
  261. MWL8K_CMDNAME(SET_BEACON);
  262. MWL8K_CMDNAME(SET_PRE_SCAN);
  263. MWL8K_CMDNAME(SET_POST_SCAN);
  264. MWL8K_CMDNAME(SET_RF_CHANNEL);
  265. MWL8K_CMDNAME(SET_AID);
  266. MWL8K_CMDNAME(SET_RATE);
  267. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  268. MWL8K_CMDNAME(RTS_THRESHOLD);
  269. MWL8K_CMDNAME(SET_SLOT);
  270. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  271. MWL8K_CMDNAME(SET_WMM_MODE);
  272. MWL8K_CMDNAME(MIMO_CONFIG);
  273. MWL8K_CMDNAME(USE_FIXED_RATE);
  274. MWL8K_CMDNAME(ENABLE_SNIFFER);
  275. MWL8K_CMDNAME(SET_MAC_ADDR);
  276. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  277. MWL8K_CMDNAME(BSS_START);
  278. MWL8K_CMDNAME(SET_NEW_STN);
  279. MWL8K_CMDNAME(UPDATE_STADB);
  280. default:
  281. snprintf(buf, bufsize, "0x%x", cmd);
  282. }
  283. #undef MWL8K_CMDNAME
  284. return buf;
  285. }
  286. /* Hardware and firmware reset */
  287. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  288. {
  289. iowrite32(MWL8K_H2A_INT_RESET,
  290. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  291. iowrite32(MWL8K_H2A_INT_RESET,
  292. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  293. msleep(20);
  294. }
  295. /* Release fw image */
  296. static void mwl8k_release_fw(struct firmware **fw)
  297. {
  298. if (*fw == NULL)
  299. return;
  300. release_firmware(*fw);
  301. *fw = NULL;
  302. }
  303. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  304. {
  305. mwl8k_release_fw(&priv->fw_ucode);
  306. mwl8k_release_fw(&priv->fw_helper);
  307. }
  308. /* Request fw image */
  309. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  310. const char *fname, struct firmware **fw)
  311. {
  312. /* release current image */
  313. if (*fw != NULL)
  314. mwl8k_release_fw(fw);
  315. return request_firmware((const struct firmware **)fw,
  316. fname, &priv->pdev->dev);
  317. }
  318. static int mwl8k_request_firmware(struct mwl8k_priv *priv)
  319. {
  320. struct mwl8k_device_info *di = priv->device_info;
  321. int rc;
  322. if (di->helper_image != NULL) {
  323. rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
  324. if (rc) {
  325. printk(KERN_ERR "%s: Error requesting helper "
  326. "firmware file %s\n", pci_name(priv->pdev),
  327. di->helper_image);
  328. return rc;
  329. }
  330. }
  331. rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
  332. if (rc) {
  333. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  334. pci_name(priv->pdev), di->fw_image);
  335. mwl8k_release_fw(&priv->fw_helper);
  336. return rc;
  337. }
  338. return 0;
  339. }
  340. MODULE_FIRMWARE("mwl8k/helper_8687.fw");
  341. MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
  342. struct mwl8k_cmd_pkt {
  343. __le16 code;
  344. __le16 length;
  345. __le16 seq_num;
  346. __le16 result;
  347. char payload[0];
  348. } __attribute__((packed));
  349. /*
  350. * Firmware loading.
  351. */
  352. static int
  353. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  354. {
  355. void __iomem *regs = priv->regs;
  356. dma_addr_t dma_addr;
  357. int loops;
  358. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  359. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  360. return -ENOMEM;
  361. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  362. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  363. iowrite32(MWL8K_H2A_INT_DOORBELL,
  364. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  365. iowrite32(MWL8K_H2A_INT_DUMMY,
  366. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  367. loops = 1000;
  368. do {
  369. u32 int_code;
  370. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  371. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  372. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  373. break;
  374. }
  375. cond_resched();
  376. udelay(1);
  377. } while (--loops);
  378. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  379. return loops ? 0 : -ETIMEDOUT;
  380. }
  381. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  382. const u8 *data, size_t length)
  383. {
  384. struct mwl8k_cmd_pkt *cmd;
  385. int done;
  386. int rc = 0;
  387. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  388. if (cmd == NULL)
  389. return -ENOMEM;
  390. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  391. cmd->seq_num = 0;
  392. cmd->result = 0;
  393. done = 0;
  394. while (length) {
  395. int block_size = length > 256 ? 256 : length;
  396. memcpy(cmd->payload, data + done, block_size);
  397. cmd->length = cpu_to_le16(block_size);
  398. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  399. sizeof(*cmd) + block_size);
  400. if (rc)
  401. break;
  402. done += block_size;
  403. length -= block_size;
  404. }
  405. if (!rc) {
  406. cmd->length = 0;
  407. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  408. }
  409. kfree(cmd);
  410. return rc;
  411. }
  412. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  413. const u8 *data, size_t length)
  414. {
  415. unsigned char *buffer;
  416. int may_continue, rc = 0;
  417. u32 done, prev_block_size;
  418. buffer = kmalloc(1024, GFP_KERNEL);
  419. if (buffer == NULL)
  420. return -ENOMEM;
  421. done = 0;
  422. prev_block_size = 0;
  423. may_continue = 1000;
  424. while (may_continue > 0) {
  425. u32 block_size;
  426. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  427. if (block_size & 1) {
  428. block_size &= ~1;
  429. may_continue--;
  430. } else {
  431. done += prev_block_size;
  432. length -= prev_block_size;
  433. }
  434. if (block_size > 1024 || block_size > length) {
  435. rc = -EOVERFLOW;
  436. break;
  437. }
  438. if (length == 0) {
  439. rc = 0;
  440. break;
  441. }
  442. if (block_size == 0) {
  443. rc = -EPROTO;
  444. may_continue--;
  445. udelay(1);
  446. continue;
  447. }
  448. prev_block_size = block_size;
  449. memcpy(buffer, data + done, block_size);
  450. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  451. if (rc)
  452. break;
  453. }
  454. if (!rc && length != 0)
  455. rc = -EREMOTEIO;
  456. kfree(buffer);
  457. return rc;
  458. }
  459. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  460. {
  461. struct mwl8k_priv *priv = hw->priv;
  462. struct firmware *fw = priv->fw_ucode;
  463. int rc;
  464. int loops;
  465. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
  466. struct firmware *helper = priv->fw_helper;
  467. if (helper == NULL) {
  468. printk(KERN_ERR "%s: helper image needed but none "
  469. "given\n", pci_name(priv->pdev));
  470. return -EINVAL;
  471. }
  472. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  473. if (rc) {
  474. printk(KERN_ERR "%s: unable to load firmware "
  475. "helper image\n", pci_name(priv->pdev));
  476. return rc;
  477. }
  478. msleep(5);
  479. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  480. } else {
  481. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  482. }
  483. if (rc) {
  484. printk(KERN_ERR "%s: unable to load firmware image\n",
  485. pci_name(priv->pdev));
  486. return rc;
  487. }
  488. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  489. loops = 500000;
  490. do {
  491. u32 ready_code;
  492. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  493. if (ready_code == MWL8K_FWAP_READY) {
  494. priv->ap_fw = 1;
  495. break;
  496. } else if (ready_code == MWL8K_FWSTA_READY) {
  497. priv->ap_fw = 0;
  498. break;
  499. }
  500. cond_resched();
  501. udelay(1);
  502. } while (--loops);
  503. return loops ? 0 : -ETIMEDOUT;
  504. }
  505. /* DMA header used by firmware and hardware. */
  506. struct mwl8k_dma_data {
  507. __le16 fwlen;
  508. struct ieee80211_hdr wh;
  509. char data[0];
  510. } __attribute__((packed));
  511. /* Routines to add/remove DMA header from skb. */
  512. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  513. {
  514. struct mwl8k_dma_data *tr;
  515. int hdrlen;
  516. tr = (struct mwl8k_dma_data *)skb->data;
  517. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  518. if (hdrlen != sizeof(tr->wh)) {
  519. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  520. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  521. *((__le16 *)(tr->data - 2)) = qos;
  522. } else {
  523. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  524. }
  525. }
  526. if (hdrlen != sizeof(*tr))
  527. skb_pull(skb, sizeof(*tr) - hdrlen);
  528. }
  529. static inline void mwl8k_add_dma_header(struct sk_buff *skb)
  530. {
  531. struct ieee80211_hdr *wh;
  532. int hdrlen;
  533. struct mwl8k_dma_data *tr;
  534. /*
  535. * Add a firmware DMA header; the firmware requires that we
  536. * present a 2-byte payload length followed by a 4-address
  537. * header (without QoS field), followed (optionally) by any
  538. * WEP/ExtIV header (but only filled in for CCMP).
  539. */
  540. wh = (struct ieee80211_hdr *)skb->data;
  541. hdrlen = ieee80211_hdrlen(wh->frame_control);
  542. if (hdrlen != sizeof(*tr))
  543. skb_push(skb, sizeof(*tr) - hdrlen);
  544. if (ieee80211_is_data_qos(wh->frame_control))
  545. hdrlen -= 2;
  546. tr = (struct mwl8k_dma_data *)skb->data;
  547. if (wh != &tr->wh)
  548. memmove(&tr->wh, wh, hdrlen);
  549. if (hdrlen != sizeof(tr->wh))
  550. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  551. /*
  552. * Firmware length is the length of the fully formed "802.11
  553. * payload". That is, everything except for the 802.11 header.
  554. * This includes all crypto material including the MIC.
  555. */
  556. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
  557. }
  558. /*
  559. * Packet reception for 88w8366 AP firmware.
  560. */
  561. struct mwl8k_rxd_8366_ap {
  562. __le16 pkt_len;
  563. __u8 sq2;
  564. __u8 rate;
  565. __le32 pkt_phys_addr;
  566. __le32 next_rxd_phys_addr;
  567. __le16 qos_control;
  568. __le16 htsig2;
  569. __le32 hw_rssi_info;
  570. __le32 hw_noise_floor_info;
  571. __u8 noise_floor;
  572. __u8 pad0[3];
  573. __u8 rssi;
  574. __u8 rx_status;
  575. __u8 channel;
  576. __u8 rx_ctrl;
  577. } __attribute__((packed));
  578. #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
  579. #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
  580. #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  581. #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
  582. static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  583. {
  584. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  585. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  586. rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
  587. }
  588. static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
  589. {
  590. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  591. rxd->pkt_len = cpu_to_le16(len);
  592. rxd->pkt_phys_addr = cpu_to_le32(addr);
  593. wmb();
  594. rxd->rx_ctrl = 0;
  595. }
  596. static int
  597. mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  598. __le16 *qos)
  599. {
  600. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  601. if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
  602. return -1;
  603. rmb();
  604. memset(status, 0, sizeof(*status));
  605. status->signal = -rxd->rssi;
  606. status->noise = -rxd->noise_floor;
  607. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
  608. status->flag |= RX_FLAG_HT;
  609. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
  610. status->flag |= RX_FLAG_40MHZ;
  611. status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
  612. } else {
  613. int i;
  614. for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
  615. if (mwl8k_rates[i].hw_value == rxd->rate) {
  616. status->rate_idx = i;
  617. break;
  618. }
  619. }
  620. }
  621. status->band = IEEE80211_BAND_2GHZ;
  622. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  623. *qos = rxd->qos_control;
  624. return le16_to_cpu(rxd->pkt_len);
  625. }
  626. static struct rxd_ops rxd_8366_ap_ops = {
  627. .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
  628. .rxd_init = mwl8k_rxd_8366_ap_init,
  629. .rxd_refill = mwl8k_rxd_8366_ap_refill,
  630. .rxd_process = mwl8k_rxd_8366_ap_process,
  631. };
  632. /*
  633. * Packet reception for STA firmware.
  634. */
  635. struct mwl8k_rxd_sta {
  636. __le16 pkt_len;
  637. __u8 link_quality;
  638. __u8 noise_level;
  639. __le32 pkt_phys_addr;
  640. __le32 next_rxd_phys_addr;
  641. __le16 qos_control;
  642. __le16 rate_info;
  643. __le32 pad0[4];
  644. __u8 rssi;
  645. __u8 channel;
  646. __le16 pad1;
  647. __u8 rx_ctrl;
  648. __u8 rx_status;
  649. __u8 pad2[2];
  650. } __attribute__((packed));
  651. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  652. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  653. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  654. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  655. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  656. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  657. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  658. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  659. {
  660. struct mwl8k_rxd_sta *rxd = _rxd;
  661. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  662. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  663. }
  664. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  665. {
  666. struct mwl8k_rxd_sta *rxd = _rxd;
  667. rxd->pkt_len = cpu_to_le16(len);
  668. rxd->pkt_phys_addr = cpu_to_le32(addr);
  669. wmb();
  670. rxd->rx_ctrl = 0;
  671. }
  672. static int
  673. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  674. __le16 *qos)
  675. {
  676. struct mwl8k_rxd_sta *rxd = _rxd;
  677. u16 rate_info;
  678. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  679. return -1;
  680. rmb();
  681. rate_info = le16_to_cpu(rxd->rate_info);
  682. memset(status, 0, sizeof(*status));
  683. status->signal = -rxd->rssi;
  684. status->noise = -rxd->noise_level;
  685. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  686. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  687. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  688. status->flag |= RX_FLAG_SHORTPRE;
  689. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  690. status->flag |= RX_FLAG_40MHZ;
  691. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  692. status->flag |= RX_FLAG_SHORT_GI;
  693. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  694. status->flag |= RX_FLAG_HT;
  695. status->band = IEEE80211_BAND_2GHZ;
  696. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  697. *qos = rxd->qos_control;
  698. return le16_to_cpu(rxd->pkt_len);
  699. }
  700. static struct rxd_ops rxd_sta_ops = {
  701. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  702. .rxd_init = mwl8k_rxd_sta_init,
  703. .rxd_refill = mwl8k_rxd_sta_refill,
  704. .rxd_process = mwl8k_rxd_sta_process,
  705. };
  706. #define MWL8K_RX_DESCS 256
  707. #define MWL8K_RX_MAXSZ 3800
  708. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  709. {
  710. struct mwl8k_priv *priv = hw->priv;
  711. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  712. int size;
  713. int i;
  714. rxq->rxd_count = 0;
  715. rxq->head = 0;
  716. rxq->tail = 0;
  717. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  718. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  719. if (rxq->rxd == NULL) {
  720. printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
  721. wiphy_name(hw->wiphy));
  722. return -ENOMEM;
  723. }
  724. memset(rxq->rxd, 0, size);
  725. rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
  726. if (rxq->buf == NULL) {
  727. printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
  728. wiphy_name(hw->wiphy));
  729. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  730. return -ENOMEM;
  731. }
  732. memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
  733. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  734. int desc_size;
  735. void *rxd;
  736. int nexti;
  737. dma_addr_t next_dma_addr;
  738. desc_size = priv->rxd_ops->rxd_size;
  739. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  740. nexti = i + 1;
  741. if (nexti == MWL8K_RX_DESCS)
  742. nexti = 0;
  743. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  744. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  745. }
  746. return 0;
  747. }
  748. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  749. {
  750. struct mwl8k_priv *priv = hw->priv;
  751. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  752. int refilled;
  753. refilled = 0;
  754. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  755. struct sk_buff *skb;
  756. dma_addr_t addr;
  757. int rx;
  758. void *rxd;
  759. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  760. if (skb == NULL)
  761. break;
  762. addr = pci_map_single(priv->pdev, skb->data,
  763. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  764. rxq->rxd_count++;
  765. rx = rxq->tail++;
  766. if (rxq->tail == MWL8K_RX_DESCS)
  767. rxq->tail = 0;
  768. rxq->buf[rx].skb = skb;
  769. pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
  770. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  771. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  772. refilled++;
  773. }
  774. return refilled;
  775. }
  776. /* Must be called only when the card's reception is completely halted */
  777. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  778. {
  779. struct mwl8k_priv *priv = hw->priv;
  780. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  781. int i;
  782. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  783. if (rxq->buf[i].skb != NULL) {
  784. pci_unmap_single(priv->pdev,
  785. pci_unmap_addr(&rxq->buf[i], dma),
  786. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  787. pci_unmap_addr_set(&rxq->buf[i], dma, 0);
  788. kfree_skb(rxq->buf[i].skb);
  789. rxq->buf[i].skb = NULL;
  790. }
  791. }
  792. kfree(rxq->buf);
  793. rxq->buf = NULL;
  794. pci_free_consistent(priv->pdev,
  795. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  796. rxq->rxd, rxq->rxd_dma);
  797. rxq->rxd = NULL;
  798. }
  799. /*
  800. * Scan a list of BSSIDs to process for finalize join.
  801. * Allows for extension to process multiple BSSIDs.
  802. */
  803. static inline int
  804. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  805. {
  806. return priv->capture_beacon &&
  807. ieee80211_is_beacon(wh->frame_control) &&
  808. !compare_ether_addr(wh->addr3, priv->capture_bssid);
  809. }
  810. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  811. struct sk_buff *skb)
  812. {
  813. struct mwl8k_priv *priv = hw->priv;
  814. priv->capture_beacon = false;
  815. memset(priv->capture_bssid, 0, ETH_ALEN);
  816. /*
  817. * Use GFP_ATOMIC as rxq_process is called from
  818. * the primary interrupt handler, memory allocation call
  819. * must not sleep.
  820. */
  821. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  822. if (priv->beacon_skb != NULL)
  823. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  824. }
  825. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  826. {
  827. struct mwl8k_priv *priv = hw->priv;
  828. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  829. int processed;
  830. processed = 0;
  831. while (rxq->rxd_count && limit--) {
  832. struct sk_buff *skb;
  833. void *rxd;
  834. int pkt_len;
  835. struct ieee80211_rx_status status;
  836. __le16 qos;
  837. skb = rxq->buf[rxq->head].skb;
  838. if (skb == NULL)
  839. break;
  840. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  841. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
  842. if (pkt_len < 0)
  843. break;
  844. rxq->buf[rxq->head].skb = NULL;
  845. pci_unmap_single(priv->pdev,
  846. pci_unmap_addr(&rxq->buf[rxq->head], dma),
  847. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  848. pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  849. rxq->head++;
  850. if (rxq->head == MWL8K_RX_DESCS)
  851. rxq->head = 0;
  852. rxq->rxd_count--;
  853. skb_put(skb, pkt_len);
  854. mwl8k_remove_dma_header(skb, qos);
  855. /*
  856. * Check for a pending join operation. Save a
  857. * copy of the beacon and schedule a tasklet to
  858. * send a FINALIZE_JOIN command to the firmware.
  859. */
  860. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  861. mwl8k_save_beacon(hw, skb);
  862. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  863. ieee80211_rx_irqsafe(hw, skb);
  864. processed++;
  865. }
  866. return processed;
  867. }
  868. /*
  869. * Packet transmission.
  870. */
  871. #define MWL8K_TXD_STATUS_OK 0x00000001
  872. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  873. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  874. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  875. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  876. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  877. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  878. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  879. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  880. #define MWL8K_QOS_EOSP 0x0010
  881. struct mwl8k_tx_desc {
  882. __le32 status;
  883. __u8 data_rate;
  884. __u8 tx_priority;
  885. __le16 qos_control;
  886. __le32 pkt_phys_addr;
  887. __le16 pkt_len;
  888. __u8 dest_MAC_addr[ETH_ALEN];
  889. __le32 next_txd_phys_addr;
  890. __le32 reserved;
  891. __le16 rate_info;
  892. __u8 peer_id;
  893. __u8 tx_frag_cnt;
  894. } __attribute__((packed));
  895. #define MWL8K_TX_DESCS 128
  896. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  897. {
  898. struct mwl8k_priv *priv = hw->priv;
  899. struct mwl8k_tx_queue *txq = priv->txq + index;
  900. int size;
  901. int i;
  902. memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
  903. txq->stats.limit = MWL8K_TX_DESCS;
  904. txq->head = 0;
  905. txq->tail = 0;
  906. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  907. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  908. if (txq->txd == NULL) {
  909. printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
  910. wiphy_name(hw->wiphy));
  911. return -ENOMEM;
  912. }
  913. memset(txq->txd, 0, size);
  914. txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
  915. if (txq->skb == NULL) {
  916. printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
  917. wiphy_name(hw->wiphy));
  918. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  919. return -ENOMEM;
  920. }
  921. memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
  922. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  923. struct mwl8k_tx_desc *tx_desc;
  924. int nexti;
  925. tx_desc = txq->txd + i;
  926. nexti = (i + 1) % MWL8K_TX_DESCS;
  927. tx_desc->status = 0;
  928. tx_desc->next_txd_phys_addr =
  929. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  930. }
  931. return 0;
  932. }
  933. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  934. {
  935. iowrite32(MWL8K_H2A_INT_PPA_READY,
  936. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  937. iowrite32(MWL8K_H2A_INT_DUMMY,
  938. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  939. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  940. }
  941. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  942. {
  943. struct mwl8k_priv *priv = hw->priv;
  944. int i;
  945. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  946. struct mwl8k_tx_queue *txq = priv->txq + i;
  947. int fw_owned = 0;
  948. int drv_owned = 0;
  949. int unused = 0;
  950. int desc;
  951. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  952. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  953. u32 status;
  954. status = le32_to_cpu(tx_desc->status);
  955. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  956. fw_owned++;
  957. else
  958. drv_owned++;
  959. if (tx_desc->pkt_len == 0)
  960. unused++;
  961. }
  962. printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
  963. "fw_owned=%d drv_owned=%d unused=%d\n",
  964. wiphy_name(hw->wiphy), i,
  965. txq->stats.len, txq->head, txq->tail,
  966. fw_owned, drv_owned, unused);
  967. }
  968. }
  969. /*
  970. * Must be called with priv->fw_mutex held and tx queues stopped.
  971. */
  972. #define MWL8K_TX_WAIT_TIMEOUT_MS 5000
  973. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  974. {
  975. struct mwl8k_priv *priv = hw->priv;
  976. DECLARE_COMPLETION_ONSTACK(tx_wait);
  977. int retry;
  978. int rc;
  979. might_sleep();
  980. /*
  981. * The TX queues are stopped at this point, so this test
  982. * doesn't need to take ->tx_lock.
  983. */
  984. if (!priv->pending_tx_pkts)
  985. return 0;
  986. retry = 0;
  987. rc = 0;
  988. spin_lock_bh(&priv->tx_lock);
  989. priv->tx_wait = &tx_wait;
  990. while (!rc) {
  991. int oldcount;
  992. unsigned long timeout;
  993. oldcount = priv->pending_tx_pkts;
  994. spin_unlock_bh(&priv->tx_lock);
  995. timeout = wait_for_completion_timeout(&tx_wait,
  996. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  997. spin_lock_bh(&priv->tx_lock);
  998. if (timeout) {
  999. WARN_ON(priv->pending_tx_pkts);
  1000. if (retry) {
  1001. printk(KERN_NOTICE "%s: tx rings drained\n",
  1002. wiphy_name(hw->wiphy));
  1003. }
  1004. break;
  1005. }
  1006. if (priv->pending_tx_pkts < oldcount) {
  1007. printk(KERN_NOTICE "%s: waiting for tx rings "
  1008. "to drain (%d -> %d pkts)\n",
  1009. wiphy_name(hw->wiphy), oldcount,
  1010. priv->pending_tx_pkts);
  1011. retry = 1;
  1012. continue;
  1013. }
  1014. priv->tx_wait = NULL;
  1015. printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
  1016. wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
  1017. mwl8k_dump_tx_rings(hw);
  1018. rc = -ETIMEDOUT;
  1019. }
  1020. spin_unlock_bh(&priv->tx_lock);
  1021. return rc;
  1022. }
  1023. #define MWL8K_TXD_SUCCESS(status) \
  1024. ((status) & (MWL8K_TXD_STATUS_OK | \
  1025. MWL8K_TXD_STATUS_OK_RETRY | \
  1026. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1027. static int
  1028. mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
  1029. {
  1030. struct mwl8k_priv *priv = hw->priv;
  1031. struct mwl8k_tx_queue *txq = priv->txq + index;
  1032. int processed;
  1033. processed = 0;
  1034. while (txq->stats.len > 0 && limit--) {
  1035. int tx;
  1036. struct mwl8k_tx_desc *tx_desc;
  1037. unsigned long addr;
  1038. int size;
  1039. struct sk_buff *skb;
  1040. struct ieee80211_tx_info *info;
  1041. u32 status;
  1042. tx = txq->head;
  1043. tx_desc = txq->txd + tx;
  1044. status = le32_to_cpu(tx_desc->status);
  1045. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1046. if (!force)
  1047. break;
  1048. tx_desc->status &=
  1049. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1050. }
  1051. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1052. BUG_ON(txq->stats.len == 0);
  1053. txq->stats.len--;
  1054. priv->pending_tx_pkts--;
  1055. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1056. size = le16_to_cpu(tx_desc->pkt_len);
  1057. skb = txq->skb[tx];
  1058. txq->skb[tx] = NULL;
  1059. BUG_ON(skb == NULL);
  1060. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1061. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1062. /* Mark descriptor as unused */
  1063. tx_desc->pkt_phys_addr = 0;
  1064. tx_desc->pkt_len = 0;
  1065. info = IEEE80211_SKB_CB(skb);
  1066. ieee80211_tx_info_clear_status(info);
  1067. if (MWL8K_TXD_SUCCESS(status))
  1068. info->flags |= IEEE80211_TX_STAT_ACK;
  1069. ieee80211_tx_status_irqsafe(hw, skb);
  1070. processed++;
  1071. }
  1072. if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
  1073. ieee80211_wake_queue(hw, index);
  1074. return processed;
  1075. }
  1076. /* must be called only when the card's transmit is completely halted */
  1077. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1078. {
  1079. struct mwl8k_priv *priv = hw->priv;
  1080. struct mwl8k_tx_queue *txq = priv->txq + index;
  1081. mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
  1082. kfree(txq->skb);
  1083. txq->skb = NULL;
  1084. pci_free_consistent(priv->pdev,
  1085. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1086. txq->txd, txq->txd_dma);
  1087. txq->txd = NULL;
  1088. }
  1089. static int
  1090. mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
  1091. {
  1092. struct mwl8k_priv *priv = hw->priv;
  1093. struct ieee80211_tx_info *tx_info;
  1094. struct mwl8k_vif *mwl8k_vif;
  1095. struct ieee80211_hdr *wh;
  1096. struct mwl8k_tx_queue *txq;
  1097. struct mwl8k_tx_desc *tx;
  1098. dma_addr_t dma;
  1099. u32 txstatus;
  1100. u8 txdatarate;
  1101. u16 qos;
  1102. wh = (struct ieee80211_hdr *)skb->data;
  1103. if (ieee80211_is_data_qos(wh->frame_control))
  1104. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1105. else
  1106. qos = 0;
  1107. mwl8k_add_dma_header(skb);
  1108. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1109. tx_info = IEEE80211_SKB_CB(skb);
  1110. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1111. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1112. u16 seqno = mwl8k_vif->seqno;
  1113. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1114. wh->seq_ctrl |= cpu_to_le16(seqno << 4);
  1115. mwl8k_vif->seqno = seqno++ % 4096;
  1116. }
  1117. /* Setup firmware control bit fields for each frame type. */
  1118. txstatus = 0;
  1119. txdatarate = 0;
  1120. if (ieee80211_is_mgmt(wh->frame_control) ||
  1121. ieee80211_is_ctl(wh->frame_control)) {
  1122. txdatarate = 0;
  1123. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1124. } else if (ieee80211_is_data(wh->frame_control)) {
  1125. txdatarate = 1;
  1126. if (is_multicast_ether_addr(wh->addr1))
  1127. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1128. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1129. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1130. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1131. else
  1132. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1133. }
  1134. dma = pci_map_single(priv->pdev, skb->data,
  1135. skb->len, PCI_DMA_TODEVICE);
  1136. if (pci_dma_mapping_error(priv->pdev, dma)) {
  1137. printk(KERN_DEBUG "%s: failed to dma map skb, "
  1138. "dropping TX frame.\n", wiphy_name(hw->wiphy));
  1139. dev_kfree_skb(skb);
  1140. return NETDEV_TX_OK;
  1141. }
  1142. spin_lock_bh(&priv->tx_lock);
  1143. txq = priv->txq + index;
  1144. BUG_ON(txq->skb[txq->tail] != NULL);
  1145. txq->skb[txq->tail] = skb;
  1146. tx = txq->txd + txq->tail;
  1147. tx->data_rate = txdatarate;
  1148. tx->tx_priority = index;
  1149. tx->qos_control = cpu_to_le16(qos);
  1150. tx->pkt_phys_addr = cpu_to_le32(dma);
  1151. tx->pkt_len = cpu_to_le16(skb->len);
  1152. tx->rate_info = 0;
  1153. if (!priv->ap_fw && tx_info->control.sta != NULL)
  1154. tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
  1155. else
  1156. tx->peer_id = 0;
  1157. wmb();
  1158. tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
  1159. txq->stats.count++;
  1160. txq->stats.len++;
  1161. priv->pending_tx_pkts++;
  1162. txq->tail++;
  1163. if (txq->tail == MWL8K_TX_DESCS)
  1164. txq->tail = 0;
  1165. if (txq->head == txq->tail)
  1166. ieee80211_stop_queue(hw, index);
  1167. mwl8k_tx_start(priv);
  1168. spin_unlock_bh(&priv->tx_lock);
  1169. return NETDEV_TX_OK;
  1170. }
  1171. /*
  1172. * Firmware access.
  1173. *
  1174. * We have the following requirements for issuing firmware commands:
  1175. * - Some commands require that the packet transmit path is idle when
  1176. * the command is issued. (For simplicity, we'll just quiesce the
  1177. * transmit path for every command.)
  1178. * - There are certain sequences of commands that need to be issued to
  1179. * the hardware sequentially, with no other intervening commands.
  1180. *
  1181. * This leads to an implementation of a "firmware lock" as a mutex that
  1182. * can be taken recursively, and which is taken by both the low-level
  1183. * command submission function (mwl8k_post_cmd) as well as any users of
  1184. * that function that require issuing of an atomic sequence of commands,
  1185. * and quiesces the transmit path whenever it's taken.
  1186. */
  1187. static int mwl8k_fw_lock(struct ieee80211_hw *hw)
  1188. {
  1189. struct mwl8k_priv *priv = hw->priv;
  1190. if (priv->fw_mutex_owner != current) {
  1191. int rc;
  1192. mutex_lock(&priv->fw_mutex);
  1193. ieee80211_stop_queues(hw);
  1194. rc = mwl8k_tx_wait_empty(hw);
  1195. if (rc) {
  1196. ieee80211_wake_queues(hw);
  1197. mutex_unlock(&priv->fw_mutex);
  1198. return rc;
  1199. }
  1200. priv->fw_mutex_owner = current;
  1201. }
  1202. priv->fw_mutex_depth++;
  1203. return 0;
  1204. }
  1205. static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
  1206. {
  1207. struct mwl8k_priv *priv = hw->priv;
  1208. if (!--priv->fw_mutex_depth) {
  1209. ieee80211_wake_queues(hw);
  1210. priv->fw_mutex_owner = NULL;
  1211. mutex_unlock(&priv->fw_mutex);
  1212. }
  1213. }
  1214. /*
  1215. * Command processing.
  1216. */
  1217. /* Timeout firmware commands after 10s */
  1218. #define MWL8K_CMD_TIMEOUT_MS 10000
  1219. static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
  1220. {
  1221. DECLARE_COMPLETION_ONSTACK(cmd_wait);
  1222. struct mwl8k_priv *priv = hw->priv;
  1223. void __iomem *regs = priv->regs;
  1224. dma_addr_t dma_addr;
  1225. unsigned int dma_size;
  1226. int rc;
  1227. unsigned long timeout = 0;
  1228. u8 buf[32];
  1229. cmd->result = 0xffff;
  1230. dma_size = le16_to_cpu(cmd->length);
  1231. dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
  1232. PCI_DMA_BIDIRECTIONAL);
  1233. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  1234. return -ENOMEM;
  1235. rc = mwl8k_fw_lock(hw);
  1236. if (rc) {
  1237. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1238. PCI_DMA_BIDIRECTIONAL);
  1239. return rc;
  1240. }
  1241. priv->hostcmd_wait = &cmd_wait;
  1242. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  1243. iowrite32(MWL8K_H2A_INT_DOORBELL,
  1244. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1245. iowrite32(MWL8K_H2A_INT_DUMMY,
  1246. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1247. timeout = wait_for_completion_timeout(&cmd_wait,
  1248. msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
  1249. priv->hostcmd_wait = NULL;
  1250. mwl8k_fw_unlock(hw);
  1251. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1252. PCI_DMA_BIDIRECTIONAL);
  1253. if (!timeout) {
  1254. printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
  1255. wiphy_name(hw->wiphy),
  1256. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1257. MWL8K_CMD_TIMEOUT_MS);
  1258. rc = -ETIMEDOUT;
  1259. } else {
  1260. int ms;
  1261. ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
  1262. rc = cmd->result ? -EINVAL : 0;
  1263. if (rc)
  1264. printk(KERN_ERR "%s: Command %s error 0x%x\n",
  1265. wiphy_name(hw->wiphy),
  1266. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1267. le16_to_cpu(cmd->result));
  1268. else if (ms > 2000)
  1269. printk(KERN_NOTICE "%s: Command %s took %d ms\n",
  1270. wiphy_name(hw->wiphy),
  1271. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1272. ms);
  1273. }
  1274. return rc;
  1275. }
  1276. /*
  1277. * CMD_GET_HW_SPEC (STA version).
  1278. */
  1279. struct mwl8k_cmd_get_hw_spec_sta {
  1280. struct mwl8k_cmd_pkt header;
  1281. __u8 hw_rev;
  1282. __u8 host_interface;
  1283. __le16 num_mcaddrs;
  1284. __u8 perm_addr[ETH_ALEN];
  1285. __le16 region_code;
  1286. __le32 fw_rev;
  1287. __le32 ps_cookie;
  1288. __le32 caps;
  1289. __u8 mcs_bitmap[16];
  1290. __le32 rx_queue_ptr;
  1291. __le32 num_tx_queues;
  1292. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1293. __le32 caps2;
  1294. __le32 num_tx_desc_per_queue;
  1295. __le32 total_rxd;
  1296. } __attribute__((packed));
  1297. #define MWL8K_CAP_MAX_AMSDU 0x20000000
  1298. #define MWL8K_CAP_GREENFIELD 0x08000000
  1299. #define MWL8K_CAP_AMPDU 0x04000000
  1300. #define MWL8K_CAP_RX_STBC 0x01000000
  1301. #define MWL8K_CAP_TX_STBC 0x00800000
  1302. #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
  1303. #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
  1304. #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
  1305. #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
  1306. #define MWL8K_CAP_DELAY_BA 0x00003000
  1307. #define MWL8K_CAP_MIMO 0x00000200
  1308. #define MWL8K_CAP_40MHZ 0x00000100
  1309. static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
  1310. {
  1311. struct mwl8k_priv *priv = hw->priv;
  1312. int rx_streams;
  1313. int tx_streams;
  1314. priv->band.ht_cap.ht_supported = 1;
  1315. if (cap & MWL8K_CAP_MAX_AMSDU)
  1316. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  1317. if (cap & MWL8K_CAP_GREENFIELD)
  1318. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
  1319. if (cap & MWL8K_CAP_AMPDU) {
  1320. hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
  1321. priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1322. priv->band.ht_cap.ampdu_density =
  1323. IEEE80211_HT_MPDU_DENSITY_NONE;
  1324. }
  1325. if (cap & MWL8K_CAP_RX_STBC)
  1326. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
  1327. if (cap & MWL8K_CAP_TX_STBC)
  1328. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
  1329. if (cap & MWL8K_CAP_SHORTGI_40MHZ)
  1330. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
  1331. if (cap & MWL8K_CAP_SHORTGI_20MHZ)
  1332. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
  1333. if (cap & MWL8K_CAP_DELAY_BA)
  1334. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
  1335. if (cap & MWL8K_CAP_40MHZ)
  1336. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  1337. rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
  1338. tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
  1339. priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
  1340. if (rx_streams >= 2)
  1341. priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
  1342. if (rx_streams >= 3)
  1343. priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
  1344. priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
  1345. priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1346. if (rx_streams != tx_streams) {
  1347. priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  1348. priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
  1349. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1350. }
  1351. }
  1352. static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
  1353. {
  1354. struct mwl8k_priv *priv = hw->priv;
  1355. struct mwl8k_cmd_get_hw_spec_sta *cmd;
  1356. int rc;
  1357. int i;
  1358. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1359. if (cmd == NULL)
  1360. return -ENOMEM;
  1361. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1362. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1363. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1364. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1365. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1366. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1367. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1368. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1369. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1370. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1371. rc = mwl8k_post_cmd(hw, &cmd->header);
  1372. if (!rc) {
  1373. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1374. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1375. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1376. priv->hw_rev = cmd->hw_rev;
  1377. if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
  1378. mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
  1379. }
  1380. kfree(cmd);
  1381. return rc;
  1382. }
  1383. /*
  1384. * CMD_GET_HW_SPEC (AP version).
  1385. */
  1386. struct mwl8k_cmd_get_hw_spec_ap {
  1387. struct mwl8k_cmd_pkt header;
  1388. __u8 hw_rev;
  1389. __u8 host_interface;
  1390. __le16 num_wcb;
  1391. __le16 num_mcaddrs;
  1392. __u8 perm_addr[ETH_ALEN];
  1393. __le16 region_code;
  1394. __le16 num_antenna;
  1395. __le32 fw_rev;
  1396. __le32 wcbbase0;
  1397. __le32 rxwrptr;
  1398. __le32 rxrdptr;
  1399. __le32 ps_cookie;
  1400. __le32 wcbbase1;
  1401. __le32 wcbbase2;
  1402. __le32 wcbbase3;
  1403. } __attribute__((packed));
  1404. static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
  1405. {
  1406. struct mwl8k_priv *priv = hw->priv;
  1407. struct mwl8k_cmd_get_hw_spec_ap *cmd;
  1408. int rc;
  1409. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1410. if (cmd == NULL)
  1411. return -ENOMEM;
  1412. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1413. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1414. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1415. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1416. rc = mwl8k_post_cmd(hw, &cmd->header);
  1417. if (!rc) {
  1418. int off;
  1419. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1420. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1421. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1422. priv->hw_rev = cmd->hw_rev;
  1423. off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
  1424. iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
  1425. off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
  1426. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1427. off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
  1428. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1429. off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
  1430. iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
  1431. off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
  1432. iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
  1433. off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
  1434. iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
  1435. }
  1436. kfree(cmd);
  1437. return rc;
  1438. }
  1439. /*
  1440. * CMD_SET_HW_SPEC.
  1441. */
  1442. struct mwl8k_cmd_set_hw_spec {
  1443. struct mwl8k_cmd_pkt header;
  1444. __u8 hw_rev;
  1445. __u8 host_interface;
  1446. __le16 num_mcaddrs;
  1447. __u8 perm_addr[ETH_ALEN];
  1448. __le16 region_code;
  1449. __le32 fw_rev;
  1450. __le32 ps_cookie;
  1451. __le32 caps;
  1452. __le32 rx_queue_ptr;
  1453. __le32 num_tx_queues;
  1454. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1455. __le32 flags;
  1456. __le32 num_tx_desc_per_queue;
  1457. __le32 total_rxd;
  1458. } __attribute__((packed));
  1459. #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
  1460. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
  1461. #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
  1462. static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
  1463. {
  1464. struct mwl8k_priv *priv = hw->priv;
  1465. struct mwl8k_cmd_set_hw_spec *cmd;
  1466. int rc;
  1467. int i;
  1468. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1469. if (cmd == NULL)
  1470. return -ENOMEM;
  1471. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
  1472. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1473. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1474. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1475. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1476. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1477. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1478. cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
  1479. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
  1480. MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
  1481. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1482. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1483. rc = mwl8k_post_cmd(hw, &cmd->header);
  1484. kfree(cmd);
  1485. return rc;
  1486. }
  1487. /*
  1488. * CMD_MAC_MULTICAST_ADR.
  1489. */
  1490. struct mwl8k_cmd_mac_multicast_adr {
  1491. struct mwl8k_cmd_pkt header;
  1492. __le16 action;
  1493. __le16 numaddr;
  1494. __u8 addr[0][ETH_ALEN];
  1495. };
  1496. #define MWL8K_ENABLE_RX_DIRECTED 0x0001
  1497. #define MWL8K_ENABLE_RX_MULTICAST 0x0002
  1498. #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
  1499. #define MWL8K_ENABLE_RX_BROADCAST 0x0008
  1500. static struct mwl8k_cmd_pkt *
  1501. __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
  1502. int mc_count, struct dev_addr_list *mclist)
  1503. {
  1504. struct mwl8k_priv *priv = hw->priv;
  1505. struct mwl8k_cmd_mac_multicast_adr *cmd;
  1506. int size;
  1507. if (allmulti || mc_count > priv->num_mcaddrs) {
  1508. allmulti = 1;
  1509. mc_count = 0;
  1510. }
  1511. size = sizeof(*cmd) + mc_count * ETH_ALEN;
  1512. cmd = kzalloc(size, GFP_ATOMIC);
  1513. if (cmd == NULL)
  1514. return NULL;
  1515. cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
  1516. cmd->header.length = cpu_to_le16(size);
  1517. cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
  1518. MWL8K_ENABLE_RX_BROADCAST);
  1519. if (allmulti) {
  1520. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
  1521. } else if (mc_count) {
  1522. int i;
  1523. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
  1524. cmd->numaddr = cpu_to_le16(mc_count);
  1525. for (i = 0; i < mc_count && mclist; i++) {
  1526. if (mclist->da_addrlen != ETH_ALEN) {
  1527. kfree(cmd);
  1528. return NULL;
  1529. }
  1530. memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
  1531. mclist = mclist->next;
  1532. }
  1533. }
  1534. return &cmd->header;
  1535. }
  1536. /*
  1537. * CMD_GET_STAT.
  1538. */
  1539. struct mwl8k_cmd_get_stat {
  1540. struct mwl8k_cmd_pkt header;
  1541. __le32 stats[64];
  1542. } __attribute__((packed));
  1543. #define MWL8K_STAT_ACK_FAILURE 9
  1544. #define MWL8K_STAT_RTS_FAILURE 12
  1545. #define MWL8K_STAT_FCS_ERROR 24
  1546. #define MWL8K_STAT_RTS_SUCCESS 11
  1547. static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
  1548. struct ieee80211_low_level_stats *stats)
  1549. {
  1550. struct mwl8k_cmd_get_stat *cmd;
  1551. int rc;
  1552. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1553. if (cmd == NULL)
  1554. return -ENOMEM;
  1555. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
  1556. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1557. rc = mwl8k_post_cmd(hw, &cmd->header);
  1558. if (!rc) {
  1559. stats->dot11ACKFailureCount =
  1560. le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
  1561. stats->dot11RTSFailureCount =
  1562. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
  1563. stats->dot11FCSErrorCount =
  1564. le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
  1565. stats->dot11RTSSuccessCount =
  1566. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
  1567. }
  1568. kfree(cmd);
  1569. return rc;
  1570. }
  1571. /*
  1572. * CMD_RADIO_CONTROL.
  1573. */
  1574. struct mwl8k_cmd_radio_control {
  1575. struct mwl8k_cmd_pkt header;
  1576. __le16 action;
  1577. __le16 control;
  1578. __le16 radio_on;
  1579. } __attribute__((packed));
  1580. static int
  1581. mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
  1582. {
  1583. struct mwl8k_priv *priv = hw->priv;
  1584. struct mwl8k_cmd_radio_control *cmd;
  1585. int rc;
  1586. if (enable == priv->radio_on && !force)
  1587. return 0;
  1588. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1589. if (cmd == NULL)
  1590. return -ENOMEM;
  1591. cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
  1592. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1593. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1594. cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
  1595. cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
  1596. rc = mwl8k_post_cmd(hw, &cmd->header);
  1597. kfree(cmd);
  1598. if (!rc)
  1599. priv->radio_on = enable;
  1600. return rc;
  1601. }
  1602. static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
  1603. {
  1604. return mwl8k_cmd_radio_control(hw, 0, 0);
  1605. }
  1606. static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
  1607. {
  1608. return mwl8k_cmd_radio_control(hw, 1, 0);
  1609. }
  1610. static int
  1611. mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
  1612. {
  1613. struct mwl8k_priv *priv = hw->priv;
  1614. priv->radio_short_preamble = short_preamble;
  1615. return mwl8k_cmd_radio_control(hw, 1, 1);
  1616. }
  1617. /*
  1618. * CMD_RF_TX_POWER.
  1619. */
  1620. #define MWL8K_TX_POWER_LEVEL_TOTAL 8
  1621. struct mwl8k_cmd_rf_tx_power {
  1622. struct mwl8k_cmd_pkt header;
  1623. __le16 action;
  1624. __le16 support_level;
  1625. __le16 current_level;
  1626. __le16 reserved;
  1627. __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
  1628. } __attribute__((packed));
  1629. static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
  1630. {
  1631. struct mwl8k_cmd_rf_tx_power *cmd;
  1632. int rc;
  1633. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1634. if (cmd == NULL)
  1635. return -ENOMEM;
  1636. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
  1637. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1638. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1639. cmd->support_level = cpu_to_le16(dBm);
  1640. rc = mwl8k_post_cmd(hw, &cmd->header);
  1641. kfree(cmd);
  1642. return rc;
  1643. }
  1644. /*
  1645. * CMD_RF_ANTENNA.
  1646. */
  1647. struct mwl8k_cmd_rf_antenna {
  1648. struct mwl8k_cmd_pkt header;
  1649. __le16 antenna;
  1650. __le16 mode;
  1651. } __attribute__((packed));
  1652. #define MWL8K_RF_ANTENNA_RX 1
  1653. #define MWL8K_RF_ANTENNA_TX 2
  1654. static int
  1655. mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
  1656. {
  1657. struct mwl8k_cmd_rf_antenna *cmd;
  1658. int rc;
  1659. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1660. if (cmd == NULL)
  1661. return -ENOMEM;
  1662. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
  1663. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1664. cmd->antenna = cpu_to_le16(antenna);
  1665. cmd->mode = cpu_to_le16(mask);
  1666. rc = mwl8k_post_cmd(hw, &cmd->header);
  1667. kfree(cmd);
  1668. return rc;
  1669. }
  1670. /*
  1671. * CMD_SET_BEACON.
  1672. */
  1673. struct mwl8k_cmd_set_beacon {
  1674. struct mwl8k_cmd_pkt header;
  1675. __le16 beacon_len;
  1676. __u8 beacon[0];
  1677. };
  1678. static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
  1679. {
  1680. struct mwl8k_cmd_set_beacon *cmd;
  1681. int rc;
  1682. cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
  1683. if (cmd == NULL)
  1684. return -ENOMEM;
  1685. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
  1686. cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
  1687. cmd->beacon_len = cpu_to_le16(len);
  1688. memcpy(cmd->beacon, beacon, len);
  1689. rc = mwl8k_post_cmd(hw, &cmd->header);
  1690. kfree(cmd);
  1691. return rc;
  1692. }
  1693. /*
  1694. * CMD_SET_PRE_SCAN.
  1695. */
  1696. struct mwl8k_cmd_set_pre_scan {
  1697. struct mwl8k_cmd_pkt header;
  1698. } __attribute__((packed));
  1699. static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
  1700. {
  1701. struct mwl8k_cmd_set_pre_scan *cmd;
  1702. int rc;
  1703. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1704. if (cmd == NULL)
  1705. return -ENOMEM;
  1706. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
  1707. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1708. rc = mwl8k_post_cmd(hw, &cmd->header);
  1709. kfree(cmd);
  1710. return rc;
  1711. }
  1712. /*
  1713. * CMD_SET_POST_SCAN.
  1714. */
  1715. struct mwl8k_cmd_set_post_scan {
  1716. struct mwl8k_cmd_pkt header;
  1717. __le32 isibss;
  1718. __u8 bssid[ETH_ALEN];
  1719. } __attribute__((packed));
  1720. static int
  1721. mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
  1722. {
  1723. struct mwl8k_cmd_set_post_scan *cmd;
  1724. int rc;
  1725. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1726. if (cmd == NULL)
  1727. return -ENOMEM;
  1728. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
  1729. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1730. cmd->isibss = 0;
  1731. memcpy(cmd->bssid, mac, ETH_ALEN);
  1732. rc = mwl8k_post_cmd(hw, &cmd->header);
  1733. kfree(cmd);
  1734. return rc;
  1735. }
  1736. /*
  1737. * CMD_SET_RF_CHANNEL.
  1738. */
  1739. struct mwl8k_cmd_set_rf_channel {
  1740. struct mwl8k_cmd_pkt header;
  1741. __le16 action;
  1742. __u8 current_channel;
  1743. __le32 channel_flags;
  1744. } __attribute__((packed));
  1745. static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
  1746. struct ieee80211_conf *conf)
  1747. {
  1748. struct ieee80211_channel *channel = conf->channel;
  1749. struct mwl8k_cmd_set_rf_channel *cmd;
  1750. int rc;
  1751. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1752. if (cmd == NULL)
  1753. return -ENOMEM;
  1754. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
  1755. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1756. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1757. cmd->current_channel = channel->hw_value;
  1758. if (channel->band == IEEE80211_BAND_2GHZ)
  1759. cmd->channel_flags |= cpu_to_le32(0x00000001);
  1760. if (conf->channel_type == NL80211_CHAN_NO_HT ||
  1761. conf->channel_type == NL80211_CHAN_HT20)
  1762. cmd->channel_flags |= cpu_to_le32(0x00000080);
  1763. else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
  1764. cmd->channel_flags |= cpu_to_le32(0x000001900);
  1765. else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
  1766. cmd->channel_flags |= cpu_to_le32(0x000000900);
  1767. rc = mwl8k_post_cmd(hw, &cmd->header);
  1768. kfree(cmd);
  1769. return rc;
  1770. }
  1771. /*
  1772. * CMD_SET_AID.
  1773. */
  1774. #define MWL8K_FRAME_PROT_DISABLED 0x00
  1775. #define MWL8K_FRAME_PROT_11G 0x07
  1776. #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
  1777. #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
  1778. struct mwl8k_cmd_update_set_aid {
  1779. struct mwl8k_cmd_pkt header;
  1780. __le16 aid;
  1781. /* AP's MAC address (BSSID) */
  1782. __u8 bssid[ETH_ALEN];
  1783. __le16 protection_mode;
  1784. __u8 supp_rates[14];
  1785. } __attribute__((packed));
  1786. static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
  1787. {
  1788. int i;
  1789. int j;
  1790. /*
  1791. * Clear nonstandard rates 4 and 13.
  1792. */
  1793. mask &= 0x1fef;
  1794. for (i = 0, j = 0; i < 14; i++) {
  1795. if (mask & (1 << i))
  1796. rates[j++] = mwl8k_rates[i].hw_value;
  1797. }
  1798. }
  1799. static int
  1800. mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
  1801. struct ieee80211_vif *vif, u32 legacy_rate_mask)
  1802. {
  1803. struct mwl8k_cmd_update_set_aid *cmd;
  1804. u16 prot_mode;
  1805. int rc;
  1806. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1807. if (cmd == NULL)
  1808. return -ENOMEM;
  1809. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
  1810. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1811. cmd->aid = cpu_to_le16(vif->bss_conf.aid);
  1812. memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
  1813. if (vif->bss_conf.use_cts_prot) {
  1814. prot_mode = MWL8K_FRAME_PROT_11G;
  1815. } else {
  1816. switch (vif->bss_conf.ht_operation_mode &
  1817. IEEE80211_HT_OP_MODE_PROTECTION) {
  1818. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1819. prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
  1820. break;
  1821. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1822. prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
  1823. break;
  1824. default:
  1825. prot_mode = MWL8K_FRAME_PROT_DISABLED;
  1826. break;
  1827. }
  1828. }
  1829. cmd->protection_mode = cpu_to_le16(prot_mode);
  1830. legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
  1831. rc = mwl8k_post_cmd(hw, &cmd->header);
  1832. kfree(cmd);
  1833. return rc;
  1834. }
  1835. /*
  1836. * CMD_SET_RATE.
  1837. */
  1838. struct mwl8k_cmd_set_rate {
  1839. struct mwl8k_cmd_pkt header;
  1840. __u8 legacy_rates[14];
  1841. /* Bitmap for supported MCS codes. */
  1842. __u8 mcs_set[16];
  1843. __u8 reserved[16];
  1844. } __attribute__((packed));
  1845. static int
  1846. mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1847. u32 legacy_rate_mask, u8 *mcs_rates)
  1848. {
  1849. struct mwl8k_cmd_set_rate *cmd;
  1850. int rc;
  1851. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1852. if (cmd == NULL)
  1853. return -ENOMEM;
  1854. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
  1855. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1856. legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
  1857. memcpy(cmd->mcs_set, mcs_rates, 16);
  1858. rc = mwl8k_post_cmd(hw, &cmd->header);
  1859. kfree(cmd);
  1860. return rc;
  1861. }
  1862. /*
  1863. * CMD_FINALIZE_JOIN.
  1864. */
  1865. #define MWL8K_FJ_BEACON_MAXLEN 128
  1866. struct mwl8k_cmd_finalize_join {
  1867. struct mwl8k_cmd_pkt header;
  1868. __le32 sleep_interval; /* Number of beacon periods to sleep */
  1869. __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
  1870. } __attribute__((packed));
  1871. static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
  1872. int framelen, int dtim)
  1873. {
  1874. struct mwl8k_cmd_finalize_join *cmd;
  1875. struct ieee80211_mgmt *payload = frame;
  1876. int payload_len;
  1877. int rc;
  1878. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1879. if (cmd == NULL)
  1880. return -ENOMEM;
  1881. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
  1882. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1883. cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
  1884. payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
  1885. if (payload_len < 0)
  1886. payload_len = 0;
  1887. else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
  1888. payload_len = MWL8K_FJ_BEACON_MAXLEN;
  1889. memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
  1890. rc = mwl8k_post_cmd(hw, &cmd->header);
  1891. kfree(cmd);
  1892. return rc;
  1893. }
  1894. /*
  1895. * CMD_SET_RTS_THRESHOLD.
  1896. */
  1897. struct mwl8k_cmd_set_rts_threshold {
  1898. struct mwl8k_cmd_pkt header;
  1899. __le16 action;
  1900. __le16 threshold;
  1901. } __attribute__((packed));
  1902. static int
  1903. mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
  1904. {
  1905. struct mwl8k_cmd_set_rts_threshold *cmd;
  1906. int rc;
  1907. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1908. if (cmd == NULL)
  1909. return -ENOMEM;
  1910. cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
  1911. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1912. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1913. cmd->threshold = cpu_to_le16(rts_thresh);
  1914. rc = mwl8k_post_cmd(hw, &cmd->header);
  1915. kfree(cmd);
  1916. return rc;
  1917. }
  1918. /*
  1919. * CMD_SET_SLOT.
  1920. */
  1921. struct mwl8k_cmd_set_slot {
  1922. struct mwl8k_cmd_pkt header;
  1923. __le16 action;
  1924. __u8 short_slot;
  1925. } __attribute__((packed));
  1926. static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
  1927. {
  1928. struct mwl8k_cmd_set_slot *cmd;
  1929. int rc;
  1930. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1931. if (cmd == NULL)
  1932. return -ENOMEM;
  1933. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
  1934. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1935. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1936. cmd->short_slot = short_slot_time;
  1937. rc = mwl8k_post_cmd(hw, &cmd->header);
  1938. kfree(cmd);
  1939. return rc;
  1940. }
  1941. /*
  1942. * CMD_SET_EDCA_PARAMS.
  1943. */
  1944. struct mwl8k_cmd_set_edca_params {
  1945. struct mwl8k_cmd_pkt header;
  1946. /* See MWL8K_SET_EDCA_XXX below */
  1947. __le16 action;
  1948. /* TX opportunity in units of 32 us */
  1949. __le16 txop;
  1950. union {
  1951. struct {
  1952. /* Log exponent of max contention period: 0...15 */
  1953. __le32 log_cw_max;
  1954. /* Log exponent of min contention period: 0...15 */
  1955. __le32 log_cw_min;
  1956. /* Adaptive interframe spacing in units of 32us */
  1957. __u8 aifs;
  1958. /* TX queue to configure */
  1959. __u8 txq;
  1960. } ap;
  1961. struct {
  1962. /* Log exponent of max contention period: 0...15 */
  1963. __u8 log_cw_max;
  1964. /* Log exponent of min contention period: 0...15 */
  1965. __u8 log_cw_min;
  1966. /* Adaptive interframe spacing in units of 32us */
  1967. __u8 aifs;
  1968. /* TX queue to configure */
  1969. __u8 txq;
  1970. } sta;
  1971. };
  1972. } __attribute__((packed));
  1973. #define MWL8K_SET_EDCA_CW 0x01
  1974. #define MWL8K_SET_EDCA_TXOP 0x02
  1975. #define MWL8K_SET_EDCA_AIFS 0x04
  1976. #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
  1977. MWL8K_SET_EDCA_TXOP | \
  1978. MWL8K_SET_EDCA_AIFS)
  1979. static int
  1980. mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
  1981. __u16 cw_min, __u16 cw_max,
  1982. __u8 aifs, __u16 txop)
  1983. {
  1984. struct mwl8k_priv *priv = hw->priv;
  1985. struct mwl8k_cmd_set_edca_params *cmd;
  1986. int rc;
  1987. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1988. if (cmd == NULL)
  1989. return -ENOMEM;
  1990. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
  1991. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1992. cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
  1993. cmd->txop = cpu_to_le16(txop);
  1994. if (priv->ap_fw) {
  1995. cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
  1996. cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
  1997. cmd->ap.aifs = aifs;
  1998. cmd->ap.txq = qnum;
  1999. } else {
  2000. cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
  2001. cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
  2002. cmd->sta.aifs = aifs;
  2003. cmd->sta.txq = qnum;
  2004. }
  2005. rc = mwl8k_post_cmd(hw, &cmd->header);
  2006. kfree(cmd);
  2007. return rc;
  2008. }
  2009. /*
  2010. * CMD_SET_WMM_MODE.
  2011. */
  2012. struct mwl8k_cmd_set_wmm_mode {
  2013. struct mwl8k_cmd_pkt header;
  2014. __le16 action;
  2015. } __attribute__((packed));
  2016. static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
  2017. {
  2018. struct mwl8k_priv *priv = hw->priv;
  2019. struct mwl8k_cmd_set_wmm_mode *cmd;
  2020. int rc;
  2021. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2022. if (cmd == NULL)
  2023. return -ENOMEM;
  2024. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
  2025. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2026. cmd->action = cpu_to_le16(!!enable);
  2027. rc = mwl8k_post_cmd(hw, &cmd->header);
  2028. kfree(cmd);
  2029. if (!rc)
  2030. priv->wmm_enabled = enable;
  2031. return rc;
  2032. }
  2033. /*
  2034. * CMD_MIMO_CONFIG.
  2035. */
  2036. struct mwl8k_cmd_mimo_config {
  2037. struct mwl8k_cmd_pkt header;
  2038. __le32 action;
  2039. __u8 rx_antenna_map;
  2040. __u8 tx_antenna_map;
  2041. } __attribute__((packed));
  2042. static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
  2043. {
  2044. struct mwl8k_cmd_mimo_config *cmd;
  2045. int rc;
  2046. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2047. if (cmd == NULL)
  2048. return -ENOMEM;
  2049. cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
  2050. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2051. cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
  2052. cmd->rx_antenna_map = rx;
  2053. cmd->tx_antenna_map = tx;
  2054. rc = mwl8k_post_cmd(hw, &cmd->header);
  2055. kfree(cmd);
  2056. return rc;
  2057. }
  2058. /*
  2059. * CMD_USE_FIXED_RATE (STA version).
  2060. */
  2061. struct mwl8k_cmd_use_fixed_rate_sta {
  2062. struct mwl8k_cmd_pkt header;
  2063. __le32 action;
  2064. __le32 allow_rate_drop;
  2065. __le32 num_rates;
  2066. struct {
  2067. __le32 is_ht_rate;
  2068. __le32 enable_retry;
  2069. __le32 rate;
  2070. __le32 retry_count;
  2071. } rate_entry[8];
  2072. __le32 rate_type;
  2073. __le32 reserved1;
  2074. __le32 reserved2;
  2075. } __attribute__((packed));
  2076. #define MWL8K_USE_AUTO_RATE 0x0002
  2077. #define MWL8K_UCAST_RATE 0
  2078. static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
  2079. {
  2080. struct mwl8k_cmd_use_fixed_rate_sta *cmd;
  2081. int rc;
  2082. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2083. if (cmd == NULL)
  2084. return -ENOMEM;
  2085. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2086. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2087. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2088. cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
  2089. rc = mwl8k_post_cmd(hw, &cmd->header);
  2090. kfree(cmd);
  2091. return rc;
  2092. }
  2093. /*
  2094. * CMD_USE_FIXED_RATE (AP version).
  2095. */
  2096. struct mwl8k_cmd_use_fixed_rate_ap {
  2097. struct mwl8k_cmd_pkt header;
  2098. __le32 action;
  2099. __le32 allow_rate_drop;
  2100. __le32 num_rates;
  2101. struct mwl8k_rate_entry_ap {
  2102. __le32 is_ht_rate;
  2103. __le32 enable_retry;
  2104. __le32 rate;
  2105. __le32 retry_count;
  2106. } rate_entry[4];
  2107. u8 multicast_rate;
  2108. u8 multicast_rate_type;
  2109. u8 management_rate;
  2110. } __attribute__((packed));
  2111. static int
  2112. mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
  2113. {
  2114. struct mwl8k_cmd_use_fixed_rate_ap *cmd;
  2115. int rc;
  2116. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2117. if (cmd == NULL)
  2118. return -ENOMEM;
  2119. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2120. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2121. cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
  2122. cmd->multicast_rate = mcast;
  2123. cmd->management_rate = mgmt;
  2124. rc = mwl8k_post_cmd(hw, &cmd->header);
  2125. kfree(cmd);
  2126. return rc;
  2127. }
  2128. /*
  2129. * CMD_ENABLE_SNIFFER.
  2130. */
  2131. struct mwl8k_cmd_enable_sniffer {
  2132. struct mwl8k_cmd_pkt header;
  2133. __le32 action;
  2134. } __attribute__((packed));
  2135. static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
  2136. {
  2137. struct mwl8k_cmd_enable_sniffer *cmd;
  2138. int rc;
  2139. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2140. if (cmd == NULL)
  2141. return -ENOMEM;
  2142. cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
  2143. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2144. cmd->action = cpu_to_le32(!!enable);
  2145. rc = mwl8k_post_cmd(hw, &cmd->header);
  2146. kfree(cmd);
  2147. return rc;
  2148. }
  2149. /*
  2150. * CMD_SET_MAC_ADDR.
  2151. */
  2152. struct mwl8k_cmd_set_mac_addr {
  2153. struct mwl8k_cmd_pkt header;
  2154. union {
  2155. struct {
  2156. __le16 mac_type;
  2157. __u8 mac_addr[ETH_ALEN];
  2158. } mbss;
  2159. __u8 mac_addr[ETH_ALEN];
  2160. };
  2161. } __attribute__((packed));
  2162. #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
  2163. #define MWL8K_MAC_TYPE_PRIMARY_AP 2
  2164. static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
  2165. {
  2166. struct mwl8k_priv *priv = hw->priv;
  2167. struct mwl8k_cmd_set_mac_addr *cmd;
  2168. int rc;
  2169. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2170. if (cmd == NULL)
  2171. return -ENOMEM;
  2172. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
  2173. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2174. if (priv->ap_fw) {
  2175. cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
  2176. memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
  2177. } else {
  2178. memcpy(cmd->mac_addr, mac, ETH_ALEN);
  2179. }
  2180. rc = mwl8k_post_cmd(hw, &cmd->header);
  2181. kfree(cmd);
  2182. return rc;
  2183. }
  2184. /*
  2185. * CMD_SET_RATEADAPT_MODE.
  2186. */
  2187. struct mwl8k_cmd_set_rate_adapt_mode {
  2188. struct mwl8k_cmd_pkt header;
  2189. __le16 action;
  2190. __le16 mode;
  2191. } __attribute__((packed));
  2192. static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
  2193. {
  2194. struct mwl8k_cmd_set_rate_adapt_mode *cmd;
  2195. int rc;
  2196. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2197. if (cmd == NULL)
  2198. return -ENOMEM;
  2199. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
  2200. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2201. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  2202. cmd->mode = cpu_to_le16(mode);
  2203. rc = mwl8k_post_cmd(hw, &cmd->header);
  2204. kfree(cmd);
  2205. return rc;
  2206. }
  2207. /*
  2208. * CMD_BSS_START.
  2209. */
  2210. struct mwl8k_cmd_bss_start {
  2211. struct mwl8k_cmd_pkt header;
  2212. __le32 enable;
  2213. } __attribute__((packed));
  2214. static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
  2215. {
  2216. struct mwl8k_cmd_bss_start *cmd;
  2217. int rc;
  2218. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2219. if (cmd == NULL)
  2220. return -ENOMEM;
  2221. cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
  2222. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2223. cmd->enable = cpu_to_le32(enable);
  2224. rc = mwl8k_post_cmd(hw, &cmd->header);
  2225. kfree(cmd);
  2226. return rc;
  2227. }
  2228. /*
  2229. * CMD_SET_NEW_STN.
  2230. */
  2231. struct mwl8k_cmd_set_new_stn {
  2232. struct mwl8k_cmd_pkt header;
  2233. __le16 aid;
  2234. __u8 mac_addr[6];
  2235. __le16 stn_id;
  2236. __le16 action;
  2237. __le16 rsvd;
  2238. __le32 legacy_rates;
  2239. __u8 ht_rates[4];
  2240. __le16 cap_info;
  2241. __le16 ht_capabilities_info;
  2242. __u8 mac_ht_param_info;
  2243. __u8 rev;
  2244. __u8 control_channel;
  2245. __u8 add_channel;
  2246. __le16 op_mode;
  2247. __le16 stbc;
  2248. __u8 add_qos_info;
  2249. __u8 is_qos_sta;
  2250. __le32 fw_sta_ptr;
  2251. } __attribute__((packed));
  2252. #define MWL8K_STA_ACTION_ADD 0
  2253. #define MWL8K_STA_ACTION_REMOVE 2
  2254. static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
  2255. struct ieee80211_vif *vif,
  2256. struct ieee80211_sta *sta)
  2257. {
  2258. struct mwl8k_cmd_set_new_stn *cmd;
  2259. int rc;
  2260. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2261. if (cmd == NULL)
  2262. return -ENOMEM;
  2263. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2264. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2265. cmd->aid = cpu_to_le16(sta->aid);
  2266. memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
  2267. cmd->stn_id = cpu_to_le16(sta->aid);
  2268. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
  2269. cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2270. if (sta->ht_cap.ht_supported) {
  2271. cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
  2272. cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
  2273. cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
  2274. cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
  2275. cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
  2276. cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
  2277. ((sta->ht_cap.ampdu_density & 7) << 2);
  2278. cmd->is_qos_sta = 1;
  2279. }
  2280. rc = mwl8k_post_cmd(hw, &cmd->header);
  2281. kfree(cmd);
  2282. return rc;
  2283. }
  2284. static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
  2285. struct ieee80211_vif *vif)
  2286. {
  2287. struct mwl8k_cmd_set_new_stn *cmd;
  2288. int rc;
  2289. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2290. if (cmd == NULL)
  2291. return -ENOMEM;
  2292. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2293. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2294. memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
  2295. rc = mwl8k_post_cmd(hw, &cmd->header);
  2296. kfree(cmd);
  2297. return rc;
  2298. }
  2299. static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
  2300. struct ieee80211_vif *vif, u8 *addr)
  2301. {
  2302. struct mwl8k_cmd_set_new_stn *cmd;
  2303. int rc;
  2304. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2305. if (cmd == NULL)
  2306. return -ENOMEM;
  2307. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
  2308. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2309. memcpy(cmd->mac_addr, addr, ETH_ALEN);
  2310. cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
  2311. rc = mwl8k_post_cmd(hw, &cmd->header);
  2312. kfree(cmd);
  2313. return rc;
  2314. }
  2315. /*
  2316. * CMD_UPDATE_STADB.
  2317. */
  2318. struct ewc_ht_info {
  2319. __le16 control1;
  2320. __le16 control2;
  2321. __le16 control3;
  2322. } __attribute__((packed));
  2323. struct peer_capability_info {
  2324. /* Peer type - AP vs. STA. */
  2325. __u8 peer_type;
  2326. /* Basic 802.11 capabilities from assoc resp. */
  2327. __le16 basic_caps;
  2328. /* Set if peer supports 802.11n high throughput (HT). */
  2329. __u8 ht_support;
  2330. /* Valid if HT is supported. */
  2331. __le16 ht_caps;
  2332. __u8 extended_ht_caps;
  2333. struct ewc_ht_info ewc_info;
  2334. /* Legacy rate table. Intersection of our rates and peer rates. */
  2335. __u8 legacy_rates[12];
  2336. /* HT rate table. Intersection of our rates and peer rates. */
  2337. __u8 ht_rates[16];
  2338. __u8 pad[16];
  2339. /* If set, interoperability mode, no proprietary extensions. */
  2340. __u8 interop;
  2341. __u8 pad2;
  2342. __u8 station_id;
  2343. __le16 amsdu_enabled;
  2344. } __attribute__((packed));
  2345. struct mwl8k_cmd_update_stadb {
  2346. struct mwl8k_cmd_pkt header;
  2347. /* See STADB_ACTION_TYPE */
  2348. __le32 action;
  2349. /* Peer MAC address */
  2350. __u8 peer_addr[ETH_ALEN];
  2351. __le32 reserved;
  2352. /* Peer info - valid during add/update. */
  2353. struct peer_capability_info peer_info;
  2354. } __attribute__((packed));
  2355. #define MWL8K_STA_DB_MODIFY_ENTRY 1
  2356. #define MWL8K_STA_DB_DEL_ENTRY 2
  2357. /* Peer Entry flags - used to define the type of the peer node */
  2358. #define MWL8K_PEER_TYPE_ACCESSPOINT 2
  2359. static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
  2360. struct ieee80211_vif *vif,
  2361. struct ieee80211_sta *sta)
  2362. {
  2363. struct mwl8k_cmd_update_stadb *cmd;
  2364. struct peer_capability_info *p;
  2365. int rc;
  2366. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2367. if (cmd == NULL)
  2368. return -ENOMEM;
  2369. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2370. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2371. cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
  2372. memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
  2373. p = &cmd->peer_info;
  2374. p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
  2375. p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
  2376. p->ht_support = sta->ht_cap.ht_supported;
  2377. p->ht_caps = sta->ht_cap.cap;
  2378. p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
  2379. ((sta->ht_cap.ampdu_density & 7) << 2);
  2380. legacy_rate_mask_to_array(p->legacy_rates,
  2381. sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2382. memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
  2383. p->interop = 1;
  2384. p->amsdu_enabled = 0;
  2385. rc = mwl8k_post_cmd(hw, &cmd->header);
  2386. kfree(cmd);
  2387. return rc ? rc : p->station_id;
  2388. }
  2389. static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
  2390. struct ieee80211_vif *vif, u8 *addr)
  2391. {
  2392. struct mwl8k_cmd_update_stadb *cmd;
  2393. int rc;
  2394. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2395. if (cmd == NULL)
  2396. return -ENOMEM;
  2397. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2398. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2399. cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
  2400. memcpy(cmd->peer_addr, addr, ETH_ALEN);
  2401. rc = mwl8k_post_cmd(hw, &cmd->header);
  2402. kfree(cmd);
  2403. return rc;
  2404. }
  2405. /*
  2406. * Interrupt handling.
  2407. */
  2408. static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
  2409. {
  2410. struct ieee80211_hw *hw = dev_id;
  2411. struct mwl8k_priv *priv = hw->priv;
  2412. u32 status;
  2413. status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2414. iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2415. if (!status)
  2416. return IRQ_NONE;
  2417. if (status & MWL8K_A2H_INT_TX_DONE)
  2418. tasklet_schedule(&priv->tx_reclaim_task);
  2419. if (status & MWL8K_A2H_INT_RX_READY) {
  2420. while (rxq_process(hw, 0, 1))
  2421. rxq_refill(hw, 0, 1);
  2422. }
  2423. if (status & MWL8K_A2H_INT_OPC_DONE) {
  2424. if (priv->hostcmd_wait != NULL)
  2425. complete(priv->hostcmd_wait);
  2426. }
  2427. if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
  2428. if (!mutex_is_locked(&priv->fw_mutex) &&
  2429. priv->radio_on && priv->pending_tx_pkts)
  2430. mwl8k_tx_start(priv);
  2431. }
  2432. return IRQ_HANDLED;
  2433. }
  2434. /*
  2435. * Core driver operations.
  2436. */
  2437. static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2438. {
  2439. struct mwl8k_priv *priv = hw->priv;
  2440. int index = skb_get_queue_mapping(skb);
  2441. int rc;
  2442. if (priv->current_channel == NULL) {
  2443. printk(KERN_DEBUG "%s: dropped TX frame since radio "
  2444. "disabled\n", wiphy_name(hw->wiphy));
  2445. dev_kfree_skb(skb);
  2446. return NETDEV_TX_OK;
  2447. }
  2448. rc = mwl8k_txq_xmit(hw, index, skb);
  2449. return rc;
  2450. }
  2451. static int mwl8k_start(struct ieee80211_hw *hw)
  2452. {
  2453. struct mwl8k_priv *priv = hw->priv;
  2454. int rc;
  2455. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2456. IRQF_SHARED, MWL8K_NAME, hw);
  2457. if (rc) {
  2458. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2459. wiphy_name(hw->wiphy));
  2460. return -EIO;
  2461. }
  2462. /* Enable tx reclaim tasklet */
  2463. tasklet_enable(&priv->tx_reclaim_task);
  2464. /* Enable interrupts */
  2465. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2466. rc = mwl8k_fw_lock(hw);
  2467. if (!rc) {
  2468. rc = mwl8k_cmd_radio_enable(hw);
  2469. if (!priv->ap_fw) {
  2470. if (!rc)
  2471. rc = mwl8k_cmd_enable_sniffer(hw, 0);
  2472. if (!rc)
  2473. rc = mwl8k_cmd_set_pre_scan(hw);
  2474. if (!rc)
  2475. rc = mwl8k_cmd_set_post_scan(hw,
  2476. "\x00\x00\x00\x00\x00\x00");
  2477. }
  2478. if (!rc)
  2479. rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
  2480. if (!rc)
  2481. rc = mwl8k_cmd_set_wmm_mode(hw, 0);
  2482. mwl8k_fw_unlock(hw);
  2483. }
  2484. if (rc) {
  2485. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2486. free_irq(priv->pdev->irq, hw);
  2487. tasklet_disable(&priv->tx_reclaim_task);
  2488. }
  2489. return rc;
  2490. }
  2491. static void mwl8k_stop(struct ieee80211_hw *hw)
  2492. {
  2493. struct mwl8k_priv *priv = hw->priv;
  2494. int i;
  2495. mwl8k_cmd_radio_disable(hw);
  2496. ieee80211_stop_queues(hw);
  2497. /* Disable interrupts */
  2498. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2499. free_irq(priv->pdev->irq, hw);
  2500. /* Stop finalize join worker */
  2501. cancel_work_sync(&priv->finalize_join_worker);
  2502. if (priv->beacon_skb != NULL)
  2503. dev_kfree_skb(priv->beacon_skb);
  2504. /* Stop tx reclaim tasklet */
  2505. tasklet_disable(&priv->tx_reclaim_task);
  2506. /* Return all skbs to mac80211 */
  2507. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2508. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  2509. }
  2510. static int mwl8k_add_interface(struct ieee80211_hw *hw,
  2511. struct ieee80211_vif *vif)
  2512. {
  2513. struct mwl8k_priv *priv = hw->priv;
  2514. struct mwl8k_vif *mwl8k_vif;
  2515. /*
  2516. * We only support one active interface at a time.
  2517. */
  2518. if (priv->vif != NULL)
  2519. return -EBUSY;
  2520. /*
  2521. * Reject interface creation if sniffer mode is active, as
  2522. * STA operation is mutually exclusive with hardware sniffer
  2523. * mode. (Sniffer mode is only used on STA firmware.)
  2524. */
  2525. if (priv->sniffer_enabled) {
  2526. printk(KERN_INFO "%s: unable to create STA "
  2527. "interface due to sniffer mode being enabled\n",
  2528. wiphy_name(hw->wiphy));
  2529. return -EINVAL;
  2530. }
  2531. /* Set the mac address. */
  2532. mwl8k_cmd_set_mac_addr(hw, vif->addr);
  2533. if (priv->ap_fw)
  2534. mwl8k_cmd_set_new_stn_add_self(hw, vif);
  2535. /* Clean out driver private area */
  2536. mwl8k_vif = MWL8K_VIF(vif);
  2537. memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
  2538. /* Set Initial sequence number to zero */
  2539. mwl8k_vif->seqno = 0;
  2540. priv->vif = vif;
  2541. priv->current_channel = NULL;
  2542. return 0;
  2543. }
  2544. static void mwl8k_remove_interface(struct ieee80211_hw *hw,
  2545. struct ieee80211_vif *vif)
  2546. {
  2547. struct mwl8k_priv *priv = hw->priv;
  2548. if (priv->ap_fw)
  2549. mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
  2550. mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2551. priv->vif = NULL;
  2552. }
  2553. static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
  2554. {
  2555. struct ieee80211_conf *conf = &hw->conf;
  2556. struct mwl8k_priv *priv = hw->priv;
  2557. int rc;
  2558. if (conf->flags & IEEE80211_CONF_IDLE) {
  2559. mwl8k_cmd_radio_disable(hw);
  2560. priv->current_channel = NULL;
  2561. return 0;
  2562. }
  2563. rc = mwl8k_fw_lock(hw);
  2564. if (rc)
  2565. return rc;
  2566. rc = mwl8k_cmd_radio_enable(hw);
  2567. if (rc)
  2568. goto out;
  2569. rc = mwl8k_cmd_set_rf_channel(hw, conf);
  2570. if (rc)
  2571. goto out;
  2572. priv->current_channel = conf->channel;
  2573. if (conf->power_level > 18)
  2574. conf->power_level = 18;
  2575. rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
  2576. if (rc)
  2577. goto out;
  2578. if (priv->ap_fw) {
  2579. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
  2580. if (!rc)
  2581. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
  2582. } else {
  2583. rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
  2584. }
  2585. out:
  2586. mwl8k_fw_unlock(hw);
  2587. return rc;
  2588. }
  2589. static void
  2590. mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2591. struct ieee80211_bss_conf *info, u32 changed)
  2592. {
  2593. struct mwl8k_priv *priv = hw->priv;
  2594. u32 ap_legacy_rates;
  2595. u8 ap_mcs_rates[16];
  2596. int rc;
  2597. if (mwl8k_fw_lock(hw))
  2598. return;
  2599. /*
  2600. * No need to capture a beacon if we're no longer associated.
  2601. */
  2602. if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
  2603. priv->capture_beacon = false;
  2604. /*
  2605. * Get the AP's legacy and MCS rates.
  2606. */
  2607. ap_legacy_rates = 0;
  2608. if (vif->bss_conf.assoc) {
  2609. struct ieee80211_sta *ap;
  2610. rcu_read_lock();
  2611. ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  2612. if (ap == NULL) {
  2613. rcu_read_unlock();
  2614. goto out;
  2615. }
  2616. ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
  2617. memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
  2618. rcu_read_unlock();
  2619. }
  2620. if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
  2621. rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
  2622. if (rc)
  2623. goto out;
  2624. rc = mwl8k_cmd_use_fixed_rate_sta(hw);
  2625. if (rc)
  2626. goto out;
  2627. }
  2628. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2629. rc = mwl8k_set_radio_preamble(hw,
  2630. vif->bss_conf.use_short_preamble);
  2631. if (rc)
  2632. goto out;
  2633. }
  2634. if (changed & BSS_CHANGED_ERP_SLOT) {
  2635. rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
  2636. if (rc)
  2637. goto out;
  2638. }
  2639. if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) ||
  2640. (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) {
  2641. rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
  2642. if (rc)
  2643. goto out;
  2644. }
  2645. if (vif->bss_conf.assoc &&
  2646. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
  2647. /*
  2648. * Finalize the join. Tell rx handler to process
  2649. * next beacon from our BSSID.
  2650. */
  2651. memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
  2652. priv->capture_beacon = true;
  2653. }
  2654. out:
  2655. mwl8k_fw_unlock(hw);
  2656. }
  2657. static void
  2658. mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2659. struct ieee80211_bss_conf *info, u32 changed)
  2660. {
  2661. int rc;
  2662. if (mwl8k_fw_lock(hw))
  2663. return;
  2664. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2665. rc = mwl8k_set_radio_preamble(hw,
  2666. vif->bss_conf.use_short_preamble);
  2667. if (rc)
  2668. goto out;
  2669. }
  2670. if (changed & BSS_CHANGED_BASIC_RATES) {
  2671. int idx;
  2672. int rate;
  2673. /*
  2674. * Use lowest supported basic rate for multicasts
  2675. * and management frames (such as probe responses --
  2676. * beacons will always go out at 1 Mb/s).
  2677. */
  2678. idx = ffs(vif->bss_conf.basic_rates);
  2679. rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
  2680. mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
  2681. }
  2682. if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
  2683. struct sk_buff *skb;
  2684. skb = ieee80211_beacon_get(hw, vif);
  2685. if (skb != NULL) {
  2686. mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
  2687. kfree_skb(skb);
  2688. }
  2689. }
  2690. if (changed & BSS_CHANGED_BEACON_ENABLED)
  2691. mwl8k_cmd_bss_start(hw, info->enable_beacon);
  2692. out:
  2693. mwl8k_fw_unlock(hw);
  2694. }
  2695. static void
  2696. mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2697. struct ieee80211_bss_conf *info, u32 changed)
  2698. {
  2699. struct mwl8k_priv *priv = hw->priv;
  2700. if (!priv->ap_fw)
  2701. mwl8k_bss_info_changed_sta(hw, vif, info, changed);
  2702. else
  2703. mwl8k_bss_info_changed_ap(hw, vif, info, changed);
  2704. }
  2705. static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
  2706. int mc_count, struct dev_addr_list *mclist)
  2707. {
  2708. struct mwl8k_cmd_pkt *cmd;
  2709. /*
  2710. * Synthesize and return a command packet that programs the
  2711. * hardware multicast address filter. At this point we don't
  2712. * know whether FIF_ALLMULTI is being requested, but if it is,
  2713. * we'll end up throwing this packet away and creating a new
  2714. * one in mwl8k_configure_filter().
  2715. */
  2716. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
  2717. return (unsigned long)cmd;
  2718. }
  2719. static int
  2720. mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
  2721. unsigned int changed_flags,
  2722. unsigned int *total_flags)
  2723. {
  2724. struct mwl8k_priv *priv = hw->priv;
  2725. /*
  2726. * Hardware sniffer mode is mutually exclusive with STA
  2727. * operation, so refuse to enable sniffer mode if a STA
  2728. * interface is active.
  2729. */
  2730. if (priv->vif != NULL) {
  2731. if (net_ratelimit())
  2732. printk(KERN_INFO "%s: not enabling sniffer "
  2733. "mode because STA interface is active\n",
  2734. wiphy_name(hw->wiphy));
  2735. return 0;
  2736. }
  2737. if (!priv->sniffer_enabled) {
  2738. if (mwl8k_cmd_enable_sniffer(hw, 1))
  2739. return 0;
  2740. priv->sniffer_enabled = true;
  2741. }
  2742. *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
  2743. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
  2744. FIF_OTHER_BSS;
  2745. return 1;
  2746. }
  2747. static void mwl8k_configure_filter(struct ieee80211_hw *hw,
  2748. unsigned int changed_flags,
  2749. unsigned int *total_flags,
  2750. u64 multicast)
  2751. {
  2752. struct mwl8k_priv *priv = hw->priv;
  2753. struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
  2754. /*
  2755. * AP firmware doesn't allow fine-grained control over
  2756. * the receive filter.
  2757. */
  2758. if (priv->ap_fw) {
  2759. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2760. kfree(cmd);
  2761. return;
  2762. }
  2763. /*
  2764. * Enable hardware sniffer mode if FIF_CONTROL or
  2765. * FIF_OTHER_BSS is requested.
  2766. */
  2767. if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
  2768. mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
  2769. kfree(cmd);
  2770. return;
  2771. }
  2772. /* Clear unsupported feature flags */
  2773. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2774. if (mwl8k_fw_lock(hw)) {
  2775. kfree(cmd);
  2776. return;
  2777. }
  2778. if (priv->sniffer_enabled) {
  2779. mwl8k_cmd_enable_sniffer(hw, 0);
  2780. priv->sniffer_enabled = false;
  2781. }
  2782. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  2783. if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
  2784. /*
  2785. * Disable the BSS filter.
  2786. */
  2787. mwl8k_cmd_set_pre_scan(hw);
  2788. } else {
  2789. const u8 *bssid;
  2790. /*
  2791. * Enable the BSS filter.
  2792. *
  2793. * If there is an active STA interface, use that
  2794. * interface's BSSID, otherwise use a dummy one
  2795. * (where the OUI part needs to be nonzero for
  2796. * the BSSID to be accepted by POST_SCAN).
  2797. */
  2798. bssid = "\x01\x00\x00\x00\x00\x00";
  2799. if (priv->vif != NULL)
  2800. bssid = priv->vif->bss_conf.bssid;
  2801. mwl8k_cmd_set_post_scan(hw, bssid);
  2802. }
  2803. }
  2804. /*
  2805. * If FIF_ALLMULTI is being requested, throw away the command
  2806. * packet that ->prepare_multicast() built and replace it with
  2807. * a command packet that enables reception of all multicast
  2808. * packets.
  2809. */
  2810. if (*total_flags & FIF_ALLMULTI) {
  2811. kfree(cmd);
  2812. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
  2813. }
  2814. if (cmd != NULL) {
  2815. mwl8k_post_cmd(hw, cmd);
  2816. kfree(cmd);
  2817. }
  2818. mwl8k_fw_unlock(hw);
  2819. }
  2820. static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2821. {
  2822. return mwl8k_cmd_set_rts_threshold(hw, value);
  2823. }
  2824. struct mwl8k_sta_notify_item
  2825. {
  2826. struct list_head list;
  2827. struct ieee80211_vif *vif;
  2828. enum sta_notify_cmd cmd;
  2829. struct ieee80211_sta sta;
  2830. };
  2831. static void
  2832. mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
  2833. {
  2834. struct mwl8k_priv *priv = hw->priv;
  2835. /*
  2836. * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
  2837. */
  2838. if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2839. int rc;
  2840. rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
  2841. if (rc >= 0) {
  2842. struct ieee80211_sta *sta;
  2843. rcu_read_lock();
  2844. sta = ieee80211_find_sta(s->vif, s->sta.addr);
  2845. if (sta != NULL)
  2846. MWL8K_STA(sta)->peer_id = rc;
  2847. rcu_read_unlock();
  2848. }
  2849. } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2850. mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
  2851. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
  2852. mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
  2853. } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
  2854. mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
  2855. }
  2856. }
  2857. static void mwl8k_sta_notify_worker(struct work_struct *work)
  2858. {
  2859. struct mwl8k_priv *priv =
  2860. container_of(work, struct mwl8k_priv, sta_notify_worker);
  2861. struct ieee80211_hw *hw = priv->hw;
  2862. spin_lock_bh(&priv->sta_notify_list_lock);
  2863. while (!list_empty(&priv->sta_notify_list)) {
  2864. struct mwl8k_sta_notify_item *s;
  2865. s = list_entry(priv->sta_notify_list.next,
  2866. struct mwl8k_sta_notify_item, list);
  2867. list_del(&s->list);
  2868. spin_unlock_bh(&priv->sta_notify_list_lock);
  2869. mwl8k_do_sta_notify(hw, s);
  2870. kfree(s);
  2871. spin_lock_bh(&priv->sta_notify_list_lock);
  2872. }
  2873. spin_unlock_bh(&priv->sta_notify_list_lock);
  2874. }
  2875. static void
  2876. mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2877. enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
  2878. {
  2879. struct mwl8k_priv *priv = hw->priv;
  2880. struct mwl8k_sta_notify_item *s;
  2881. if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
  2882. return;
  2883. s = kmalloc(sizeof(*s), GFP_ATOMIC);
  2884. if (s != NULL) {
  2885. s->vif = vif;
  2886. s->cmd = cmd;
  2887. s->sta = *sta;
  2888. spin_lock(&priv->sta_notify_list_lock);
  2889. list_add_tail(&s->list, &priv->sta_notify_list);
  2890. spin_unlock(&priv->sta_notify_list_lock);
  2891. ieee80211_queue_work(hw, &priv->sta_notify_worker);
  2892. }
  2893. }
  2894. static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2895. const struct ieee80211_tx_queue_params *params)
  2896. {
  2897. struct mwl8k_priv *priv = hw->priv;
  2898. int rc;
  2899. rc = mwl8k_fw_lock(hw);
  2900. if (!rc) {
  2901. if (!priv->wmm_enabled)
  2902. rc = mwl8k_cmd_set_wmm_mode(hw, 1);
  2903. if (!rc)
  2904. rc = mwl8k_cmd_set_edca_params(hw, queue,
  2905. params->cw_min,
  2906. params->cw_max,
  2907. params->aifs,
  2908. params->txop);
  2909. mwl8k_fw_unlock(hw);
  2910. }
  2911. return rc;
  2912. }
  2913. static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
  2914. struct ieee80211_tx_queue_stats *stats)
  2915. {
  2916. struct mwl8k_priv *priv = hw->priv;
  2917. struct mwl8k_tx_queue *txq;
  2918. int index;
  2919. spin_lock_bh(&priv->tx_lock);
  2920. for (index = 0; index < MWL8K_TX_QUEUES; index++) {
  2921. txq = priv->txq + index;
  2922. memcpy(&stats[index], &txq->stats,
  2923. sizeof(struct ieee80211_tx_queue_stats));
  2924. }
  2925. spin_unlock_bh(&priv->tx_lock);
  2926. return 0;
  2927. }
  2928. static int mwl8k_get_stats(struct ieee80211_hw *hw,
  2929. struct ieee80211_low_level_stats *stats)
  2930. {
  2931. return mwl8k_cmd_get_stat(hw, stats);
  2932. }
  2933. static int
  2934. mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2935. enum ieee80211_ampdu_mlme_action action,
  2936. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2937. {
  2938. switch (action) {
  2939. case IEEE80211_AMPDU_RX_START:
  2940. case IEEE80211_AMPDU_RX_STOP:
  2941. if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
  2942. return -ENOTSUPP;
  2943. return 0;
  2944. default:
  2945. return -ENOTSUPP;
  2946. }
  2947. }
  2948. static const struct ieee80211_ops mwl8k_ops = {
  2949. .tx = mwl8k_tx,
  2950. .start = mwl8k_start,
  2951. .stop = mwl8k_stop,
  2952. .add_interface = mwl8k_add_interface,
  2953. .remove_interface = mwl8k_remove_interface,
  2954. .config = mwl8k_config,
  2955. .bss_info_changed = mwl8k_bss_info_changed,
  2956. .prepare_multicast = mwl8k_prepare_multicast,
  2957. .configure_filter = mwl8k_configure_filter,
  2958. .set_rts_threshold = mwl8k_set_rts_threshold,
  2959. .sta_notify = mwl8k_sta_notify,
  2960. .conf_tx = mwl8k_conf_tx,
  2961. .get_tx_stats = mwl8k_get_tx_stats,
  2962. .get_stats = mwl8k_get_stats,
  2963. .ampdu_action = mwl8k_ampdu_action,
  2964. };
  2965. static void mwl8k_tx_reclaim_handler(unsigned long data)
  2966. {
  2967. int i;
  2968. struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
  2969. struct mwl8k_priv *priv = hw->priv;
  2970. spin_lock_bh(&priv->tx_lock);
  2971. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2972. mwl8k_txq_reclaim(hw, i, INT_MAX, 0);
  2973. if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
  2974. complete(priv->tx_wait);
  2975. priv->tx_wait = NULL;
  2976. }
  2977. spin_unlock_bh(&priv->tx_lock);
  2978. }
  2979. static void mwl8k_finalize_join_worker(struct work_struct *work)
  2980. {
  2981. struct mwl8k_priv *priv =
  2982. container_of(work, struct mwl8k_priv, finalize_join_worker);
  2983. struct sk_buff *skb = priv->beacon_skb;
  2984. mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
  2985. priv->vif->bss_conf.dtim_period);
  2986. dev_kfree_skb(skb);
  2987. priv->beacon_skb = NULL;
  2988. }
  2989. enum {
  2990. MWL8363 = 0,
  2991. MWL8687,
  2992. MWL8366,
  2993. };
  2994. static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
  2995. [MWL8363] = {
  2996. .part_name = "88w8363",
  2997. .helper_image = "mwl8k/helper_8363.fw",
  2998. .fw_image = "mwl8k/fmimage_8363.fw",
  2999. },
  3000. [MWL8687] = {
  3001. .part_name = "88w8687",
  3002. .helper_image = "mwl8k/helper_8687.fw",
  3003. .fw_image = "mwl8k/fmimage_8687.fw",
  3004. },
  3005. [MWL8366] = {
  3006. .part_name = "88w8366",
  3007. .helper_image = "mwl8k/helper_8366.fw",
  3008. .fw_image = "mwl8k/fmimage_8366.fw",
  3009. .ap_rxd_ops = &rxd_8366_ap_ops,
  3010. },
  3011. };
  3012. static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
  3013. { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
  3014. { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
  3015. { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
  3016. { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
  3017. { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
  3018. { },
  3019. };
  3020. MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
  3021. static int __devinit mwl8k_probe(struct pci_dev *pdev,
  3022. const struct pci_device_id *id)
  3023. {
  3024. static int printed_version = 0;
  3025. struct ieee80211_hw *hw;
  3026. struct mwl8k_priv *priv;
  3027. int rc;
  3028. int i;
  3029. if (!printed_version) {
  3030. printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
  3031. printed_version = 1;
  3032. }
  3033. rc = pci_enable_device(pdev);
  3034. if (rc) {
  3035. printk(KERN_ERR "%s: Cannot enable new PCI device\n",
  3036. MWL8K_NAME);
  3037. return rc;
  3038. }
  3039. rc = pci_request_regions(pdev, MWL8K_NAME);
  3040. if (rc) {
  3041. printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
  3042. MWL8K_NAME);
  3043. goto err_disable_device;
  3044. }
  3045. pci_set_master(pdev);
  3046. hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
  3047. if (hw == NULL) {
  3048. printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
  3049. rc = -ENOMEM;
  3050. goto err_free_reg;
  3051. }
  3052. SET_IEEE80211_DEV(hw, &pdev->dev);
  3053. pci_set_drvdata(pdev, hw);
  3054. priv = hw->priv;
  3055. priv->hw = hw;
  3056. priv->pdev = pdev;
  3057. priv->device_info = &mwl8k_info_tbl[id->driver_data];
  3058. priv->sram = pci_iomap(pdev, 0, 0x10000);
  3059. if (priv->sram == NULL) {
  3060. printk(KERN_ERR "%s: Cannot map device SRAM\n",
  3061. wiphy_name(hw->wiphy));
  3062. goto err_iounmap;
  3063. }
  3064. /*
  3065. * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
  3066. * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
  3067. */
  3068. priv->regs = pci_iomap(pdev, 1, 0x10000);
  3069. if (priv->regs == NULL) {
  3070. priv->regs = pci_iomap(pdev, 2, 0x10000);
  3071. if (priv->regs == NULL) {
  3072. printk(KERN_ERR "%s: Cannot map device registers\n",
  3073. wiphy_name(hw->wiphy));
  3074. goto err_iounmap;
  3075. }
  3076. }
  3077. /* Reset firmware and hardware */
  3078. mwl8k_hw_reset(priv);
  3079. /* Ask userland hotplug daemon for the device firmware */
  3080. rc = mwl8k_request_firmware(priv);
  3081. if (rc) {
  3082. printk(KERN_ERR "%s: Firmware files not found\n",
  3083. wiphy_name(hw->wiphy));
  3084. goto err_stop_firmware;
  3085. }
  3086. /* Load firmware into hardware */
  3087. rc = mwl8k_load_firmware(hw);
  3088. if (rc) {
  3089. printk(KERN_ERR "%s: Cannot start firmware\n",
  3090. wiphy_name(hw->wiphy));
  3091. goto err_stop_firmware;
  3092. }
  3093. /* Reclaim memory once firmware is successfully loaded */
  3094. mwl8k_release_firmware(priv);
  3095. if (priv->ap_fw) {
  3096. priv->rxd_ops = priv->device_info->ap_rxd_ops;
  3097. if (priv->rxd_ops == NULL) {
  3098. printk(KERN_ERR "%s: Driver does not have AP "
  3099. "firmware image support for this hardware\n",
  3100. wiphy_name(hw->wiphy));
  3101. goto err_stop_firmware;
  3102. }
  3103. } else {
  3104. priv->rxd_ops = &rxd_sta_ops;
  3105. }
  3106. priv->sniffer_enabled = false;
  3107. priv->wmm_enabled = false;
  3108. priv->pending_tx_pkts = 0;
  3109. memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
  3110. priv->band.band = IEEE80211_BAND_2GHZ;
  3111. priv->band.channels = priv->channels;
  3112. priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
  3113. priv->band.bitrates = priv->rates;
  3114. priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
  3115. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  3116. BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
  3117. memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
  3118. /*
  3119. * Extra headroom is the size of the required DMA header
  3120. * minus the size of the smallest 802.11 frame (CTS frame).
  3121. */
  3122. hw->extra_tx_headroom =
  3123. sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
  3124. hw->channel_change_time = 10;
  3125. hw->queues = MWL8K_TX_QUEUES;
  3126. /* Set rssi and noise values to dBm */
  3127. hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
  3128. hw->vif_data_size = sizeof(struct mwl8k_vif);
  3129. hw->sta_data_size = sizeof(struct mwl8k_sta);
  3130. priv->vif = NULL;
  3131. /* Set default radio state and preamble */
  3132. priv->radio_on = 0;
  3133. priv->radio_short_preamble = 0;
  3134. /* Station database handling */
  3135. INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
  3136. spin_lock_init(&priv->sta_notify_list_lock);
  3137. INIT_LIST_HEAD(&priv->sta_notify_list);
  3138. /* Finalize join worker */
  3139. INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
  3140. /* TX reclaim tasklet */
  3141. tasklet_init(&priv->tx_reclaim_task,
  3142. mwl8k_tx_reclaim_handler, (unsigned long)hw);
  3143. tasklet_disable(&priv->tx_reclaim_task);
  3144. /* Power management cookie */
  3145. priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
  3146. if (priv->cookie == NULL)
  3147. goto err_stop_firmware;
  3148. rc = mwl8k_rxq_init(hw, 0);
  3149. if (rc)
  3150. goto err_free_cookie;
  3151. rxq_refill(hw, 0, INT_MAX);
  3152. mutex_init(&priv->fw_mutex);
  3153. priv->fw_mutex_owner = NULL;
  3154. priv->fw_mutex_depth = 0;
  3155. priv->hostcmd_wait = NULL;
  3156. spin_lock_init(&priv->tx_lock);
  3157. priv->tx_wait = NULL;
  3158. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  3159. rc = mwl8k_txq_init(hw, i);
  3160. if (rc)
  3161. goto err_free_queues;
  3162. }
  3163. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  3164. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3165. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
  3166. iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
  3167. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  3168. IRQF_SHARED, MWL8K_NAME, hw);
  3169. if (rc) {
  3170. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  3171. wiphy_name(hw->wiphy));
  3172. goto err_free_queues;
  3173. }
  3174. /*
  3175. * Temporarily enable interrupts. Initial firmware host
  3176. * commands use interrupts and avoid polling. Disable
  3177. * interrupts when done.
  3178. */
  3179. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3180. /* Get config data, mac addrs etc */
  3181. if (priv->ap_fw) {
  3182. rc = mwl8k_cmd_get_hw_spec_ap(hw);
  3183. if (!rc)
  3184. rc = mwl8k_cmd_set_hw_spec(hw);
  3185. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
  3186. } else {
  3187. rc = mwl8k_cmd_get_hw_spec_sta(hw);
  3188. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  3189. }
  3190. if (rc) {
  3191. printk(KERN_ERR "%s: Cannot initialise firmware\n",
  3192. wiphy_name(hw->wiphy));
  3193. goto err_free_irq;
  3194. }
  3195. /* Turn radio off */
  3196. rc = mwl8k_cmd_radio_disable(hw);
  3197. if (rc) {
  3198. printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
  3199. goto err_free_irq;
  3200. }
  3201. /* Clear MAC address */
  3202. rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  3203. if (rc) {
  3204. printk(KERN_ERR "%s: Cannot clear MAC address\n",
  3205. wiphy_name(hw->wiphy));
  3206. goto err_free_irq;
  3207. }
  3208. /* Disable interrupts */
  3209. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3210. free_irq(priv->pdev->irq, hw);
  3211. rc = ieee80211_register_hw(hw);
  3212. if (rc) {
  3213. printk(KERN_ERR "%s: Cannot register device\n",
  3214. wiphy_name(hw->wiphy));
  3215. goto err_free_queues;
  3216. }
  3217. printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
  3218. wiphy_name(hw->wiphy), priv->device_info->part_name,
  3219. priv->hw_rev, hw->wiphy->perm_addr,
  3220. priv->ap_fw ? "AP" : "STA",
  3221. (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
  3222. (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
  3223. return 0;
  3224. err_free_irq:
  3225. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3226. free_irq(priv->pdev->irq, hw);
  3227. err_free_queues:
  3228. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3229. mwl8k_txq_deinit(hw, i);
  3230. mwl8k_rxq_deinit(hw, 0);
  3231. err_free_cookie:
  3232. if (priv->cookie != NULL)
  3233. pci_free_consistent(priv->pdev, 4,
  3234. priv->cookie, priv->cookie_dma);
  3235. err_stop_firmware:
  3236. mwl8k_hw_reset(priv);
  3237. mwl8k_release_firmware(priv);
  3238. err_iounmap:
  3239. if (priv->regs != NULL)
  3240. pci_iounmap(pdev, priv->regs);
  3241. if (priv->sram != NULL)
  3242. pci_iounmap(pdev, priv->sram);
  3243. pci_set_drvdata(pdev, NULL);
  3244. ieee80211_free_hw(hw);
  3245. err_free_reg:
  3246. pci_release_regions(pdev);
  3247. err_disable_device:
  3248. pci_disable_device(pdev);
  3249. return rc;
  3250. }
  3251. static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
  3252. {
  3253. printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
  3254. }
  3255. static void __devexit mwl8k_remove(struct pci_dev *pdev)
  3256. {
  3257. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  3258. struct mwl8k_priv *priv;
  3259. int i;
  3260. if (hw == NULL)
  3261. return;
  3262. priv = hw->priv;
  3263. ieee80211_stop_queues(hw);
  3264. ieee80211_unregister_hw(hw);
  3265. /* Remove tx reclaim tasklet */
  3266. tasklet_kill(&priv->tx_reclaim_task);
  3267. /* Stop hardware */
  3268. mwl8k_hw_reset(priv);
  3269. /* Return all skbs to mac80211 */
  3270. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3271. mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
  3272. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3273. mwl8k_txq_deinit(hw, i);
  3274. mwl8k_rxq_deinit(hw, 0);
  3275. pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
  3276. pci_iounmap(pdev, priv->regs);
  3277. pci_iounmap(pdev, priv->sram);
  3278. pci_set_drvdata(pdev, NULL);
  3279. ieee80211_free_hw(hw);
  3280. pci_release_regions(pdev);
  3281. pci_disable_device(pdev);
  3282. }
  3283. static struct pci_driver mwl8k_driver = {
  3284. .name = MWL8K_NAME,
  3285. .id_table = mwl8k_pci_id_table,
  3286. .probe = mwl8k_probe,
  3287. .remove = __devexit_p(mwl8k_remove),
  3288. .shutdown = __devexit_p(mwl8k_shutdown),
  3289. };
  3290. static int __init mwl8k_init(void)
  3291. {
  3292. return pci_register_driver(&mwl8k_driver);
  3293. }
  3294. static void __exit mwl8k_exit(void)
  3295. {
  3296. pci_unregister_driver(&mwl8k_driver);
  3297. }
  3298. module_init(mwl8k_init);
  3299. module_exit(mwl8k_exit);
  3300. MODULE_DESCRIPTION(MWL8K_DESC);
  3301. MODULE_VERSION(MWL8K_VERSION);
  3302. MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
  3303. MODULE_LICENSE("GPL");