iwl-rx.c 37 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. unsigned long flags;
  126. u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
  127. u32 reg;
  128. int ret = 0;
  129. spin_lock_irqsave(&q->lock, flags);
  130. if (q->need_update == 0)
  131. goto exit_unlock;
  132. /* If power-saving is in use, make sure device is awake */
  133. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  134. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  135. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  136. IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n",
  137. reg);
  138. iwl_set_bit(priv, CSR_GP_CNTRL,
  139. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  140. goto exit_unlock;
  141. }
  142. q->write_actual = (q->write & ~0x7);
  143. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  144. /* Else device is assumed to be awake */
  145. } else {
  146. /* Device expects a multiple of 8 */
  147. q->write_actual = (q->write & ~0x7);
  148. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  149. }
  150. q->need_update = 0;
  151. exit_unlock:
  152. spin_unlock_irqrestore(&q->lock, flags);
  153. return ret;
  154. }
  155. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  156. /**
  157. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  158. */
  159. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  160. dma_addr_t dma_addr)
  161. {
  162. return cpu_to_le32((u32)(dma_addr >> 8));
  163. }
  164. /**
  165. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  166. *
  167. * If there are slots in the RX queue that need to be restocked,
  168. * and we have free pre-allocated buffers, fill the ranks as much
  169. * as we can, pulling from rx_free.
  170. *
  171. * This moves the 'write' index forward to catch up with 'processed', and
  172. * also updates the memory address in the firmware to reference the new
  173. * target buffer.
  174. */
  175. int iwl_rx_queue_restock(struct iwl_priv *priv)
  176. {
  177. struct iwl_rx_queue *rxq = &priv->rxq;
  178. struct list_head *element;
  179. struct iwl_rx_mem_buffer *rxb;
  180. unsigned long flags;
  181. int write;
  182. int ret = 0;
  183. spin_lock_irqsave(&rxq->lock, flags);
  184. write = rxq->write & ~0x7;
  185. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  186. /* Get next free Rx buffer, remove from free list */
  187. element = rxq->rx_free.next;
  188. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  189. list_del(element);
  190. /* Point to Rx buffer via next RBD in circular buffer */
  191. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma);
  192. rxq->queue[rxq->write] = rxb;
  193. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  194. rxq->free_count--;
  195. }
  196. spin_unlock_irqrestore(&rxq->lock, flags);
  197. /* If the pre-allocated buffer pool is dropping low, schedule to
  198. * refill it */
  199. if (rxq->free_count <= RX_LOW_WATERMARK)
  200. queue_work(priv->workqueue, &priv->rx_replenish);
  201. /* If we've added more space for the firmware to place data, tell it.
  202. * Increment device's write pointer in multiples of 8. */
  203. if (rxq->write_actual != (rxq->write & ~0x7)) {
  204. spin_lock_irqsave(&rxq->lock, flags);
  205. rxq->need_update = 1;
  206. spin_unlock_irqrestore(&rxq->lock, flags);
  207. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  208. }
  209. return ret;
  210. }
  211. EXPORT_SYMBOL(iwl_rx_queue_restock);
  212. /**
  213. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  214. *
  215. * When moving to rx_free an SKB is allocated for the slot.
  216. *
  217. * Also restock the Rx queue via iwl_rx_queue_restock.
  218. * This is called as a scheduled work item (except for during initialization)
  219. */
  220. void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  221. {
  222. struct iwl_rx_queue *rxq = &priv->rxq;
  223. struct list_head *element;
  224. struct iwl_rx_mem_buffer *rxb;
  225. struct page *page;
  226. unsigned long flags;
  227. gfp_t gfp_mask = priority;
  228. while (1) {
  229. spin_lock_irqsave(&rxq->lock, flags);
  230. if (list_empty(&rxq->rx_used)) {
  231. spin_unlock_irqrestore(&rxq->lock, flags);
  232. return;
  233. }
  234. spin_unlock_irqrestore(&rxq->lock, flags);
  235. if (rxq->free_count > RX_LOW_WATERMARK)
  236. gfp_mask |= __GFP_NOWARN;
  237. if (priv->hw_params.rx_page_order > 0)
  238. gfp_mask |= __GFP_COMP;
  239. /* Alloc a new receive buffer */
  240. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  241. if (!page) {
  242. if (net_ratelimit())
  243. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  244. "order: %d\n",
  245. priv->hw_params.rx_page_order);
  246. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  247. net_ratelimit())
  248. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  249. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  250. rxq->free_count);
  251. /* We don't reschedule replenish work here -- we will
  252. * call the restock method and if it still needs
  253. * more buffers it will schedule replenish */
  254. return;
  255. }
  256. spin_lock_irqsave(&rxq->lock, flags);
  257. if (list_empty(&rxq->rx_used)) {
  258. spin_unlock_irqrestore(&rxq->lock, flags);
  259. __free_pages(page, priv->hw_params.rx_page_order);
  260. return;
  261. }
  262. element = rxq->rx_used.next;
  263. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  264. list_del(element);
  265. spin_unlock_irqrestore(&rxq->lock, flags);
  266. rxb->page = page;
  267. /* Get physical address of the RB */
  268. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  269. PAGE_SIZE << priv->hw_params.rx_page_order,
  270. PCI_DMA_FROMDEVICE);
  271. /* dma address must be no more than 36 bits */
  272. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  273. /* and also 256 byte aligned! */
  274. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  275. spin_lock_irqsave(&rxq->lock, flags);
  276. list_add_tail(&rxb->list, &rxq->rx_free);
  277. rxq->free_count++;
  278. priv->alloc_rxb_page++;
  279. spin_unlock_irqrestore(&rxq->lock, flags);
  280. }
  281. }
  282. void iwl_rx_replenish(struct iwl_priv *priv)
  283. {
  284. unsigned long flags;
  285. iwl_rx_allocate(priv, GFP_KERNEL);
  286. spin_lock_irqsave(&priv->lock, flags);
  287. iwl_rx_queue_restock(priv);
  288. spin_unlock_irqrestore(&priv->lock, flags);
  289. }
  290. EXPORT_SYMBOL(iwl_rx_replenish);
  291. void iwl_rx_replenish_now(struct iwl_priv *priv)
  292. {
  293. iwl_rx_allocate(priv, GFP_ATOMIC);
  294. iwl_rx_queue_restock(priv);
  295. }
  296. EXPORT_SYMBOL(iwl_rx_replenish_now);
  297. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  298. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  299. * This free routine walks the list of POOL entries and if SKB is set to
  300. * non NULL it is unmapped and freed
  301. */
  302. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  303. {
  304. int i;
  305. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  306. if (rxq->pool[i].page != NULL) {
  307. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  308. PAGE_SIZE << priv->hw_params.rx_page_order,
  309. PCI_DMA_FROMDEVICE);
  310. __free_pages(rxq->pool[i].page,
  311. priv->hw_params.rx_page_order);
  312. rxq->pool[i].page = NULL;
  313. priv->alloc_rxb_page--;
  314. }
  315. }
  316. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  317. rxq->dma_addr);
  318. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  319. rxq->rb_stts, rxq->rb_stts_dma);
  320. rxq->bd = NULL;
  321. rxq->rb_stts = NULL;
  322. }
  323. EXPORT_SYMBOL(iwl_rx_queue_free);
  324. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  325. {
  326. struct iwl_rx_queue *rxq = &priv->rxq;
  327. struct pci_dev *dev = priv->pci_dev;
  328. int i;
  329. spin_lock_init(&rxq->lock);
  330. INIT_LIST_HEAD(&rxq->rx_free);
  331. INIT_LIST_HEAD(&rxq->rx_used);
  332. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  333. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  334. if (!rxq->bd)
  335. goto err_bd;
  336. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  337. &rxq->rb_stts_dma);
  338. if (!rxq->rb_stts)
  339. goto err_rb;
  340. /* Fill the rx_used queue with _all_ of the Rx buffers */
  341. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  342. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  343. /* Set us so that we have processed and used all buffers, but have
  344. * not restocked the Rx queue with fresh buffers */
  345. rxq->read = rxq->write = 0;
  346. rxq->write_actual = 0;
  347. rxq->free_count = 0;
  348. rxq->need_update = 0;
  349. return 0;
  350. err_rb:
  351. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  352. rxq->dma_addr);
  353. err_bd:
  354. return -ENOMEM;
  355. }
  356. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  357. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  358. {
  359. unsigned long flags;
  360. int i;
  361. spin_lock_irqsave(&rxq->lock, flags);
  362. INIT_LIST_HEAD(&rxq->rx_free);
  363. INIT_LIST_HEAD(&rxq->rx_used);
  364. /* Fill the rx_used queue with _all_ of the Rx buffers */
  365. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  366. /* In the reset function, these buffers may have been allocated
  367. * to an SKB, so we need to unmap and free potential storage */
  368. if (rxq->pool[i].page != NULL) {
  369. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  370. PAGE_SIZE << priv->hw_params.rx_page_order,
  371. PCI_DMA_FROMDEVICE);
  372. priv->alloc_rxb_page--;
  373. __free_pages(rxq->pool[i].page,
  374. priv->hw_params.rx_page_order);
  375. rxq->pool[i].page = NULL;
  376. }
  377. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  378. }
  379. /* Set us so that we have processed and used all buffers, but have
  380. * not restocked the Rx queue with fresh buffers */
  381. rxq->read = rxq->write = 0;
  382. rxq->write_actual = 0;
  383. rxq->free_count = 0;
  384. spin_unlock_irqrestore(&rxq->lock, flags);
  385. }
  386. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  387. {
  388. u32 rb_size;
  389. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  390. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  391. if (!priv->cfg->use_isr_legacy)
  392. rb_timeout = RX_RB_TIMEOUT;
  393. if (priv->cfg->mod_params->amsdu_size_8K)
  394. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  395. else
  396. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  397. /* Stop Rx DMA */
  398. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  399. /* Reset driver's Rx queue write index */
  400. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  401. /* Tell device where to find RBD circular buffer in DRAM */
  402. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  403. (u32)(rxq->dma_addr >> 8));
  404. /* Tell device where in DRAM to update its Rx status */
  405. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  406. rxq->rb_stts_dma >> 4);
  407. /* Enable Rx DMA
  408. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  409. * the credit mechanism in 5000 HW RX FIFO
  410. * Direct rx interrupts to hosts
  411. * Rx buffer size 4 or 8k
  412. * RB timeout 0x10
  413. * 256 RBDs
  414. */
  415. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  416. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  417. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  418. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  419. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  420. rb_size|
  421. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  422. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  423. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  424. return 0;
  425. }
  426. int iwl_rxq_stop(struct iwl_priv *priv)
  427. {
  428. /* stop Rx DMA */
  429. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  430. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  431. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  432. return 0;
  433. }
  434. EXPORT_SYMBOL(iwl_rxq_stop);
  435. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  436. struct iwl_rx_mem_buffer *rxb)
  437. {
  438. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  439. struct iwl_missed_beacon_notif *missed_beacon;
  440. missed_beacon = &pkt->u.missed_beacon;
  441. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  442. IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  443. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  444. le32_to_cpu(missed_beacon->total_missed_becons),
  445. le32_to_cpu(missed_beacon->num_recvd_beacons),
  446. le32_to_cpu(missed_beacon->num_expected_beacons));
  447. if (!test_bit(STATUS_SCANNING, &priv->status))
  448. iwl_init_sensitivity(priv);
  449. }
  450. }
  451. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  452. /* Calculate noise level, based on measurements during network silence just
  453. * before arriving beacon. This measurement can be done only if we know
  454. * exactly when to expect beacons, therefore only when we're associated. */
  455. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  456. {
  457. struct statistics_rx_non_phy *rx_info
  458. = &(priv->statistics.rx.general);
  459. int num_active_rx = 0;
  460. int total_silence = 0;
  461. int bcn_silence_a =
  462. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  463. int bcn_silence_b =
  464. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  465. int bcn_silence_c =
  466. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  467. if (bcn_silence_a) {
  468. total_silence += bcn_silence_a;
  469. num_active_rx++;
  470. }
  471. if (bcn_silence_b) {
  472. total_silence += bcn_silence_b;
  473. num_active_rx++;
  474. }
  475. if (bcn_silence_c) {
  476. total_silence += bcn_silence_c;
  477. num_active_rx++;
  478. }
  479. /* Average among active antennas */
  480. if (num_active_rx)
  481. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  482. else
  483. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  484. IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
  485. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  486. priv->last_rx_noise);
  487. }
  488. #ifdef CONFIG_IWLWIFI_DEBUG
  489. /*
  490. * based on the assumption of all statistics counter are in DWORD
  491. * FIXME: This function is for debugging, do not deal with
  492. * the case of counters roll-over.
  493. */
  494. static void iwl_accumulative_statistics(struct iwl_priv *priv,
  495. __le32 *stats)
  496. {
  497. int i;
  498. __le32 *prev_stats;
  499. u32 *accum_stats;
  500. prev_stats = (__le32 *)&priv->statistics;
  501. accum_stats = (u32 *)&priv->accum_statistics;
  502. for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics);
  503. i += sizeof(__le32), stats++, prev_stats++, accum_stats++)
  504. if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats))
  505. *accum_stats += (le32_to_cpu(*stats) -
  506. le32_to_cpu(*prev_stats));
  507. /* reset accumulative statistics for "no-counter" type statistics */
  508. priv->accum_statistics.general.temperature =
  509. priv->statistics.general.temperature;
  510. priv->accum_statistics.general.temperature_m =
  511. priv->statistics.general.temperature_m;
  512. priv->accum_statistics.general.ttl_timestamp =
  513. priv->statistics.general.ttl_timestamp;
  514. priv->accum_statistics.tx.tx_power.ant_a =
  515. priv->statistics.tx.tx_power.ant_a;
  516. priv->accum_statistics.tx.tx_power.ant_b =
  517. priv->statistics.tx.tx_power.ant_b;
  518. priv->accum_statistics.tx.tx_power.ant_c =
  519. priv->statistics.tx.tx_power.ant_c;
  520. }
  521. #endif
  522. #define REG_RECALIB_PERIOD (60)
  523. void iwl_rx_statistics(struct iwl_priv *priv,
  524. struct iwl_rx_mem_buffer *rxb)
  525. {
  526. int change;
  527. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  528. IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
  529. (int)sizeof(priv->statistics),
  530. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  531. change = ((priv->statistics.general.temperature !=
  532. pkt->u.stats.general.temperature) ||
  533. ((priv->statistics.flag &
  534. STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
  535. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
  536. #ifdef CONFIG_IWLWIFI_DEBUG
  537. iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
  538. #endif
  539. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  540. set_bit(STATUS_STATISTICS, &priv->status);
  541. /* Reschedule the statistics timer to occur in
  542. * REG_RECALIB_PERIOD seconds to ensure we get a
  543. * thermal update even if the uCode doesn't give
  544. * us one */
  545. mod_timer(&priv->statistics_periodic, jiffies +
  546. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  547. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  548. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  549. iwl_rx_calc_noise(priv);
  550. queue_work(priv->workqueue, &priv->run_time_calib_work);
  551. }
  552. if (priv->cfg->ops->lib->temp_ops.temperature && change)
  553. priv->cfg->ops->lib->temp_ops.temperature(priv);
  554. }
  555. EXPORT_SYMBOL(iwl_rx_statistics);
  556. void iwl_reply_statistics(struct iwl_priv *priv,
  557. struct iwl_rx_mem_buffer *rxb)
  558. {
  559. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  560. if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
  561. memset(&priv->statistics, 0,
  562. sizeof(struct iwl_notif_statistics));
  563. #ifdef CONFIG_IWLWIFI_DEBUG
  564. memset(&priv->accum_statistics, 0,
  565. sizeof(struct iwl_notif_statistics));
  566. #endif
  567. IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
  568. }
  569. iwl_rx_statistics(priv, rxb);
  570. }
  571. EXPORT_SYMBOL(iwl_reply_statistics);
  572. #define PERFECT_RSSI (-20) /* dBm */
  573. #define WORST_RSSI (-95) /* dBm */
  574. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  575. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  576. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  577. * about formulas used below. */
  578. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  579. {
  580. int sig_qual;
  581. int degradation = PERFECT_RSSI - rssi_dbm;
  582. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  583. * as indicator; formula is (signal dbm - noise dbm).
  584. * SNR at or above 40 is a great signal (100%).
  585. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  586. * Weakest usable signal is usually 10 - 15 dB SNR. */
  587. if (noise_dbm) {
  588. if (rssi_dbm - noise_dbm >= 40)
  589. return 100;
  590. else if (rssi_dbm < noise_dbm)
  591. return 0;
  592. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  593. /* Else use just the signal level.
  594. * This formula is a least squares fit of data points collected and
  595. * compared with a reference system that had a percentage (%) display
  596. * for signal quality. */
  597. } else
  598. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  599. (15 * RSSI_RANGE + 62 * degradation)) /
  600. (RSSI_RANGE * RSSI_RANGE);
  601. if (sig_qual > 100)
  602. sig_qual = 100;
  603. else if (sig_qual < 1)
  604. sig_qual = 0;
  605. return sig_qual;
  606. }
  607. /* Calc max signal level (dBm) among 3 possible receivers */
  608. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  609. struct iwl_rx_phy_res *rx_resp)
  610. {
  611. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  612. }
  613. #ifdef CONFIG_IWLWIFI_DEBUG
  614. /**
  615. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  616. *
  617. * You may hack this function to show different aspects of received frames,
  618. * including selective frame dumps.
  619. * group100 parameter selects whether to show 1 out of 100 good data frames.
  620. * All beacon and probe response frames are printed.
  621. */
  622. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  623. struct iwl_rx_phy_res *phy_res, u16 length,
  624. struct ieee80211_hdr *header, int group100)
  625. {
  626. u32 to_us;
  627. u32 print_summary = 0;
  628. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  629. u32 hundred = 0;
  630. u32 dataframe = 0;
  631. __le16 fc;
  632. u16 seq_ctl;
  633. u16 channel;
  634. u16 phy_flags;
  635. u32 rate_n_flags;
  636. u32 tsf_low;
  637. int rssi;
  638. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  639. return;
  640. /* MAC header */
  641. fc = header->frame_control;
  642. seq_ctl = le16_to_cpu(header->seq_ctrl);
  643. /* metadata */
  644. channel = le16_to_cpu(phy_res->channel);
  645. phy_flags = le16_to_cpu(phy_res->phy_flags);
  646. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  647. /* signal statistics */
  648. rssi = iwl_calc_rssi(priv, phy_res);
  649. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  650. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  651. /* if data frame is to us and all is good,
  652. * (optionally) print summary for only 1 out of every 100 */
  653. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  654. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  655. dataframe = 1;
  656. if (!group100)
  657. print_summary = 1; /* print each frame */
  658. else if (priv->framecnt_to_us < 100) {
  659. priv->framecnt_to_us++;
  660. print_summary = 0;
  661. } else {
  662. priv->framecnt_to_us = 0;
  663. print_summary = 1;
  664. hundred = 1;
  665. }
  666. } else {
  667. /* print summary for all other frames */
  668. print_summary = 1;
  669. }
  670. if (print_summary) {
  671. char *title;
  672. int rate_idx;
  673. u32 bitrate;
  674. if (hundred)
  675. title = "100Frames";
  676. else if (ieee80211_has_retry(fc))
  677. title = "Retry";
  678. else if (ieee80211_is_assoc_resp(fc))
  679. title = "AscRsp";
  680. else if (ieee80211_is_reassoc_resp(fc))
  681. title = "RasRsp";
  682. else if (ieee80211_is_probe_resp(fc)) {
  683. title = "PrbRsp";
  684. print_dump = 1; /* dump frame contents */
  685. } else if (ieee80211_is_beacon(fc)) {
  686. title = "Beacon";
  687. print_dump = 1; /* dump frame contents */
  688. } else if (ieee80211_is_atim(fc))
  689. title = "ATIM";
  690. else if (ieee80211_is_auth(fc))
  691. title = "Auth";
  692. else if (ieee80211_is_deauth(fc))
  693. title = "DeAuth";
  694. else if (ieee80211_is_disassoc(fc))
  695. title = "DisAssoc";
  696. else
  697. title = "Frame";
  698. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  699. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  700. bitrate = 0;
  701. WARN_ON_ONCE(1);
  702. } else {
  703. bitrate = iwl_rates[rate_idx].ieee / 2;
  704. }
  705. /* print frame summary.
  706. * MAC addresses show just the last byte (for brevity),
  707. * but you can hack it to show more, if you'd like to. */
  708. if (dataframe)
  709. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  710. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  711. title, le16_to_cpu(fc), header->addr1[5],
  712. length, rssi, channel, bitrate);
  713. else {
  714. /* src/dst addresses assume managed mode */
  715. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  716. "len=%u, rssi=%d, tim=%lu usec, "
  717. "phy=0x%02x, chnl=%d\n",
  718. title, le16_to_cpu(fc), header->addr1[5],
  719. header->addr3[5], length, rssi,
  720. tsf_low - priv->scan_start_tsf,
  721. phy_flags, channel);
  722. }
  723. }
  724. if (print_dump)
  725. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  726. }
  727. #endif
  728. /*
  729. * returns non-zero if packet should be dropped
  730. */
  731. int iwl_set_decrypted_flag(struct iwl_priv *priv,
  732. struct ieee80211_hdr *hdr,
  733. u32 decrypt_res,
  734. struct ieee80211_rx_status *stats)
  735. {
  736. u16 fc = le16_to_cpu(hdr->frame_control);
  737. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  738. return 0;
  739. if (!(fc & IEEE80211_FCTL_PROTECTED))
  740. return 0;
  741. IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res);
  742. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  743. case RX_RES_STATUS_SEC_TYPE_TKIP:
  744. /* The uCode has got a bad phase 1 Key, pushes the packet.
  745. * Decryption will be done in SW. */
  746. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  747. RX_RES_STATUS_BAD_KEY_TTAK)
  748. break;
  749. case RX_RES_STATUS_SEC_TYPE_WEP:
  750. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  751. RX_RES_STATUS_BAD_ICV_MIC) {
  752. /* bad ICV, the packet is destroyed since the
  753. * decryption is inplace, drop it */
  754. IWL_DEBUG_RX(priv, "Packet destroyed\n");
  755. return -1;
  756. }
  757. case RX_RES_STATUS_SEC_TYPE_CCMP:
  758. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  759. RX_RES_STATUS_DECRYPT_OK) {
  760. IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n");
  761. stats->flag |= RX_FLAG_DECRYPTED;
  762. }
  763. break;
  764. default:
  765. break;
  766. }
  767. return 0;
  768. }
  769. EXPORT_SYMBOL(iwl_set_decrypted_flag);
  770. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  771. {
  772. u32 decrypt_out = 0;
  773. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  774. RX_RES_STATUS_STATION_FOUND)
  775. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  776. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  777. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  778. /* packet was not encrypted */
  779. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  780. RX_RES_STATUS_SEC_TYPE_NONE)
  781. return decrypt_out;
  782. /* packet was encrypted with unknown alg */
  783. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  784. RX_RES_STATUS_SEC_TYPE_ERR)
  785. return decrypt_out;
  786. /* decryption was not done in HW */
  787. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  788. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  789. return decrypt_out;
  790. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  791. case RX_RES_STATUS_SEC_TYPE_CCMP:
  792. /* alg is CCM: check MIC only */
  793. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  794. /* Bad MIC */
  795. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  796. else
  797. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  798. break;
  799. case RX_RES_STATUS_SEC_TYPE_TKIP:
  800. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  801. /* Bad TTAK */
  802. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  803. break;
  804. }
  805. /* fall through if TTAK OK */
  806. default:
  807. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  808. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  809. else
  810. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  811. break;
  812. };
  813. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  814. decrypt_in, decrypt_out);
  815. return decrypt_out;
  816. }
  817. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  818. struct ieee80211_hdr *hdr,
  819. u16 len,
  820. u32 ampdu_status,
  821. struct iwl_rx_mem_buffer *rxb,
  822. struct ieee80211_rx_status *stats)
  823. {
  824. struct sk_buff *skb;
  825. int ret = 0;
  826. __le16 fc = hdr->frame_control;
  827. /* We only process data packets if the interface is open */
  828. if (unlikely(!priv->is_open)) {
  829. IWL_DEBUG_DROP_LIMIT(priv,
  830. "Dropping packet while interface is not open.\n");
  831. return;
  832. }
  833. /* In case of HW accelerated crypto and bad decryption, drop */
  834. if (!priv->cfg->mod_params->sw_crypto &&
  835. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  836. return;
  837. skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
  838. if (!skb) {
  839. IWL_ERR(priv, "alloc_skb failed\n");
  840. return;
  841. }
  842. skb_reserve(skb, IWL_LINK_HDR_MAX);
  843. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  844. /* mac80211 currently doesn't support paged SKB. Convert it to
  845. * linear SKB for management frame and data frame requires
  846. * software decryption or software defragementation. */
  847. if (ieee80211_is_mgmt(fc) ||
  848. ieee80211_has_protected(fc) ||
  849. ieee80211_has_morefrags(fc) ||
  850. le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
  851. ret = skb_linearize(skb);
  852. else
  853. ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
  854. 0 : -ENOMEM;
  855. if (ret) {
  856. kfree_skb(skb);
  857. goto out;
  858. }
  859. /*
  860. * XXX: We cannot touch the page and its virtual memory (hdr) after
  861. * here. It might have already been freed by the above skb change.
  862. */
  863. iwl_update_stats(priv, false, fc, len);
  864. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  865. ieee80211_rx(priv->hw, skb);
  866. out:
  867. priv->alloc_rxb_page--;
  868. rxb->page = NULL;
  869. }
  870. /* This is necessary only for a number of statistics, see the caller. */
  871. static int iwl_is_network_packet(struct iwl_priv *priv,
  872. struct ieee80211_hdr *header)
  873. {
  874. /* Filter incoming packets to determine if they are targeted toward
  875. * this network, discarding packets coming from ourselves */
  876. switch (priv->iw_mode) {
  877. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  878. /* packets to our IBSS update information */
  879. return !compare_ether_addr(header->addr3, priv->bssid);
  880. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  881. /* packets to our IBSS update information */
  882. return !compare_ether_addr(header->addr2, priv->bssid);
  883. default:
  884. return 1;
  885. }
  886. }
  887. /* Called for REPLY_RX (legacy ABG frames), or
  888. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  889. void iwl_rx_reply_rx(struct iwl_priv *priv,
  890. struct iwl_rx_mem_buffer *rxb)
  891. {
  892. struct ieee80211_hdr *header;
  893. struct ieee80211_rx_status rx_status;
  894. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  895. struct iwl_rx_phy_res *phy_res;
  896. __le32 rx_pkt_status;
  897. struct iwl4965_rx_mpdu_res_start *amsdu;
  898. u32 len;
  899. u32 ampdu_status;
  900. u16 fc;
  901. u32 rate_n_flags;
  902. /**
  903. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  904. * REPLY_RX: physical layer info is in this buffer
  905. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  906. * command and cached in priv->last_phy_res
  907. *
  908. * Here we set up local variables depending on which command is
  909. * received.
  910. */
  911. if (pkt->hdr.cmd == REPLY_RX) {
  912. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  913. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  914. + phy_res->cfg_phy_cnt);
  915. len = le16_to_cpu(phy_res->byte_count);
  916. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  917. phy_res->cfg_phy_cnt + len);
  918. ampdu_status = le32_to_cpu(rx_pkt_status);
  919. } else {
  920. if (!priv->last_phy_res[0]) {
  921. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  922. return;
  923. }
  924. phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  925. amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  926. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  927. len = le16_to_cpu(amsdu->byte_count);
  928. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  929. ampdu_status = iwl_translate_rx_status(priv,
  930. le32_to_cpu(rx_pkt_status));
  931. }
  932. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  933. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  934. phy_res->cfg_phy_cnt);
  935. return;
  936. }
  937. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  938. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  939. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  940. le32_to_cpu(rx_pkt_status));
  941. return;
  942. }
  943. /* This will be used in several places later */
  944. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  945. /* rx_status carries information about the packet to mac80211 */
  946. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  947. rx_status.freq =
  948. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  949. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  950. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  951. rx_status.rate_idx =
  952. iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  953. rx_status.flag = 0;
  954. /* TSF isn't reliable. In order to allow smooth user experience,
  955. * this W/A doesn't propagate it to the mac80211 */
  956. /*rx_status.flag |= RX_FLAG_TSFT;*/
  957. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  958. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  959. rx_status.signal = iwl_calc_rssi(priv, phy_res);
  960. /* Meaningful noise values are available only from beacon statistics,
  961. * which are gathered only when associated, and indicate noise
  962. * only for the associated network channel ...
  963. * Ignore these noise values while scanning (other channels) */
  964. if (iwl_is_associated(priv) &&
  965. !test_bit(STATUS_SCANNING, &priv->status)) {
  966. rx_status.noise = priv->last_rx_noise;
  967. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  968. rx_status.noise);
  969. } else {
  970. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  971. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  972. }
  973. /* Reset beacon noise level if not associated. */
  974. if (!iwl_is_associated(priv))
  975. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  976. #ifdef CONFIG_IWLWIFI_DEBUG
  977. /* Set "1" to report good data frames in groups of 100 */
  978. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  979. iwl_dbg_report_frame(priv, phy_res, len, header, 1);
  980. #endif
  981. iwl_dbg_log_rx_data_frame(priv, len, header);
  982. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, qual %d, TSF %llu\n",
  983. rx_status.signal, rx_status.noise, rx_status.qual,
  984. (unsigned long long)rx_status.mactime);
  985. /*
  986. * "antenna number"
  987. *
  988. * It seems that the antenna field in the phy flags value
  989. * is actually a bit field. This is undefined by radiotap,
  990. * it wants an actual antenna number but I always get "7"
  991. * for most legacy frames I receive indicating that the
  992. * same frame was received on all three RX chains.
  993. *
  994. * I think this field should be removed in favor of a
  995. * new 802.11n radiotap field "RX chains" that is defined
  996. * as a bitmask.
  997. */
  998. rx_status.antenna =
  999. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  1000. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  1001. /* set the preamble flag if appropriate */
  1002. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1003. rx_status.flag |= RX_FLAG_SHORTPRE;
  1004. /* Set up the HT phy flags */
  1005. if (rate_n_flags & RATE_MCS_HT_MSK)
  1006. rx_status.flag |= RX_FLAG_HT;
  1007. if (rate_n_flags & RATE_MCS_HT40_MSK)
  1008. rx_status.flag |= RX_FLAG_40MHZ;
  1009. if (rate_n_flags & RATE_MCS_SGI_MSK)
  1010. rx_status.flag |= RX_FLAG_SHORT_GI;
  1011. if (iwl_is_network_packet(priv, header)) {
  1012. priv->last_rx_rssi = rx_status.signal;
  1013. priv->last_beacon_time = priv->ucode_beacon_time;
  1014. priv->last_tsf = le64_to_cpu(phy_res->timestamp);
  1015. }
  1016. fc = le16_to_cpu(header->frame_control);
  1017. switch (fc & IEEE80211_FCTL_FTYPE) {
  1018. case IEEE80211_FTYPE_MGMT:
  1019. case IEEE80211_FTYPE_DATA:
  1020. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1021. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  1022. header->addr2);
  1023. /* fall through */
  1024. default:
  1025. iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  1026. rxb, &rx_status);
  1027. break;
  1028. }
  1029. }
  1030. EXPORT_SYMBOL(iwl_rx_reply_rx);
  1031. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1032. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1033. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  1034. struct iwl_rx_mem_buffer *rxb)
  1035. {
  1036. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1037. priv->last_phy_res[0] = 1;
  1038. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  1039. sizeof(struct iwl_rx_phy_res));
  1040. }
  1041. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);