video1394.c 42 KB

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  1. /*
  2. * video1394.c - video driver for OHCI 1394 boards
  3. * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
  4. * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. * NOTES:
  21. *
  22. * jds -- add private data to file to keep track of iso contexts associated
  23. * with each open -- so release won't kill all iso transfers.
  24. *
  25. * Damien Douxchamps: Fix failure when the number of DMA pages per frame is
  26. * one.
  27. *
  28. * ioctl return codes:
  29. * EFAULT is only for invalid address for the argp
  30. * EINVAL for out of range values
  31. * EBUSY when trying to use an already used resource
  32. * ESRCH when trying to free/stop a not used resource
  33. * EAGAIN for resource allocation failure that could perhaps succeed later
  34. * ENOTTY for unsupported ioctl request
  35. *
  36. */
  37. /* Markus Tavenrath <speedygoo@speedygoo.de> :
  38. - fixed checks for valid buffer-numbers in video1394_icotl
  39. - changed the ways the dma prg's are used, now it's possible to use
  40. even a single dma buffer
  41. */
  42. #include <linux/config.h>
  43. #include <linux/kernel.h>
  44. #include <linux/list.h>
  45. #include <linux/slab.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/wait.h>
  48. #include <linux/errno.h>
  49. #include <linux/module.h>
  50. #include <linux/init.h>
  51. #include <linux/pci.h>
  52. #include <linux/fs.h>
  53. #include <linux/poll.h>
  54. #include <linux/smp_lock.h>
  55. #include <linux/delay.h>
  56. #include <linux/devfs_fs_kernel.h>
  57. #include <linux/bitops.h>
  58. #include <linux/types.h>
  59. #include <linux/vmalloc.h>
  60. #include <linux/timex.h>
  61. #include <linux/mm.h>
  62. #include <linux/ioctl32.h>
  63. #include <linux/compat.h>
  64. #include <linux/cdev.h>
  65. #include "ieee1394.h"
  66. #include "ieee1394_types.h"
  67. #include "hosts.h"
  68. #include "ieee1394_core.h"
  69. #include "highlevel.h"
  70. #include "video1394.h"
  71. #include "nodemgr.h"
  72. #include "dma.h"
  73. #include "ohci1394.h"
  74. #define ISO_CHANNELS 64
  75. struct it_dma_prg {
  76. struct dma_cmd begin;
  77. quadlet_t data[4];
  78. struct dma_cmd end;
  79. quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
  80. };
  81. struct dma_iso_ctx {
  82. struct ti_ohci *ohci;
  83. int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
  84. struct ohci1394_iso_tasklet iso_tasklet;
  85. int channel;
  86. int ctx;
  87. int last_buffer;
  88. int * next_buffer; /* For ISO Transmit of video packets
  89. to write the correct SYT field
  90. into the next block */
  91. unsigned int num_desc;
  92. unsigned int buf_size;
  93. unsigned int frame_size;
  94. unsigned int packet_size;
  95. unsigned int left_size;
  96. unsigned int nb_cmd;
  97. struct dma_region dma;
  98. struct dma_prog_region *prg_reg;
  99. struct dma_cmd **ir_prg;
  100. struct it_dma_prg **it_prg;
  101. unsigned int *buffer_status;
  102. unsigned int *buffer_prg_assignment;
  103. struct timeval *buffer_time; /* time when the buffer was received */
  104. unsigned int *last_used_cmd; /* For ISO Transmit with
  105. variable sized packets only ! */
  106. int ctrlClear;
  107. int ctrlSet;
  108. int cmdPtr;
  109. int ctxMatch;
  110. wait_queue_head_t waitq;
  111. spinlock_t lock;
  112. unsigned int syt_offset;
  113. int flags;
  114. struct list_head link;
  115. };
  116. struct file_ctx {
  117. struct ti_ohci *ohci;
  118. struct list_head context_list;
  119. struct dma_iso_ctx *current_ctx;
  120. };
  121. #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
  122. #define VIDEO1394_DEBUG
  123. #endif
  124. #ifdef DBGMSG
  125. #undef DBGMSG
  126. #endif
  127. #ifdef VIDEO1394_DEBUG
  128. #define DBGMSG(card, fmt, args...) \
  129. printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
  130. #else
  131. #define DBGMSG(card, fmt, args...)
  132. #endif
  133. /* print general (card independent) information */
  134. #define PRINT_G(level, fmt, args...) \
  135. printk(level "video1394: " fmt "\n" , ## args)
  136. /* print card specific information */
  137. #define PRINT(level, card, fmt, args...) \
  138. printk(level "video1394_%d: " fmt "\n" , card , ## args)
  139. static void wakeup_dma_ir_ctx(unsigned long l);
  140. static void wakeup_dma_it_ctx(unsigned long l);
  141. static struct hpsb_highlevel video1394_highlevel;
  142. static int free_dma_iso_ctx(struct dma_iso_ctx *d)
  143. {
  144. int i;
  145. DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
  146. ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
  147. if (d->iso_tasklet.link.next != NULL)
  148. ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
  149. dma_region_free(&d->dma);
  150. if (d->prg_reg) {
  151. for (i = 0; i < d->num_desc; i++)
  152. dma_prog_region_free(&d->prg_reg[i]);
  153. kfree(d->prg_reg);
  154. }
  155. kfree(d->ir_prg);
  156. kfree(d->it_prg);
  157. kfree(d->buffer_status);
  158. kfree(d->buffer_prg_assignment);
  159. kfree(d->buffer_time);
  160. kfree(d->last_used_cmd);
  161. kfree(d->next_buffer);
  162. list_del(&d->link);
  163. kfree(d);
  164. return 0;
  165. }
  166. static struct dma_iso_ctx *
  167. alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
  168. int buf_size, int channel, unsigned int packet_size)
  169. {
  170. struct dma_iso_ctx *d;
  171. int i;
  172. d = kzalloc(sizeof(*d), GFP_KERNEL);
  173. if (!d) {
  174. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
  175. return NULL;
  176. }
  177. d->ohci = ohci;
  178. d->type = type;
  179. d->channel = channel;
  180. d->num_desc = num_desc;
  181. d->frame_size = buf_size;
  182. d->buf_size = PAGE_ALIGN(buf_size);
  183. d->last_buffer = -1;
  184. INIT_LIST_HEAD(&d->link);
  185. init_waitqueue_head(&d->waitq);
  186. /* Init the regions for easy cleanup */
  187. dma_region_init(&d->dma);
  188. if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
  189. PCI_DMA_BIDIRECTIONAL)) {
  190. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
  191. free_dma_iso_ctx(d);
  192. return NULL;
  193. }
  194. if (type == OHCI_ISO_RECEIVE)
  195. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  196. wakeup_dma_ir_ctx,
  197. (unsigned long) d);
  198. else
  199. ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
  200. wakeup_dma_it_ctx,
  201. (unsigned long) d);
  202. if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
  203. PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
  204. type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
  205. free_dma_iso_ctx(d);
  206. return NULL;
  207. }
  208. d->ctx = d->iso_tasklet.context;
  209. d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
  210. if (!d->prg_reg) {
  211. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
  212. free_dma_iso_ctx(d);
  213. return NULL;
  214. }
  215. /* Makes for easier cleanup */
  216. for (i = 0; i < d->num_desc; i++)
  217. dma_prog_region_init(&d->prg_reg[i]);
  218. if (type == OHCI_ISO_RECEIVE) {
  219. d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
  220. d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
  221. d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
  222. d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
  223. d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
  224. GFP_KERNEL);
  225. if (!d->ir_prg) {
  226. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  227. free_dma_iso_ctx(d);
  228. return NULL;
  229. }
  230. d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
  231. d->left_size = (d->frame_size % PAGE_SIZE) ?
  232. d->frame_size % PAGE_SIZE : PAGE_SIZE;
  233. for (i = 0;i < d->num_desc; i++) {
  234. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  235. sizeof(struct dma_cmd), ohci->dev)) {
  236. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
  237. free_dma_iso_ctx(d);
  238. return NULL;
  239. }
  240. d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
  241. }
  242. } else { /* OHCI_ISO_TRANSMIT */
  243. d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
  244. d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
  245. d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
  246. d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
  247. GFP_KERNEL);
  248. if (!d->it_prg) {
  249. PRINT(KERN_ERR, ohci->host->id,
  250. "Failed to allocate dma it prg");
  251. free_dma_iso_ctx(d);
  252. return NULL;
  253. }
  254. d->packet_size = packet_size;
  255. if (PAGE_SIZE % packet_size || packet_size>4096) {
  256. PRINT(KERN_ERR, ohci->host->id,
  257. "Packet size %d (page_size: %ld) "
  258. "not yet supported\n",
  259. packet_size, PAGE_SIZE);
  260. free_dma_iso_ctx(d);
  261. return NULL;
  262. }
  263. d->nb_cmd = d->frame_size / d->packet_size;
  264. if (d->frame_size % d->packet_size) {
  265. d->nb_cmd++;
  266. d->left_size = d->frame_size % d->packet_size;
  267. } else
  268. d->left_size = d->packet_size;
  269. for (i = 0; i < d->num_desc; i++) {
  270. if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
  271. sizeof(struct it_dma_prg), ohci->dev)) {
  272. PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
  273. free_dma_iso_ctx(d);
  274. return NULL;
  275. }
  276. d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
  277. }
  278. }
  279. d->buffer_status =
  280. kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
  281. d->buffer_prg_assignment =
  282. kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
  283. d->buffer_time =
  284. kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
  285. d->last_used_cmd =
  286. kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
  287. d->next_buffer =
  288. kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
  289. if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
  290. !d->last_used_cmd || !d->next_buffer) {
  291. PRINT(KERN_ERR, ohci->host->id,
  292. "Failed to allocate dma_iso_ctx member");
  293. free_dma_iso_ctx(d);
  294. return NULL;
  295. }
  296. spin_lock_init(&d->lock);
  297. PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
  298. "of size %d allocated for a frame size %d, each with %d prgs",
  299. (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
  300. d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
  301. return d;
  302. }
  303. static void reset_ir_status(struct dma_iso_ctx *d, int n)
  304. {
  305. int i;
  306. d->ir_prg[n][0].status = cpu_to_le32(4);
  307. d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
  308. for (i = 2; i < d->nb_cmd - 1; i++)
  309. d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
  310. d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
  311. }
  312. static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
  313. {
  314. struct dma_cmd *ir_prg = d->ir_prg[n];
  315. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  316. int i;
  317. d->buffer_prg_assignment[n] = buffer;
  318. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  319. (unsigned long)d->dma.kvirt));
  320. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  321. (buf + 4) - (unsigned long)d->dma.kvirt));
  322. for (i=2;i<d->nb_cmd-1;i++) {
  323. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  324. (buf+(i-1)*PAGE_SIZE) -
  325. (unsigned long)d->dma.kvirt));
  326. }
  327. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  328. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  329. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  330. (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
  331. }
  332. static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
  333. {
  334. struct dma_cmd *ir_prg = d->ir_prg[n];
  335. struct dma_prog_region *ir_reg = &d->prg_reg[n];
  336. unsigned long buf = (unsigned long)d->dma.kvirt;
  337. int i;
  338. /* the first descriptor will read only 4 bytes */
  339. ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  340. DMA_CTL_BRANCH | 4);
  341. /* set the sync flag */
  342. if (flags & VIDEO1394_SYNC_FRAMES)
  343. ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
  344. ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
  345. (unsigned long)d->dma.kvirt));
  346. ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  347. 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  348. /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
  349. if (d->nb_cmd > 2) {
  350. /* The second descriptor will read PAGE_SIZE-4 bytes */
  351. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  352. DMA_CTL_BRANCH | (PAGE_SIZE-4));
  353. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
  354. (unsigned long)d->dma.kvirt));
  355. ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  356. 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  357. for (i = 2; i < d->nb_cmd - 1; i++) {
  358. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  359. DMA_CTL_BRANCH | PAGE_SIZE);
  360. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  361. (buf+(i-1)*PAGE_SIZE) -
  362. (unsigned long)d->dma.kvirt));
  363. ir_prg[i].branchAddress =
  364. cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
  365. (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
  366. }
  367. /* The last descriptor will generate an interrupt */
  368. ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  369. DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
  370. ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  371. (buf+(i-1)*PAGE_SIZE) -
  372. (unsigned long)d->dma.kvirt));
  373. } else {
  374. /* Only one DMA page is used. Read d->left_size immediately and */
  375. /* generate an interrupt as this is also the last page. */
  376. ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
  377. DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
  378. ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  379. (buf + 4) - (unsigned long)d->dma.kvirt));
  380. }
  381. }
  382. static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
  383. {
  384. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  385. int i;
  386. d->flags = flags;
  387. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  388. for (i=0;i<d->num_desc;i++) {
  389. initialize_dma_ir_prg(d, i, flags);
  390. reset_ir_status(d, i);
  391. }
  392. /* reset the ctrl register */
  393. reg_write(ohci, d->ctrlClear, 0xf0000000);
  394. /* Set bufferFill */
  395. reg_write(ohci, d->ctrlSet, 0x80000000);
  396. /* Set isoch header */
  397. if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
  398. reg_write(ohci, d->ctrlSet, 0x40000000);
  399. /* Set the context match register to match on all tags,
  400. sync for sync tag, and listen to d->channel */
  401. reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
  402. /* Set up isoRecvIntMask to generate interrupts */
  403. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
  404. }
  405. /* find which context is listening to this channel */
  406. static struct dma_iso_ctx *
  407. find_ctx(struct list_head *list, int type, int channel)
  408. {
  409. struct dma_iso_ctx *ctx;
  410. list_for_each_entry(ctx, list, link) {
  411. if (ctx->type == type && ctx->channel == channel)
  412. return ctx;
  413. }
  414. return NULL;
  415. }
  416. static void wakeup_dma_ir_ctx(unsigned long l)
  417. {
  418. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  419. int i;
  420. spin_lock(&d->lock);
  421. for (i = 0; i < d->num_desc; i++) {
  422. if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
  423. reset_ir_status(d, i);
  424. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  425. do_gettimeofday(&d->buffer_time[i]);
  426. }
  427. }
  428. spin_unlock(&d->lock);
  429. if (waitqueue_active(&d->waitq))
  430. wake_up_interruptible(&d->waitq);
  431. }
  432. static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
  433. int n)
  434. {
  435. unsigned char* buf = d->dma.kvirt + n * d->buf_size;
  436. u32 cycleTimer;
  437. u32 timeStamp;
  438. if (n == -1) {
  439. return;
  440. }
  441. cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  442. timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
  443. timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
  444. + (cycleTimer & 0xf000)) & 0xffff;
  445. buf[6] = timeStamp >> 8;
  446. buf[7] = timeStamp & 0xff;
  447. /* if first packet is empty packet, then put timestamp into the next full one too */
  448. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  449. buf += d->packet_size;
  450. buf[6] = timeStamp >> 8;
  451. buf[7] = timeStamp & 0xff;
  452. }
  453. /* do the next buffer frame too in case of irq latency */
  454. n = d->next_buffer[n];
  455. if (n == -1) {
  456. return;
  457. }
  458. buf = d->dma.kvirt + n * d->buf_size;
  459. timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
  460. buf[6] = timeStamp >> 8;
  461. buf[7] = timeStamp & 0xff;
  462. /* if first packet is empty packet, then put timestamp into the next full one too */
  463. if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
  464. buf += d->packet_size;
  465. buf[6] = timeStamp >> 8;
  466. buf[7] = timeStamp & 0xff;
  467. }
  468. #if 0
  469. printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
  470. curr, n, cycleTimer, timeStamp);
  471. #endif
  472. }
  473. static void wakeup_dma_it_ctx(unsigned long l)
  474. {
  475. struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
  476. struct ti_ohci *ohci = d->ohci;
  477. int i;
  478. spin_lock(&d->lock);
  479. for (i = 0; i < d->num_desc; i++) {
  480. if (d->it_prg[i][d->last_used_cmd[i]].end.status &
  481. cpu_to_le32(0xFFFF0000)) {
  482. int next = d->next_buffer[i];
  483. put_timestamp(ohci, d, next);
  484. d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
  485. d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
  486. }
  487. }
  488. spin_unlock(&d->lock);
  489. if (waitqueue_active(&d->waitq))
  490. wake_up_interruptible(&d->waitq);
  491. }
  492. static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
  493. {
  494. struct it_dma_prg *it_prg = d->it_prg[n];
  495. unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
  496. int i;
  497. d->buffer_prg_assignment[n] = buffer;
  498. for (i=0;i<d->nb_cmd;i++) {
  499. it_prg[i].end.address =
  500. cpu_to_le32(dma_region_offset_to_bus(&d->dma,
  501. (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
  502. }
  503. }
  504. static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
  505. {
  506. struct it_dma_prg *it_prg = d->it_prg[n];
  507. struct dma_prog_region *it_reg = &d->prg_reg[n];
  508. unsigned long buf = (unsigned long)d->dma.kvirt;
  509. int i;
  510. d->last_used_cmd[n] = d->nb_cmd - 1;
  511. for (i=0;i<d->nb_cmd;i++) {
  512. it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
  513. DMA_CTL_IMMEDIATE | 8) ;
  514. it_prg[i].begin.address = 0;
  515. it_prg[i].begin.status = 0;
  516. it_prg[i].data[0] = cpu_to_le32(
  517. (IEEE1394_SPEED_100 << 16)
  518. | (/* tag */ 1 << 14)
  519. | (d->channel << 8)
  520. | (TCODE_ISO_DATA << 4));
  521. if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
  522. it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
  523. it_prg[i].data[2] = 0;
  524. it_prg[i].data[3] = 0;
  525. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
  526. DMA_CTL_BRANCH);
  527. it_prg[i].end.address =
  528. cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
  529. (unsigned long)d->dma.kvirt));
  530. if (i<d->nb_cmd-1) {
  531. it_prg[i].end.control |= cpu_to_le32(d->packet_size);
  532. it_prg[i].begin.branchAddress =
  533. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  534. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  535. it_prg[i].end.branchAddress =
  536. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  537. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  538. } else {
  539. /* the last prg generates an interrupt */
  540. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  541. DMA_CTL_IRQ | d->left_size);
  542. /* the last prg doesn't branch */
  543. it_prg[i].begin.branchAddress = 0;
  544. it_prg[i].end.branchAddress = 0;
  545. }
  546. it_prg[i].end.status = 0;
  547. }
  548. }
  549. static void initialize_dma_it_prg_var_packet_queue(
  550. struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
  551. struct ti_ohci *ohci)
  552. {
  553. struct it_dma_prg *it_prg = d->it_prg[n];
  554. struct dma_prog_region *it_reg = &d->prg_reg[n];
  555. int i;
  556. #if 0
  557. if (n != -1) {
  558. put_timestamp(ohci, d, n);
  559. }
  560. #endif
  561. d->last_used_cmd[n] = d->nb_cmd - 1;
  562. for (i = 0; i < d->nb_cmd; i++) {
  563. unsigned int size;
  564. if (packet_sizes[i] > d->packet_size) {
  565. size = d->packet_size;
  566. } else {
  567. size = packet_sizes[i];
  568. }
  569. it_prg[i].data[1] = cpu_to_le32(size << 16);
  570. it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
  571. if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
  572. it_prg[i].end.control |= cpu_to_le32(size);
  573. it_prg[i].begin.branchAddress =
  574. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  575. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  576. it_prg[i].end.branchAddress =
  577. cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
  578. sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
  579. } else {
  580. /* the last prg generates an interrupt */
  581. it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
  582. DMA_CTL_IRQ | size);
  583. /* the last prg doesn't branch */
  584. it_prg[i].begin.branchAddress = 0;
  585. it_prg[i].end.branchAddress = 0;
  586. d->last_used_cmd[n] = i;
  587. break;
  588. }
  589. }
  590. }
  591. static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
  592. unsigned int syt_offset, int flags)
  593. {
  594. struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
  595. int i;
  596. d->flags = flags;
  597. d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
  598. ohci1394_stop_context(ohci, d->ctrlClear, NULL);
  599. for (i=0;i<d->num_desc;i++)
  600. initialize_dma_it_prg(d, i, sync_tag);
  601. /* Set up isoRecvIntMask to generate interrupts */
  602. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
  603. }
  604. static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
  605. unsigned int buffer)
  606. {
  607. unsigned long flags;
  608. unsigned int ret;
  609. spin_lock_irqsave(&d->lock, flags);
  610. ret = d->buffer_status[buffer];
  611. spin_unlock_irqrestore(&d->lock, flags);
  612. return ret;
  613. }
  614. static int __video1394_ioctl(struct file *file,
  615. unsigned int cmd, unsigned long arg)
  616. {
  617. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  618. struct ti_ohci *ohci = ctx->ohci;
  619. unsigned long flags;
  620. void __user *argp = (void __user *)arg;
  621. switch(cmd)
  622. {
  623. case VIDEO1394_IOC_LISTEN_CHANNEL:
  624. case VIDEO1394_IOC_TALK_CHANNEL:
  625. {
  626. struct video1394_mmap v;
  627. u64 mask;
  628. struct dma_iso_ctx *d;
  629. int i;
  630. if (copy_from_user(&v, argp, sizeof(v)))
  631. return -EFAULT;
  632. /* if channel < 0, find lowest available one */
  633. if (v.channel < 0) {
  634. mask = (u64)0x1;
  635. for (i=0; ; i++) {
  636. if (i == ISO_CHANNELS) {
  637. PRINT(KERN_ERR, ohci->host->id,
  638. "No free channel found");
  639. return EAGAIN;
  640. }
  641. if (!(ohci->ISO_channel_usage & mask)) {
  642. v.channel = i;
  643. PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
  644. break;
  645. }
  646. mask = mask << 1;
  647. }
  648. } else if (v.channel >= ISO_CHANNELS) {
  649. PRINT(KERN_ERR, ohci->host->id,
  650. "Iso channel %d out of bounds", v.channel);
  651. return -EINVAL;
  652. } else {
  653. mask = (u64)0x1<<v.channel;
  654. }
  655. PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
  656. (u32)(mask>>32),(u32)(mask&0xffffffff),
  657. (u32)(ohci->ISO_channel_usage>>32),
  658. (u32)(ohci->ISO_channel_usage&0xffffffff));
  659. if (ohci->ISO_channel_usage & mask) {
  660. PRINT(KERN_ERR, ohci->host->id,
  661. "Channel %d is already taken", v.channel);
  662. return -EBUSY;
  663. }
  664. if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
  665. PRINT(KERN_ERR, ohci->host->id,
  666. "Invalid %d length buffer requested",v.buf_size);
  667. return -EINVAL;
  668. }
  669. if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
  670. PRINT(KERN_ERR, ohci->host->id,
  671. "Invalid %d buffers requested",v.nb_buffers);
  672. return -EINVAL;
  673. }
  674. if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
  675. PRINT(KERN_ERR, ohci->host->id,
  676. "%d buffers of size %d bytes is too big",
  677. v.nb_buffers, v.buf_size);
  678. return -EINVAL;
  679. }
  680. if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
  681. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
  682. v.nb_buffers + 1, v.buf_size,
  683. v.channel, 0);
  684. if (d == NULL) {
  685. PRINT(KERN_ERR, ohci->host->id,
  686. "Couldn't allocate ir context");
  687. return -EAGAIN;
  688. }
  689. initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
  690. ctx->current_ctx = d;
  691. v.buf_size = d->buf_size;
  692. list_add_tail(&d->link, &ctx->context_list);
  693. PRINT(KERN_INFO, ohci->host->id,
  694. "iso context %d listen on channel %d",
  695. d->ctx, v.channel);
  696. }
  697. else {
  698. d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
  699. v.nb_buffers + 1, v.buf_size,
  700. v.channel, v.packet_size);
  701. if (d == NULL) {
  702. PRINT(KERN_ERR, ohci->host->id,
  703. "Couldn't allocate it context");
  704. return -EAGAIN;
  705. }
  706. initialize_dma_it_ctx(d, v.sync_tag,
  707. v.syt_offset, v.flags);
  708. ctx->current_ctx = d;
  709. v.buf_size = d->buf_size;
  710. list_add_tail(&d->link, &ctx->context_list);
  711. PRINT(KERN_INFO, ohci->host->id,
  712. "Iso context %d talk on channel %d", d->ctx,
  713. v.channel);
  714. }
  715. if (copy_to_user(argp, &v, sizeof(v))) {
  716. /* FIXME : free allocated dma resources */
  717. return -EFAULT;
  718. }
  719. ohci->ISO_channel_usage |= mask;
  720. return 0;
  721. }
  722. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  723. case VIDEO1394_IOC_UNTALK_CHANNEL:
  724. {
  725. int channel;
  726. u64 mask;
  727. struct dma_iso_ctx *d;
  728. if (copy_from_user(&channel, argp, sizeof(int)))
  729. return -EFAULT;
  730. if (channel < 0 || channel >= ISO_CHANNELS) {
  731. PRINT(KERN_ERR, ohci->host->id,
  732. "Iso channel %d out of bound", channel);
  733. return -EINVAL;
  734. }
  735. mask = (u64)0x1<<channel;
  736. if (!(ohci->ISO_channel_usage & mask)) {
  737. PRINT(KERN_ERR, ohci->host->id,
  738. "Channel %d is not being used", channel);
  739. return -ESRCH;
  740. }
  741. /* Mark this channel as unused */
  742. ohci->ISO_channel_usage &= ~mask;
  743. if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
  744. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
  745. else
  746. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
  747. if (d == NULL) return -ESRCH;
  748. PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
  749. "stop talking on channel %d", d->ctx, channel);
  750. free_dma_iso_ctx(d);
  751. return 0;
  752. }
  753. case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
  754. {
  755. struct video1394_wait v;
  756. struct dma_iso_ctx *d;
  757. int next_prg;
  758. if (copy_from_user(&v, argp, sizeof(v)))
  759. return -EFAULT;
  760. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  761. if (d == NULL) return -EFAULT;
  762. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  763. PRINT(KERN_ERR, ohci->host->id,
  764. "Buffer %d out of range",v.buffer);
  765. return -EINVAL;
  766. }
  767. spin_lock_irqsave(&d->lock,flags);
  768. if (d->buffer_status[v.buffer]==VIDEO1394_BUFFER_QUEUED) {
  769. PRINT(KERN_ERR, ohci->host->id,
  770. "Buffer %d is already used",v.buffer);
  771. spin_unlock_irqrestore(&d->lock,flags);
  772. return -EBUSY;
  773. }
  774. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  775. next_prg = (d->last_buffer + 1) % d->num_desc;
  776. if (d->last_buffer>=0)
  777. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress =
  778. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0)
  779. & 0xfffffff0) | 0x1);
  780. d->last_buffer = next_prg;
  781. reprogram_dma_ir_prg(d, d->last_buffer, v.buffer, d->flags);
  782. d->ir_prg[d->last_buffer][d->nb_cmd-1].branchAddress = 0;
  783. spin_unlock_irqrestore(&d->lock,flags);
  784. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  785. {
  786. DBGMSG(ohci->host->id, "Starting iso DMA ctx=%d",d->ctx);
  787. /* Tell the controller where the first program is */
  788. reg_write(ohci, d->cmdPtr,
  789. dma_prog_region_offset_to_bus(&d->prg_reg[d->last_buffer], 0) | 0x1);
  790. /* Run IR context */
  791. reg_write(ohci, d->ctrlSet, 0x8000);
  792. }
  793. else {
  794. /* Wake up dma context if necessary */
  795. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  796. PRINT(KERN_INFO, ohci->host->id,
  797. "Waking up iso dma ctx=%d", d->ctx);
  798. reg_write(ohci, d->ctrlSet, 0x1000);
  799. }
  800. }
  801. return 0;
  802. }
  803. case VIDEO1394_IOC_LISTEN_WAIT_BUFFER:
  804. case VIDEO1394_IOC_LISTEN_POLL_BUFFER:
  805. {
  806. struct video1394_wait v;
  807. struct dma_iso_ctx *d;
  808. int i = 0;
  809. if (copy_from_user(&v, argp, sizeof(v)))
  810. return -EFAULT;
  811. d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
  812. if (d == NULL) return -EFAULT;
  813. if ((v.buffer<0) || (v.buffer>d->num_desc - 1)) {
  814. PRINT(KERN_ERR, ohci->host->id,
  815. "Buffer %d out of range",v.buffer);
  816. return -EINVAL;
  817. }
  818. /*
  819. * I change the way it works so that it returns
  820. * the last received frame.
  821. */
  822. spin_lock_irqsave(&d->lock, flags);
  823. switch(d->buffer_status[v.buffer]) {
  824. case VIDEO1394_BUFFER_READY:
  825. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  826. break;
  827. case VIDEO1394_BUFFER_QUEUED:
  828. if (cmd == VIDEO1394_IOC_LISTEN_POLL_BUFFER) {
  829. /* for polling, return error code EINTR */
  830. spin_unlock_irqrestore(&d->lock, flags);
  831. return -EINTR;
  832. }
  833. spin_unlock_irqrestore(&d->lock, flags);
  834. wait_event_interruptible(d->waitq,
  835. video1394_buffer_state(d, v.buffer) ==
  836. VIDEO1394_BUFFER_READY);
  837. if (signal_pending(current))
  838. return -EINTR;
  839. spin_lock_irqsave(&d->lock, flags);
  840. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  841. break;
  842. default:
  843. PRINT(KERN_ERR, ohci->host->id,
  844. "Buffer %d is not queued",v.buffer);
  845. spin_unlock_irqrestore(&d->lock, flags);
  846. return -ESRCH;
  847. }
  848. /* set time of buffer */
  849. v.filltime = d->buffer_time[v.buffer];
  850. // printk("Buffer %d time %d\n", v.buffer, (d->buffer_time[v.buffer]).tv_usec);
  851. /*
  852. * Look ahead to see how many more buffers have been received
  853. */
  854. i=0;
  855. while (d->buffer_status[(v.buffer+1)%(d->num_desc - 1)]==
  856. VIDEO1394_BUFFER_READY) {
  857. v.buffer=(v.buffer+1)%(d->num_desc - 1);
  858. i++;
  859. }
  860. spin_unlock_irqrestore(&d->lock, flags);
  861. v.buffer=i;
  862. if (copy_to_user(argp, &v, sizeof(v)))
  863. return -EFAULT;
  864. return 0;
  865. }
  866. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  867. {
  868. struct video1394_wait v;
  869. unsigned int *psizes = NULL;
  870. struct dma_iso_ctx *d;
  871. int next_prg;
  872. if (copy_from_user(&v, argp, sizeof(v)))
  873. return -EFAULT;
  874. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  875. if (d == NULL) return -EFAULT;
  876. if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
  877. PRINT(KERN_ERR, ohci->host->id,
  878. "Buffer %d out of range",v.buffer);
  879. return -EINVAL;
  880. }
  881. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  882. int buf_size = d->nb_cmd * sizeof(*psizes);
  883. struct video1394_queue_variable __user *p = argp;
  884. unsigned int __user *qv;
  885. if (get_user(qv, &p->packet_sizes))
  886. return -EFAULT;
  887. psizes = kmalloc(buf_size, GFP_KERNEL);
  888. if (!psizes)
  889. return -ENOMEM;
  890. if (copy_from_user(psizes, qv, buf_size)) {
  891. kfree(psizes);
  892. return -EFAULT;
  893. }
  894. }
  895. spin_lock_irqsave(&d->lock,flags);
  896. // last_buffer is last_prg
  897. next_prg = (d->last_buffer + 1) % d->num_desc;
  898. if (d->buffer_status[v.buffer]!=VIDEO1394_BUFFER_FREE) {
  899. PRINT(KERN_ERR, ohci->host->id,
  900. "Buffer %d is already used",v.buffer);
  901. spin_unlock_irqrestore(&d->lock,flags);
  902. kfree(psizes);
  903. return -EBUSY;
  904. }
  905. if (d->flags & VIDEO1394_VARIABLE_PACKET_SIZE) {
  906. initialize_dma_it_prg_var_packet_queue(
  907. d, next_prg, psizes, ohci);
  908. }
  909. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_QUEUED;
  910. if (d->last_buffer >= 0) {
  911. d->it_prg[d->last_buffer]
  912. [ d->last_used_cmd[d->last_buffer] ].end.branchAddress =
  913. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  914. 0) & 0xfffffff0) | 0x3);
  915. d->it_prg[d->last_buffer]
  916. [ d->last_used_cmd[d->last_buffer] ].begin.branchAddress =
  917. cpu_to_le32((dma_prog_region_offset_to_bus(&d->prg_reg[next_prg],
  918. 0) & 0xfffffff0) | 0x3);
  919. d->next_buffer[d->last_buffer] = (v.buffer + 1) % (d->num_desc - 1);
  920. }
  921. d->last_buffer = next_prg;
  922. reprogram_dma_it_prg(d, d->last_buffer, v.buffer);
  923. d->next_buffer[d->last_buffer] = -1;
  924. d->it_prg[d->last_buffer][d->last_used_cmd[d->last_buffer]].end.branchAddress = 0;
  925. spin_unlock_irqrestore(&d->lock,flags);
  926. if (!(reg_read(ohci, d->ctrlSet) & 0x8000))
  927. {
  928. DBGMSG(ohci->host->id, "Starting iso transmit DMA ctx=%d",
  929. d->ctx);
  930. put_timestamp(ohci, d, d->last_buffer);
  931. /* Tell the controller where the first program is */
  932. reg_write(ohci, d->cmdPtr,
  933. dma_prog_region_offset_to_bus(&d->prg_reg[next_prg], 0) | 0x3);
  934. /* Run IT context */
  935. reg_write(ohci, d->ctrlSet, 0x8000);
  936. }
  937. else {
  938. /* Wake up dma context if necessary */
  939. if (!(reg_read(ohci, d->ctrlSet) & 0x400)) {
  940. PRINT(KERN_INFO, ohci->host->id,
  941. "Waking up iso transmit dma ctx=%d",
  942. d->ctx);
  943. put_timestamp(ohci, d, d->last_buffer);
  944. reg_write(ohci, d->ctrlSet, 0x1000);
  945. }
  946. }
  947. kfree(psizes);
  948. return 0;
  949. }
  950. case VIDEO1394_IOC_TALK_WAIT_BUFFER:
  951. {
  952. struct video1394_wait v;
  953. struct dma_iso_ctx *d;
  954. if (copy_from_user(&v, argp, sizeof(v)))
  955. return -EFAULT;
  956. d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, v.channel);
  957. if (d == NULL) return -EFAULT;
  958. if ((v.buffer<0) || (v.buffer>=d->num_desc-1)) {
  959. PRINT(KERN_ERR, ohci->host->id,
  960. "Buffer %d out of range",v.buffer);
  961. return -EINVAL;
  962. }
  963. switch(d->buffer_status[v.buffer]) {
  964. case VIDEO1394_BUFFER_READY:
  965. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  966. return 0;
  967. case VIDEO1394_BUFFER_QUEUED:
  968. wait_event_interruptible(d->waitq,
  969. (d->buffer_status[v.buffer] == VIDEO1394_BUFFER_READY));
  970. if (signal_pending(current))
  971. return -EINTR;
  972. d->buffer_status[v.buffer]=VIDEO1394_BUFFER_FREE;
  973. return 0;
  974. default:
  975. PRINT(KERN_ERR, ohci->host->id,
  976. "Buffer %d is not queued",v.buffer);
  977. return -ESRCH;
  978. }
  979. }
  980. default:
  981. return -ENOTTY;
  982. }
  983. }
  984. static long video1394_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  985. {
  986. int err;
  987. lock_kernel();
  988. err = __video1394_ioctl(file, cmd, arg);
  989. unlock_kernel();
  990. return err;
  991. }
  992. /*
  993. * This maps the vmalloced and reserved buffer to user space.
  994. *
  995. * FIXME:
  996. * - PAGE_READONLY should suffice!?
  997. * - remap_pfn_range is kind of inefficient for page by page remapping.
  998. * But e.g. pte_alloc() does not work in modules ... :-(
  999. */
  1000. static int video1394_mmap(struct file *file, struct vm_area_struct *vma)
  1001. {
  1002. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1003. int res = -EINVAL;
  1004. lock_kernel();
  1005. if (ctx->current_ctx == NULL) {
  1006. PRINT(KERN_ERR, ctx->ohci->host->id, "Current iso context not set");
  1007. } else
  1008. res = dma_region_mmap(&ctx->current_ctx->dma, file, vma);
  1009. unlock_kernel();
  1010. return res;
  1011. }
  1012. static int video1394_open(struct inode *inode, struct file *file)
  1013. {
  1014. int i = ieee1394_file_to_instance(file);
  1015. struct ti_ohci *ohci;
  1016. struct file_ctx *ctx;
  1017. ohci = hpsb_get_hostinfo_bykey(&video1394_highlevel, i);
  1018. if (ohci == NULL)
  1019. return -EIO;
  1020. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1021. if (!ctx) {
  1022. PRINT(KERN_ERR, ohci->host->id, "Cannot malloc file_ctx");
  1023. return -ENOMEM;
  1024. }
  1025. ctx->ohci = ohci;
  1026. INIT_LIST_HEAD(&ctx->context_list);
  1027. ctx->current_ctx = NULL;
  1028. file->private_data = ctx;
  1029. return 0;
  1030. }
  1031. static int video1394_release(struct inode *inode, struct file *file)
  1032. {
  1033. struct file_ctx *ctx = (struct file_ctx *)file->private_data;
  1034. struct ti_ohci *ohci = ctx->ohci;
  1035. struct list_head *lh, *next;
  1036. u64 mask;
  1037. lock_kernel();
  1038. list_for_each_safe(lh, next, &ctx->context_list) {
  1039. struct dma_iso_ctx *d;
  1040. d = list_entry(lh, struct dma_iso_ctx, link);
  1041. mask = (u64) 1 << d->channel;
  1042. if (!(ohci->ISO_channel_usage & mask))
  1043. PRINT(KERN_ERR, ohci->host->id, "On release: Channel %d "
  1044. "is not being used", d->channel);
  1045. else
  1046. ohci->ISO_channel_usage &= ~mask;
  1047. PRINT(KERN_INFO, ohci->host->id, "On release: Iso %s context "
  1048. "%d stop listening on channel %d",
  1049. d->type == OHCI_ISO_RECEIVE ? "receive" : "transmit",
  1050. d->ctx, d->channel);
  1051. free_dma_iso_ctx(d);
  1052. }
  1053. kfree(ctx);
  1054. file->private_data = NULL;
  1055. unlock_kernel();
  1056. return 0;
  1057. }
  1058. #ifdef CONFIG_COMPAT
  1059. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg);
  1060. #endif
  1061. static struct cdev video1394_cdev;
  1062. static struct file_operations video1394_fops=
  1063. {
  1064. .owner = THIS_MODULE,
  1065. .unlocked_ioctl = video1394_ioctl,
  1066. #ifdef CONFIG_COMPAT
  1067. .compat_ioctl = video1394_compat_ioctl,
  1068. #endif
  1069. .mmap = video1394_mmap,
  1070. .open = video1394_open,
  1071. .release = video1394_release
  1072. };
  1073. /*** HOTPLUG STUFF **********************************************************/
  1074. /*
  1075. * Export information about protocols/devices supported by this driver.
  1076. */
  1077. static struct ieee1394_device_id video1394_id_table[] = {
  1078. {
  1079. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1080. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1081. .version = CAMERA_SW_VERSION_ENTRY & 0xffffff
  1082. },
  1083. {
  1084. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1085. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1086. .version = (CAMERA_SW_VERSION_ENTRY + 1) & 0xffffff
  1087. },
  1088. {
  1089. .match_flags = IEEE1394_MATCH_SPECIFIER_ID | IEEE1394_MATCH_VERSION,
  1090. .specifier_id = CAMERA_UNIT_SPEC_ID_ENTRY & 0xffffff,
  1091. .version = (CAMERA_SW_VERSION_ENTRY + 2) & 0xffffff
  1092. },
  1093. { }
  1094. };
  1095. MODULE_DEVICE_TABLE(ieee1394, video1394_id_table);
  1096. static struct hpsb_protocol_driver video1394_driver = {
  1097. .name = "1394 Digital Camera Driver",
  1098. .id_table = video1394_id_table,
  1099. .driver = {
  1100. .name = VIDEO1394_DRIVER_NAME,
  1101. .bus = &ieee1394_bus_type,
  1102. },
  1103. };
  1104. static void video1394_add_host (struct hpsb_host *host)
  1105. {
  1106. struct ti_ohci *ohci;
  1107. int minor;
  1108. /* We only work with the OHCI-1394 driver */
  1109. if (strcmp(host->driver->name, OHCI1394_DRIVER_NAME))
  1110. return;
  1111. ohci = (struct ti_ohci *)host->hostdata;
  1112. if (!hpsb_create_hostinfo(&video1394_highlevel, host, 0)) {
  1113. PRINT(KERN_ERR, ohci->host->id, "Cannot allocate hostinfo");
  1114. return;
  1115. }
  1116. hpsb_set_hostinfo(&video1394_highlevel, host, ohci);
  1117. hpsb_set_hostinfo_key(&video1394_highlevel, host, ohci->host->id);
  1118. minor = IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id;
  1119. class_device_create(hpsb_protocol_class, NULL, MKDEV(
  1120. IEEE1394_MAJOR, minor),
  1121. NULL, "%s-%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1122. devfs_mk_cdev(MKDEV(IEEE1394_MAJOR, minor),
  1123. S_IFCHR | S_IRUSR | S_IWUSR,
  1124. "%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1125. }
  1126. static void video1394_remove_host (struct hpsb_host *host)
  1127. {
  1128. struct ti_ohci *ohci = hpsb_get_hostinfo(&video1394_highlevel, host);
  1129. if (ohci) {
  1130. class_device_destroy(hpsb_protocol_class, MKDEV(IEEE1394_MAJOR,
  1131. IEEE1394_MINOR_BLOCK_VIDEO1394 * 16 + ohci->host->id));
  1132. devfs_remove("%s/%d", VIDEO1394_DRIVER_NAME, ohci->host->id);
  1133. }
  1134. return;
  1135. }
  1136. static struct hpsb_highlevel video1394_highlevel = {
  1137. .name = VIDEO1394_DRIVER_NAME,
  1138. .add_host = video1394_add_host,
  1139. .remove_host = video1394_remove_host,
  1140. };
  1141. MODULE_AUTHOR("Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>");
  1142. MODULE_DESCRIPTION("driver for digital video on OHCI board");
  1143. MODULE_SUPPORTED_DEVICE(VIDEO1394_DRIVER_NAME);
  1144. MODULE_LICENSE("GPL");
  1145. #ifdef CONFIG_COMPAT
  1146. #define VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER \
  1147. _IOW ('#', 0x12, struct video1394_wait32)
  1148. #define VIDEO1394_IOC32_LISTEN_WAIT_BUFFER \
  1149. _IOWR('#', 0x13, struct video1394_wait32)
  1150. #define VIDEO1394_IOC32_TALK_WAIT_BUFFER \
  1151. _IOW ('#', 0x17, struct video1394_wait32)
  1152. #define VIDEO1394_IOC32_LISTEN_POLL_BUFFER \
  1153. _IOWR('#', 0x18, struct video1394_wait32)
  1154. struct video1394_wait32 {
  1155. u32 channel;
  1156. u32 buffer;
  1157. struct compat_timeval filltime;
  1158. };
  1159. static int video1394_wr_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1160. {
  1161. struct video1394_wait32 __user *argp = (void __user *)arg;
  1162. struct video1394_wait32 wait32;
  1163. struct video1394_wait wait;
  1164. mm_segment_t old_fs;
  1165. int ret;
  1166. if (copy_from_user(&wait32, argp, sizeof(wait32)))
  1167. return -EFAULT;
  1168. wait.channel = wait32.channel;
  1169. wait.buffer = wait32.buffer;
  1170. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1171. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1172. old_fs = get_fs();
  1173. set_fs(KERNEL_DS);
  1174. if (cmd == VIDEO1394_IOC32_LISTEN_WAIT_BUFFER)
  1175. ret = video1394_ioctl(file,
  1176. VIDEO1394_IOC_LISTEN_WAIT_BUFFER,
  1177. (unsigned long) &wait);
  1178. else
  1179. ret = video1394_ioctl(file,
  1180. VIDEO1394_IOC_LISTEN_POLL_BUFFER,
  1181. (unsigned long) &wait);
  1182. set_fs(old_fs);
  1183. if (!ret) {
  1184. wait32.channel = wait.channel;
  1185. wait32.buffer = wait.buffer;
  1186. wait32.filltime.tv_sec = (int)wait.filltime.tv_sec;
  1187. wait32.filltime.tv_usec = (int)wait.filltime.tv_usec;
  1188. if (copy_to_user(argp, &wait32, sizeof(wait32)))
  1189. ret = -EFAULT;
  1190. }
  1191. return ret;
  1192. }
  1193. static int video1394_w_wait32(struct file *file, unsigned int cmd, unsigned long arg)
  1194. {
  1195. struct video1394_wait32 wait32;
  1196. struct video1394_wait wait;
  1197. mm_segment_t old_fs;
  1198. int ret;
  1199. if (copy_from_user(&wait32, (void __user *)arg, sizeof(wait32)))
  1200. return -EFAULT;
  1201. wait.channel = wait32.channel;
  1202. wait.buffer = wait32.buffer;
  1203. wait.filltime.tv_sec = (time_t)wait32.filltime.tv_sec;
  1204. wait.filltime.tv_usec = (suseconds_t)wait32.filltime.tv_usec;
  1205. old_fs = get_fs();
  1206. set_fs(KERNEL_DS);
  1207. if (cmd == VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER)
  1208. ret = video1394_ioctl(file,
  1209. VIDEO1394_IOC_LISTEN_QUEUE_BUFFER,
  1210. (unsigned long) &wait);
  1211. else
  1212. ret = video1394_ioctl(file,
  1213. VIDEO1394_IOC_TALK_WAIT_BUFFER,
  1214. (unsigned long) &wait);
  1215. set_fs(old_fs);
  1216. return ret;
  1217. }
  1218. static int video1394_queue_buf32(struct file *file, unsigned int cmd, unsigned long arg)
  1219. {
  1220. return -EFAULT; /* ??? was there before. */
  1221. return video1394_ioctl(file,
  1222. VIDEO1394_IOC_TALK_QUEUE_BUFFER, arg);
  1223. }
  1224. static long video1394_compat_ioctl(struct file *f, unsigned cmd, unsigned long arg)
  1225. {
  1226. switch (cmd) {
  1227. case VIDEO1394_IOC_LISTEN_CHANNEL:
  1228. case VIDEO1394_IOC_UNLISTEN_CHANNEL:
  1229. case VIDEO1394_IOC_TALK_CHANNEL:
  1230. case VIDEO1394_IOC_UNTALK_CHANNEL:
  1231. return video1394_ioctl(f, cmd, arg);
  1232. case VIDEO1394_IOC32_LISTEN_QUEUE_BUFFER:
  1233. return video1394_w_wait32(f, cmd, arg);
  1234. case VIDEO1394_IOC32_LISTEN_WAIT_BUFFER:
  1235. return video1394_wr_wait32(f, cmd, arg);
  1236. case VIDEO1394_IOC_TALK_QUEUE_BUFFER:
  1237. return video1394_queue_buf32(f, cmd, arg);
  1238. case VIDEO1394_IOC32_TALK_WAIT_BUFFER:
  1239. return video1394_w_wait32(f, cmd, arg);
  1240. case VIDEO1394_IOC32_LISTEN_POLL_BUFFER:
  1241. return video1394_wr_wait32(f, cmd, arg);
  1242. default:
  1243. return -ENOIOCTLCMD;
  1244. }
  1245. }
  1246. #endif /* CONFIG_COMPAT */
  1247. static void __exit video1394_exit_module (void)
  1248. {
  1249. hpsb_unregister_protocol(&video1394_driver);
  1250. hpsb_unregister_highlevel(&video1394_highlevel);
  1251. devfs_remove(VIDEO1394_DRIVER_NAME);
  1252. cdev_del(&video1394_cdev);
  1253. PRINT_G(KERN_INFO, "Removed " VIDEO1394_DRIVER_NAME " module");
  1254. }
  1255. static int __init video1394_init_module (void)
  1256. {
  1257. int ret;
  1258. cdev_init(&video1394_cdev, &video1394_fops);
  1259. video1394_cdev.owner = THIS_MODULE;
  1260. kobject_set_name(&video1394_cdev.kobj, VIDEO1394_DRIVER_NAME);
  1261. ret = cdev_add(&video1394_cdev, IEEE1394_VIDEO1394_DEV, 16);
  1262. if (ret) {
  1263. PRINT_G(KERN_ERR, "video1394: unable to get minor device block");
  1264. return ret;
  1265. }
  1266. devfs_mk_dir(VIDEO1394_DRIVER_NAME);
  1267. hpsb_register_highlevel(&video1394_highlevel);
  1268. ret = hpsb_register_protocol(&video1394_driver);
  1269. if (ret) {
  1270. PRINT_G(KERN_ERR, "video1394: failed to register protocol");
  1271. hpsb_unregister_highlevel(&video1394_highlevel);
  1272. devfs_remove(VIDEO1394_DRIVER_NAME);
  1273. cdev_del(&video1394_cdev);
  1274. return ret;
  1275. }
  1276. PRINT_G(KERN_INFO, "Installed " VIDEO1394_DRIVER_NAME " module");
  1277. return 0;
  1278. }
  1279. module_init(video1394_init_module);
  1280. module_exit(video1394_exit_module);