r8a66597-udc.c 40 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "r8a66597-udc.h"
  31. #define DRIVER_VERSION "2009-08-18"
  32. static const char udc_name[] = "r8a66597_udc";
  33. static const char *r8a66597_ep_name[] = {
  34. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  35. "ep8", "ep9",
  36. };
  37. static void disable_controller(struct r8a66597 *r8a66597);
  38. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  39. static void irq_packet_write(struct r8a66597_ep *ep,
  40. struct r8a66597_request *req);
  41. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  42. gfp_t gfp_flags);
  43. static void transfer_complete(struct r8a66597_ep *ep,
  44. struct r8a66597_request *req, int status);
  45. /*-------------------------------------------------------------------------*/
  46. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  47. {
  48. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  49. }
  50. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  51. unsigned long reg)
  52. {
  53. u16 tmp;
  54. tmp = r8a66597_read(r8a66597, INTENB0);
  55. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  56. INTENB0);
  57. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  58. r8a66597_write(r8a66597, tmp, INTENB0);
  59. }
  60. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  61. unsigned long reg)
  62. {
  63. u16 tmp;
  64. tmp = r8a66597_read(r8a66597, INTENB0);
  65. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  66. INTENB0);
  67. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  68. r8a66597_write(r8a66597, tmp, INTENB0);
  69. }
  70. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  71. {
  72. r8a66597_bset(r8a66597, CTRE, INTENB0);
  73. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  74. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  75. }
  76. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  77. __releases(r8a66597->lock)
  78. __acquires(r8a66597->lock)
  79. {
  80. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  81. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  82. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  83. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  84. spin_unlock(&r8a66597->lock);
  85. r8a66597->driver->disconnect(&r8a66597->gadget);
  86. spin_lock(&r8a66597->lock);
  87. disable_controller(r8a66597);
  88. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  89. }
  90. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  91. {
  92. u16 pid = 0;
  93. unsigned long offset;
  94. if (pipenum == 0)
  95. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  96. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  97. offset = get_pipectr_addr(pipenum);
  98. pid = r8a66597_read(r8a66597, offset) & PID;
  99. } else
  100. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  101. return pid;
  102. }
  103. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  104. u16 pid)
  105. {
  106. unsigned long offset;
  107. if (pipenum == 0)
  108. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  109. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  110. offset = get_pipectr_addr(pipenum);
  111. r8a66597_mdfy(r8a66597, pid, PID, offset);
  112. } else
  113. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  114. }
  115. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  116. {
  117. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  118. }
  119. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  120. {
  121. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  122. }
  123. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  124. {
  125. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  126. }
  127. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  128. {
  129. u16 ret = 0;
  130. unsigned long offset;
  131. if (pipenum == 0)
  132. ret = r8a66597_read(r8a66597, DCPCTR);
  133. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  134. offset = get_pipectr_addr(pipenum);
  135. ret = r8a66597_read(r8a66597, offset);
  136. } else
  137. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  138. return ret;
  139. }
  140. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  141. {
  142. unsigned long offset;
  143. pipe_stop(r8a66597, pipenum);
  144. if (pipenum == 0)
  145. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  146. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  147. offset = get_pipectr_addr(pipenum);
  148. r8a66597_bset(r8a66597, SQCLR, offset);
  149. } else
  150. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  151. }
  152. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  153. {
  154. u16 tmp;
  155. int size;
  156. if (pipenum == 0) {
  157. tmp = r8a66597_read(r8a66597, DCPCFG);
  158. if ((tmp & R8A66597_CNTMD) != 0)
  159. size = 256;
  160. else {
  161. tmp = r8a66597_read(r8a66597, DCPMAXP);
  162. size = tmp & MAXP;
  163. }
  164. } else {
  165. r8a66597_write(r8a66597, pipenum, PIPESEL);
  166. tmp = r8a66597_read(r8a66597, PIPECFG);
  167. if ((tmp & R8A66597_CNTMD) != 0) {
  168. tmp = r8a66597_read(r8a66597, PIPEBUF);
  169. size = ((tmp >> 10) + 1) * 64;
  170. } else {
  171. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  172. size = tmp & MXPS;
  173. }
  174. }
  175. return size;
  176. }
  177. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  178. {
  179. if (r8a66597->pdata->on_chip)
  180. return MBW_32;
  181. else
  182. return MBW_16;
  183. }
  184. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  185. {
  186. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  187. if (ep->use_dma)
  188. return;
  189. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  190. ndelay(450);
  191. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  192. }
  193. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  194. struct r8a66597_pipe_info *info)
  195. {
  196. u16 bufnum = 0, buf_bsize = 0;
  197. u16 pipecfg = 0;
  198. if (info->pipe == 0)
  199. return -EINVAL;
  200. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  201. if (info->dir_in)
  202. pipecfg |= R8A66597_DIR;
  203. pipecfg |= info->type;
  204. pipecfg |= info->epnum;
  205. switch (info->type) {
  206. case R8A66597_INT:
  207. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  208. buf_bsize = 0;
  209. break;
  210. case R8A66597_BULK:
  211. /* isochronous pipes may be used as bulk pipes */
  212. if (info->pipe > R8A66597_BASE_PIPENUM_BULK)
  213. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  214. else
  215. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  216. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  217. buf_bsize = 7;
  218. pipecfg |= R8A66597_DBLB;
  219. if (!info->dir_in)
  220. pipecfg |= R8A66597_SHTNAK;
  221. break;
  222. case R8A66597_ISO:
  223. bufnum = R8A66597_BASE_BUFNUM +
  224. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  225. buf_bsize = 7;
  226. break;
  227. }
  228. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  229. pr_err(KERN_ERR "r8a66597 pipe memory is insufficient\n");
  230. return -ENOMEM;
  231. }
  232. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  233. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  234. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  235. if (info->interval)
  236. info->interval--;
  237. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  238. return 0;
  239. }
  240. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  241. struct r8a66597_pipe_info *info)
  242. {
  243. if (info->pipe == 0)
  244. return;
  245. if (is_bulk_pipe(info->pipe))
  246. r8a66597->bulk--;
  247. else if (is_interrupt_pipe(info->pipe))
  248. r8a66597->interrupt--;
  249. else if (is_isoc_pipe(info->pipe)) {
  250. r8a66597->isochronous--;
  251. if (info->type == R8A66597_BULK)
  252. r8a66597->bulk--;
  253. } else
  254. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  255. info->pipe);
  256. }
  257. static void pipe_initialize(struct r8a66597_ep *ep)
  258. {
  259. struct r8a66597 *r8a66597 = ep->r8a66597;
  260. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  261. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  262. r8a66597_write(r8a66597, 0, ep->pipectr);
  263. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  264. if (ep->use_dma) {
  265. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  266. ndelay(450);
  267. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  268. }
  269. }
  270. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  271. struct r8a66597_ep *ep,
  272. const struct usb_endpoint_descriptor *desc,
  273. u16 pipenum, int dma)
  274. {
  275. ep->use_dma = 0;
  276. ep->fifoaddr = CFIFO;
  277. ep->fifosel = CFIFOSEL;
  278. ep->fifoctr = CFIFOCTR;
  279. ep->fifotrn = 0;
  280. ep->pipectr = get_pipectr_addr(pipenum);
  281. ep->pipenum = pipenum;
  282. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  283. r8a66597->pipenum2ep[pipenum] = ep;
  284. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  285. = ep;
  286. INIT_LIST_HEAD(&ep->queue);
  287. }
  288. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  289. {
  290. struct r8a66597 *r8a66597 = ep->r8a66597;
  291. u16 pipenum = ep->pipenum;
  292. if (pipenum == 0)
  293. return;
  294. if (ep->use_dma)
  295. r8a66597->num_dma--;
  296. ep->pipenum = 0;
  297. ep->busy = 0;
  298. ep->use_dma = 0;
  299. }
  300. static int alloc_pipe_config(struct r8a66597_ep *ep,
  301. const struct usb_endpoint_descriptor *desc)
  302. {
  303. struct r8a66597 *r8a66597 = ep->r8a66597;
  304. struct r8a66597_pipe_info info;
  305. int dma = 0;
  306. unsigned char *counter;
  307. int ret;
  308. ep->desc = desc;
  309. if (ep->pipenum) /* already allocated pipe */
  310. return 0;
  311. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  312. case USB_ENDPOINT_XFER_BULK:
  313. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  314. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  315. printk(KERN_ERR "bulk pipe is insufficient\n");
  316. return -ENODEV;
  317. } else {
  318. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  319. + r8a66597->isochronous;
  320. counter = &r8a66597->isochronous;
  321. }
  322. } else {
  323. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  324. counter = &r8a66597->bulk;
  325. }
  326. info.type = R8A66597_BULK;
  327. dma = 1;
  328. break;
  329. case USB_ENDPOINT_XFER_INT:
  330. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  331. printk(KERN_ERR "interrupt pipe is insufficient\n");
  332. return -ENODEV;
  333. }
  334. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  335. info.type = R8A66597_INT;
  336. counter = &r8a66597->interrupt;
  337. break;
  338. case USB_ENDPOINT_XFER_ISOC:
  339. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  340. printk(KERN_ERR "isochronous pipe is insufficient\n");
  341. return -ENODEV;
  342. }
  343. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  344. info.type = R8A66597_ISO;
  345. counter = &r8a66597->isochronous;
  346. break;
  347. default:
  348. printk(KERN_ERR "unexpect xfer type\n");
  349. return -EINVAL;
  350. }
  351. ep->type = info.type;
  352. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  353. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  354. info.interval = desc->bInterval;
  355. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  356. info.dir_in = 1;
  357. else
  358. info.dir_in = 0;
  359. ret = pipe_buffer_setting(r8a66597, &info);
  360. if (ret < 0) {
  361. printk(KERN_ERR "pipe_buffer_setting fail\n");
  362. return ret;
  363. }
  364. (*counter)++;
  365. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  366. r8a66597->bulk++;
  367. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  368. pipe_initialize(ep);
  369. return 0;
  370. }
  371. static int free_pipe_config(struct r8a66597_ep *ep)
  372. {
  373. struct r8a66597 *r8a66597 = ep->r8a66597;
  374. struct r8a66597_pipe_info info;
  375. info.pipe = ep->pipenum;
  376. info.type = ep->type;
  377. pipe_buffer_release(r8a66597, &info);
  378. r8a66597_ep_release(ep);
  379. return 0;
  380. }
  381. /*-------------------------------------------------------------------------*/
  382. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  383. {
  384. enable_irq_ready(r8a66597, pipenum);
  385. enable_irq_nrdy(r8a66597, pipenum);
  386. }
  387. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  388. {
  389. disable_irq_ready(r8a66597, pipenum);
  390. disable_irq_nrdy(r8a66597, pipenum);
  391. }
  392. /* if complete is true, gadget driver complete function is not call */
  393. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  394. {
  395. r8a66597->ep[0].internal_ccpl = ccpl;
  396. pipe_start(r8a66597, 0);
  397. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  398. }
  399. static void start_ep0_write(struct r8a66597_ep *ep,
  400. struct r8a66597_request *req)
  401. {
  402. struct r8a66597 *r8a66597 = ep->r8a66597;
  403. pipe_change(r8a66597, ep->pipenum);
  404. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  405. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  406. if (req->req.length == 0) {
  407. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  408. pipe_start(r8a66597, 0);
  409. transfer_complete(ep, req, 0);
  410. } else {
  411. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  412. irq_ep0_write(ep, req);
  413. }
  414. }
  415. static void start_packet_write(struct r8a66597_ep *ep,
  416. struct r8a66597_request *req)
  417. {
  418. struct r8a66597 *r8a66597 = ep->r8a66597;
  419. u16 tmp;
  420. pipe_change(r8a66597, ep->pipenum);
  421. disable_irq_empty(r8a66597, ep->pipenum);
  422. pipe_start(r8a66597, ep->pipenum);
  423. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  424. if (unlikely((tmp & FRDY) == 0))
  425. pipe_irq_enable(r8a66597, ep->pipenum);
  426. else
  427. irq_packet_write(ep, req);
  428. }
  429. static void start_packet_read(struct r8a66597_ep *ep,
  430. struct r8a66597_request *req)
  431. {
  432. struct r8a66597 *r8a66597 = ep->r8a66597;
  433. u16 pipenum = ep->pipenum;
  434. if (ep->pipenum == 0) {
  435. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  436. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  437. pipe_start(r8a66597, pipenum);
  438. pipe_irq_enable(r8a66597, pipenum);
  439. } else {
  440. if (ep->use_dma) {
  441. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  442. pipe_change(r8a66597, pipenum);
  443. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  444. r8a66597_write(r8a66597,
  445. (req->req.length + ep->ep.maxpacket - 1)
  446. / ep->ep.maxpacket,
  447. ep->fifotrn);
  448. }
  449. pipe_start(r8a66597, pipenum); /* trigger once */
  450. pipe_irq_enable(r8a66597, pipenum);
  451. }
  452. }
  453. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  454. {
  455. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  456. start_packet_write(ep, req);
  457. else
  458. start_packet_read(ep, req);
  459. }
  460. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  461. {
  462. u16 ctsq;
  463. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  464. switch (ctsq) {
  465. case CS_RDDS:
  466. start_ep0_write(ep, req);
  467. break;
  468. case CS_WRDS:
  469. start_packet_read(ep, req);
  470. break;
  471. case CS_WRND:
  472. control_end(ep->r8a66597, 0);
  473. break;
  474. default:
  475. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  476. break;
  477. }
  478. }
  479. static void init_controller(struct r8a66597 *r8a66597)
  480. {
  481. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  482. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  483. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  484. if (r8a66597->pdata->on_chip) {
  485. r8a66597_bset(r8a66597, 0x04, SYSCFG1);
  486. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  487. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  488. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  489. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  490. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  491. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  492. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  493. DMA0CFG);
  494. } else {
  495. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  496. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  497. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  498. XTAL, SYSCFG0);
  499. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  500. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  501. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  502. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  503. msleep(3);
  504. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  505. msleep(1);
  506. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  507. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  508. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  509. DMA0CFG);
  510. }
  511. }
  512. static void disable_controller(struct r8a66597 *r8a66597)
  513. {
  514. if (r8a66597->pdata->on_chip) {
  515. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  516. r8a66597_write(r8a66597, 0, INTENB0);
  517. r8a66597_write(r8a66597, 0, INTENB1);
  518. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  519. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  520. } else {
  521. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  522. udelay(1);
  523. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  524. udelay(1);
  525. udelay(1);
  526. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  527. }
  528. }
  529. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  530. {
  531. u16 tmp;
  532. if (!r8a66597->pdata->on_chip) {
  533. tmp = r8a66597_read(r8a66597, SYSCFG0);
  534. if (!(tmp & XCKE))
  535. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  536. }
  537. }
  538. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  539. {
  540. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  541. }
  542. /*-------------------------------------------------------------------------*/
  543. static void transfer_complete(struct r8a66597_ep *ep,
  544. struct r8a66597_request *req, int status)
  545. __releases(r8a66597->lock)
  546. __acquires(r8a66597->lock)
  547. {
  548. int restart = 0;
  549. if (unlikely(ep->pipenum == 0)) {
  550. if (ep->internal_ccpl) {
  551. ep->internal_ccpl = 0;
  552. return;
  553. }
  554. }
  555. list_del_init(&req->queue);
  556. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  557. req->req.status = -ESHUTDOWN;
  558. else
  559. req->req.status = status;
  560. if (!list_empty(&ep->queue))
  561. restart = 1;
  562. spin_unlock(&ep->r8a66597->lock);
  563. req->req.complete(&ep->ep, &req->req);
  564. spin_lock(&ep->r8a66597->lock);
  565. if (restart) {
  566. req = get_request_from_ep(ep);
  567. if (ep->desc)
  568. start_packet(ep, req);
  569. }
  570. }
  571. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  572. {
  573. int i;
  574. u16 tmp;
  575. unsigned bufsize;
  576. size_t size;
  577. void *buf;
  578. u16 pipenum = ep->pipenum;
  579. struct r8a66597 *r8a66597 = ep->r8a66597;
  580. pipe_change(r8a66597, pipenum);
  581. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  582. i = 0;
  583. do {
  584. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  585. if (i++ > 100000) {
  586. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  587. "conflict. please power off this controller.");
  588. return;
  589. }
  590. ndelay(1);
  591. } while ((tmp & FRDY) == 0);
  592. /* prepare parameters */
  593. bufsize = get_buffer_size(r8a66597, pipenum);
  594. buf = req->req.buf + req->req.actual;
  595. size = min(bufsize, req->req.length - req->req.actual);
  596. /* write fifo */
  597. if (req->req.buf) {
  598. if (size > 0)
  599. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  600. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  601. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  602. }
  603. /* update parameters */
  604. req->req.actual += size;
  605. /* check transfer finish */
  606. if ((!req->req.zero && (req->req.actual == req->req.length))
  607. || (size % ep->ep.maxpacket)
  608. || (size == 0)) {
  609. disable_irq_ready(r8a66597, pipenum);
  610. disable_irq_empty(r8a66597, pipenum);
  611. } else {
  612. disable_irq_ready(r8a66597, pipenum);
  613. enable_irq_empty(r8a66597, pipenum);
  614. }
  615. pipe_start(r8a66597, pipenum);
  616. }
  617. static void irq_packet_write(struct r8a66597_ep *ep,
  618. struct r8a66597_request *req)
  619. {
  620. u16 tmp;
  621. unsigned bufsize;
  622. size_t size;
  623. void *buf;
  624. u16 pipenum = ep->pipenum;
  625. struct r8a66597 *r8a66597 = ep->r8a66597;
  626. pipe_change(r8a66597, pipenum);
  627. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  628. if (unlikely((tmp & FRDY) == 0)) {
  629. pipe_stop(r8a66597, pipenum);
  630. pipe_irq_disable(r8a66597, pipenum);
  631. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  632. return;
  633. }
  634. /* prepare parameters */
  635. bufsize = get_buffer_size(r8a66597, pipenum);
  636. buf = req->req.buf + req->req.actual;
  637. size = min(bufsize, req->req.length - req->req.actual);
  638. /* write fifo */
  639. if (req->req.buf) {
  640. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  641. if ((size == 0)
  642. || ((size % ep->ep.maxpacket) != 0)
  643. || ((bufsize != ep->ep.maxpacket)
  644. && (bufsize > size)))
  645. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  646. }
  647. /* update parameters */
  648. req->req.actual += size;
  649. /* check transfer finish */
  650. if ((!req->req.zero && (req->req.actual == req->req.length))
  651. || (size % ep->ep.maxpacket)
  652. || (size == 0)) {
  653. disable_irq_ready(r8a66597, pipenum);
  654. enable_irq_empty(r8a66597, pipenum);
  655. } else {
  656. disable_irq_empty(r8a66597, pipenum);
  657. pipe_irq_enable(r8a66597, pipenum);
  658. }
  659. }
  660. static void irq_packet_read(struct r8a66597_ep *ep,
  661. struct r8a66597_request *req)
  662. {
  663. u16 tmp;
  664. int rcv_len, bufsize, req_len;
  665. int size;
  666. void *buf;
  667. u16 pipenum = ep->pipenum;
  668. struct r8a66597 *r8a66597 = ep->r8a66597;
  669. int finish = 0;
  670. pipe_change(r8a66597, pipenum);
  671. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  672. if (unlikely((tmp & FRDY) == 0)) {
  673. req->req.status = -EPIPE;
  674. pipe_stop(r8a66597, pipenum);
  675. pipe_irq_disable(r8a66597, pipenum);
  676. printk(KERN_ERR "read fifo not ready");
  677. return;
  678. }
  679. /* prepare parameters */
  680. rcv_len = tmp & DTLN;
  681. bufsize = get_buffer_size(r8a66597, pipenum);
  682. buf = req->req.buf + req->req.actual;
  683. req_len = req->req.length - req->req.actual;
  684. if (rcv_len < bufsize)
  685. size = min(rcv_len, req_len);
  686. else
  687. size = min(bufsize, req_len);
  688. /* update parameters */
  689. req->req.actual += size;
  690. /* check transfer finish */
  691. if ((!req->req.zero && (req->req.actual == req->req.length))
  692. || (size % ep->ep.maxpacket)
  693. || (size == 0)) {
  694. pipe_stop(r8a66597, pipenum);
  695. pipe_irq_disable(r8a66597, pipenum);
  696. finish = 1;
  697. }
  698. /* read fifo */
  699. if (req->req.buf) {
  700. if (size == 0)
  701. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  702. else
  703. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  704. }
  705. if ((ep->pipenum != 0) && finish)
  706. transfer_complete(ep, req, 0);
  707. }
  708. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  709. {
  710. u16 check;
  711. u16 pipenum;
  712. struct r8a66597_ep *ep;
  713. struct r8a66597_request *req;
  714. if ((status & BRDY0) && (enb & BRDY0)) {
  715. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  716. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  717. ep = &r8a66597->ep[0];
  718. req = get_request_from_ep(ep);
  719. irq_packet_read(ep, req);
  720. } else {
  721. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  722. check = 1 << pipenum;
  723. if ((status & check) && (enb & check)) {
  724. r8a66597_write(r8a66597, ~check, BRDYSTS);
  725. ep = r8a66597->pipenum2ep[pipenum];
  726. req = get_request_from_ep(ep);
  727. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  728. irq_packet_write(ep, req);
  729. else
  730. irq_packet_read(ep, req);
  731. }
  732. }
  733. }
  734. }
  735. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  736. {
  737. u16 tmp;
  738. u16 check;
  739. u16 pipenum;
  740. struct r8a66597_ep *ep;
  741. struct r8a66597_request *req;
  742. if ((status & BEMP0) && (enb & BEMP0)) {
  743. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  744. ep = &r8a66597->ep[0];
  745. req = get_request_from_ep(ep);
  746. irq_ep0_write(ep, req);
  747. } else {
  748. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  749. check = 1 << pipenum;
  750. if ((status & check) && (enb & check)) {
  751. r8a66597_write(r8a66597, ~check, BEMPSTS);
  752. tmp = control_reg_get(r8a66597, pipenum);
  753. if ((tmp & INBUFM) == 0) {
  754. disable_irq_empty(r8a66597, pipenum);
  755. pipe_irq_disable(r8a66597, pipenum);
  756. pipe_stop(r8a66597, pipenum);
  757. ep = r8a66597->pipenum2ep[pipenum];
  758. req = get_request_from_ep(ep);
  759. if (!list_empty(&ep->queue))
  760. transfer_complete(ep, req, 0);
  761. }
  762. }
  763. }
  764. }
  765. }
  766. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  767. __releases(r8a66597->lock)
  768. __acquires(r8a66597->lock)
  769. {
  770. struct r8a66597_ep *ep;
  771. u16 pid;
  772. u16 status = 0;
  773. u16 w_index = le16_to_cpu(ctrl->wIndex);
  774. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  775. case USB_RECIP_DEVICE:
  776. status = 1 << USB_DEVICE_SELF_POWERED;
  777. break;
  778. case USB_RECIP_INTERFACE:
  779. status = 0;
  780. break;
  781. case USB_RECIP_ENDPOINT:
  782. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  783. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  784. if (pid == PID_STALL)
  785. status = 1 << USB_ENDPOINT_HALT;
  786. else
  787. status = 0;
  788. break;
  789. default:
  790. pipe_stall(r8a66597, 0);
  791. return; /* exit */
  792. }
  793. r8a66597->ep0_data = cpu_to_le16(status);
  794. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  795. r8a66597->ep0_req->length = 2;
  796. /* AV: what happens if we get called again before that gets through? */
  797. spin_unlock(&r8a66597->lock);
  798. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  799. spin_lock(&r8a66597->lock);
  800. }
  801. static void clear_feature(struct r8a66597 *r8a66597,
  802. struct usb_ctrlrequest *ctrl)
  803. {
  804. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  805. case USB_RECIP_DEVICE:
  806. control_end(r8a66597, 1);
  807. break;
  808. case USB_RECIP_INTERFACE:
  809. control_end(r8a66597, 1);
  810. break;
  811. case USB_RECIP_ENDPOINT: {
  812. struct r8a66597_ep *ep;
  813. struct r8a66597_request *req;
  814. u16 w_index = le16_to_cpu(ctrl->wIndex);
  815. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  816. pipe_stop(r8a66597, ep->pipenum);
  817. control_reg_sqclr(r8a66597, ep->pipenum);
  818. control_end(r8a66597, 1);
  819. req = get_request_from_ep(ep);
  820. if (ep->busy) {
  821. ep->busy = 0;
  822. if (list_empty(&ep->queue))
  823. break;
  824. start_packet(ep, req);
  825. } else if (!list_empty(&ep->queue))
  826. pipe_start(r8a66597, ep->pipenum);
  827. }
  828. break;
  829. default:
  830. pipe_stall(r8a66597, 0);
  831. break;
  832. }
  833. }
  834. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  835. {
  836. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  837. case USB_RECIP_DEVICE:
  838. control_end(r8a66597, 1);
  839. break;
  840. case USB_RECIP_INTERFACE:
  841. control_end(r8a66597, 1);
  842. break;
  843. case USB_RECIP_ENDPOINT: {
  844. struct r8a66597_ep *ep;
  845. u16 w_index = le16_to_cpu(ctrl->wIndex);
  846. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  847. pipe_stall(r8a66597, ep->pipenum);
  848. control_end(r8a66597, 1);
  849. }
  850. break;
  851. default:
  852. pipe_stall(r8a66597, 0);
  853. break;
  854. }
  855. }
  856. /* if return value is true, call class driver's setup() */
  857. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  858. {
  859. u16 *p = (u16 *)ctrl;
  860. unsigned long offset = USBREQ;
  861. int i, ret = 0;
  862. /* read fifo */
  863. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  864. for (i = 0; i < 4; i++)
  865. p[i] = r8a66597_read(r8a66597, offset + i*2);
  866. /* check request */
  867. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  868. switch (ctrl->bRequest) {
  869. case USB_REQ_GET_STATUS:
  870. get_status(r8a66597, ctrl);
  871. break;
  872. case USB_REQ_CLEAR_FEATURE:
  873. clear_feature(r8a66597, ctrl);
  874. break;
  875. case USB_REQ_SET_FEATURE:
  876. set_feature(r8a66597, ctrl);
  877. break;
  878. default:
  879. ret = 1;
  880. break;
  881. }
  882. } else
  883. ret = 1;
  884. return ret;
  885. }
  886. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  887. {
  888. u16 speed = get_usb_speed(r8a66597);
  889. switch (speed) {
  890. case HSMODE:
  891. r8a66597->gadget.speed = USB_SPEED_HIGH;
  892. break;
  893. case FSMODE:
  894. r8a66597->gadget.speed = USB_SPEED_FULL;
  895. break;
  896. default:
  897. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  898. printk(KERN_ERR "USB speed unknown\n");
  899. }
  900. }
  901. static void irq_device_state(struct r8a66597 *r8a66597)
  902. {
  903. u16 dvsq;
  904. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  905. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  906. if (dvsq == DS_DFLT) {
  907. /* bus reset */
  908. r8a66597->driver->disconnect(&r8a66597->gadget);
  909. r8a66597_update_usb_speed(r8a66597);
  910. }
  911. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  912. r8a66597_update_usb_speed(r8a66597);
  913. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  914. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  915. r8a66597_update_usb_speed(r8a66597);
  916. r8a66597->old_dvsq = dvsq;
  917. }
  918. static void irq_control_stage(struct r8a66597 *r8a66597)
  919. __releases(r8a66597->lock)
  920. __acquires(r8a66597->lock)
  921. {
  922. struct usb_ctrlrequest ctrl;
  923. u16 ctsq;
  924. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  925. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  926. switch (ctsq) {
  927. case CS_IDST: {
  928. struct r8a66597_ep *ep;
  929. struct r8a66597_request *req;
  930. ep = &r8a66597->ep[0];
  931. req = get_request_from_ep(ep);
  932. transfer_complete(ep, req, 0);
  933. }
  934. break;
  935. case CS_RDDS:
  936. case CS_WRDS:
  937. case CS_WRND:
  938. if (setup_packet(r8a66597, &ctrl)) {
  939. spin_unlock(&r8a66597->lock);
  940. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  941. < 0)
  942. pipe_stall(r8a66597, 0);
  943. spin_lock(&r8a66597->lock);
  944. }
  945. break;
  946. case CS_RDSS:
  947. case CS_WRSS:
  948. control_end(r8a66597, 0);
  949. break;
  950. default:
  951. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  952. break;
  953. }
  954. }
  955. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  956. {
  957. struct r8a66597 *r8a66597 = _r8a66597;
  958. u16 intsts0;
  959. u16 intenb0;
  960. u16 brdysts, nrdysts, bempsts;
  961. u16 brdyenb, nrdyenb, bempenb;
  962. u16 savepipe;
  963. u16 mask0;
  964. spin_lock(&r8a66597->lock);
  965. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  966. intenb0 = r8a66597_read(r8a66597, INTENB0);
  967. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  968. mask0 = intsts0 & intenb0;
  969. if (mask0) {
  970. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  971. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  972. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  973. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  974. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  975. bempenb = r8a66597_read(r8a66597, BEMPENB);
  976. if (mask0 & VBINT) {
  977. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  978. INTSTS0);
  979. r8a66597_start_xclock(r8a66597);
  980. /* start vbus sampling */
  981. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  982. & VBSTS;
  983. r8a66597->scount = R8A66597_MAX_SAMPLING;
  984. mod_timer(&r8a66597->timer,
  985. jiffies + msecs_to_jiffies(50));
  986. }
  987. if (intsts0 & DVSQ)
  988. irq_device_state(r8a66597);
  989. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  990. && (brdysts & brdyenb))
  991. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  992. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  993. && (bempsts & bempenb))
  994. irq_pipe_empty(r8a66597, bempsts, bempenb);
  995. if (intsts0 & CTRT)
  996. irq_control_stage(r8a66597);
  997. }
  998. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  999. spin_unlock(&r8a66597->lock);
  1000. return IRQ_HANDLED;
  1001. }
  1002. static void r8a66597_timer(unsigned long _r8a66597)
  1003. {
  1004. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1005. unsigned long flags;
  1006. u16 tmp;
  1007. spin_lock_irqsave(&r8a66597->lock, flags);
  1008. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1009. if (r8a66597->scount > 0) {
  1010. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1011. if (tmp == r8a66597->old_vbus) {
  1012. r8a66597->scount--;
  1013. if (r8a66597->scount == 0) {
  1014. if (tmp == VBSTS)
  1015. r8a66597_usb_connect(r8a66597);
  1016. else
  1017. r8a66597_usb_disconnect(r8a66597);
  1018. } else {
  1019. mod_timer(&r8a66597->timer,
  1020. jiffies + msecs_to_jiffies(50));
  1021. }
  1022. } else {
  1023. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1024. r8a66597->old_vbus = tmp;
  1025. mod_timer(&r8a66597->timer,
  1026. jiffies + msecs_to_jiffies(50));
  1027. }
  1028. }
  1029. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1030. }
  1031. /*-------------------------------------------------------------------------*/
  1032. static int r8a66597_enable(struct usb_ep *_ep,
  1033. const struct usb_endpoint_descriptor *desc)
  1034. {
  1035. struct r8a66597_ep *ep;
  1036. ep = container_of(_ep, struct r8a66597_ep, ep);
  1037. return alloc_pipe_config(ep, desc);
  1038. }
  1039. static int r8a66597_disable(struct usb_ep *_ep)
  1040. {
  1041. struct r8a66597_ep *ep;
  1042. struct r8a66597_request *req;
  1043. unsigned long flags;
  1044. ep = container_of(_ep, struct r8a66597_ep, ep);
  1045. BUG_ON(!ep);
  1046. while (!list_empty(&ep->queue)) {
  1047. req = get_request_from_ep(ep);
  1048. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1049. transfer_complete(ep, req, -ECONNRESET);
  1050. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1051. }
  1052. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1053. return free_pipe_config(ep);
  1054. }
  1055. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1056. gfp_t gfp_flags)
  1057. {
  1058. struct r8a66597_request *req;
  1059. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1060. if (!req)
  1061. return NULL;
  1062. INIT_LIST_HEAD(&req->queue);
  1063. return &req->req;
  1064. }
  1065. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1066. {
  1067. struct r8a66597_request *req;
  1068. req = container_of(_req, struct r8a66597_request, req);
  1069. kfree(req);
  1070. }
  1071. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1072. gfp_t gfp_flags)
  1073. {
  1074. struct r8a66597_ep *ep;
  1075. struct r8a66597_request *req;
  1076. unsigned long flags;
  1077. int request = 0;
  1078. ep = container_of(_ep, struct r8a66597_ep, ep);
  1079. req = container_of(_req, struct r8a66597_request, req);
  1080. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1081. return -ESHUTDOWN;
  1082. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1083. if (list_empty(&ep->queue))
  1084. request = 1;
  1085. list_add_tail(&req->queue, &ep->queue);
  1086. req->req.actual = 0;
  1087. req->req.status = -EINPROGRESS;
  1088. if (ep->desc == NULL) /* control */
  1089. start_ep0(ep, req);
  1090. else {
  1091. if (request && !ep->busy)
  1092. start_packet(ep, req);
  1093. }
  1094. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1095. return 0;
  1096. }
  1097. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1098. {
  1099. struct r8a66597_ep *ep;
  1100. struct r8a66597_request *req;
  1101. unsigned long flags;
  1102. ep = container_of(_ep, struct r8a66597_ep, ep);
  1103. req = container_of(_req, struct r8a66597_request, req);
  1104. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1105. if (!list_empty(&ep->queue))
  1106. transfer_complete(ep, req, -ECONNRESET);
  1107. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1108. return 0;
  1109. }
  1110. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1111. {
  1112. struct r8a66597_ep *ep;
  1113. struct r8a66597_request *req;
  1114. unsigned long flags;
  1115. int ret = 0;
  1116. ep = container_of(_ep, struct r8a66597_ep, ep);
  1117. req = get_request_from_ep(ep);
  1118. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1119. if (!list_empty(&ep->queue)) {
  1120. ret = -EAGAIN;
  1121. goto out;
  1122. }
  1123. if (value) {
  1124. ep->busy = 1;
  1125. pipe_stall(ep->r8a66597, ep->pipenum);
  1126. } else {
  1127. ep->busy = 0;
  1128. pipe_stop(ep->r8a66597, ep->pipenum);
  1129. }
  1130. out:
  1131. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1132. return ret;
  1133. }
  1134. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1135. {
  1136. struct r8a66597_ep *ep;
  1137. unsigned long flags;
  1138. ep = container_of(_ep, struct r8a66597_ep, ep);
  1139. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1140. if (list_empty(&ep->queue) && !ep->busy) {
  1141. pipe_stop(ep->r8a66597, ep->pipenum);
  1142. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1143. }
  1144. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1145. }
  1146. static struct usb_ep_ops r8a66597_ep_ops = {
  1147. .enable = r8a66597_enable,
  1148. .disable = r8a66597_disable,
  1149. .alloc_request = r8a66597_alloc_request,
  1150. .free_request = r8a66597_free_request,
  1151. .queue = r8a66597_queue,
  1152. .dequeue = r8a66597_dequeue,
  1153. .set_halt = r8a66597_set_halt,
  1154. .fifo_flush = r8a66597_fifo_flush,
  1155. };
  1156. /*-------------------------------------------------------------------------*/
  1157. static struct r8a66597 *the_controller;
  1158. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1159. {
  1160. struct r8a66597 *r8a66597 = the_controller;
  1161. int retval;
  1162. if (!driver
  1163. || driver->speed != USB_SPEED_HIGH
  1164. || !driver->bind
  1165. || !driver->setup)
  1166. return -EINVAL;
  1167. if (!r8a66597)
  1168. return -ENODEV;
  1169. if (r8a66597->driver)
  1170. return -EBUSY;
  1171. /* hook up the driver */
  1172. driver->driver.bus = NULL;
  1173. r8a66597->driver = driver;
  1174. r8a66597->gadget.dev.driver = &driver->driver;
  1175. retval = device_add(&r8a66597->gadget.dev);
  1176. if (retval) {
  1177. printk(KERN_ERR "device_add error (%d)\n", retval);
  1178. goto error;
  1179. }
  1180. retval = driver->bind(&r8a66597->gadget);
  1181. if (retval) {
  1182. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1183. device_del(&r8a66597->gadget.dev);
  1184. goto error;
  1185. }
  1186. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1187. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1188. r8a66597_start_xclock(r8a66597);
  1189. /* start vbus sampling */
  1190. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1191. INTSTS0) & VBSTS;
  1192. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1193. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1194. }
  1195. return 0;
  1196. error:
  1197. r8a66597->driver = NULL;
  1198. r8a66597->gadget.dev.driver = NULL;
  1199. return retval;
  1200. }
  1201. EXPORT_SYMBOL(usb_gadget_register_driver);
  1202. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1203. {
  1204. struct r8a66597 *r8a66597 = the_controller;
  1205. unsigned long flags;
  1206. if (driver != r8a66597->driver || !driver->unbind)
  1207. return -EINVAL;
  1208. spin_lock_irqsave(&r8a66597->lock, flags);
  1209. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1210. r8a66597_usb_disconnect(r8a66597);
  1211. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1212. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1213. driver->unbind(&r8a66597->gadget);
  1214. init_controller(r8a66597);
  1215. disable_controller(r8a66597);
  1216. device_del(&r8a66597->gadget.dev);
  1217. r8a66597->driver = NULL;
  1218. return 0;
  1219. }
  1220. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1221. /*-------------------------------------------------------------------------*/
  1222. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1223. {
  1224. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1225. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1226. }
  1227. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1228. .get_frame = r8a66597_get_frame,
  1229. };
  1230. static int __exit r8a66597_remove(struct platform_device *pdev)
  1231. {
  1232. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1233. del_timer_sync(&r8a66597->timer);
  1234. iounmap((void *)r8a66597->reg);
  1235. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1236. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1237. #ifdef CONFIG_HAVE_CLK
  1238. if (r8a66597->pdata->on_chip) {
  1239. clk_disable(r8a66597->clk);
  1240. clk_put(r8a66597->clk);
  1241. }
  1242. #endif
  1243. kfree(r8a66597);
  1244. return 0;
  1245. }
  1246. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1247. {
  1248. }
  1249. static int __init r8a66597_probe(struct platform_device *pdev)
  1250. {
  1251. #ifdef CONFIG_HAVE_CLK
  1252. char clk_name[8];
  1253. #endif
  1254. struct resource *res, *ires;
  1255. int irq;
  1256. void __iomem *reg = NULL;
  1257. struct r8a66597 *r8a66597 = NULL;
  1258. int ret = 0;
  1259. int i;
  1260. unsigned long irq_trigger;
  1261. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1262. if (!res) {
  1263. ret = -ENODEV;
  1264. printk(KERN_ERR "platform_get_resource error.\n");
  1265. goto clean_up;
  1266. }
  1267. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1268. irq = ires->start;
  1269. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1270. if (irq < 0) {
  1271. ret = -ENODEV;
  1272. printk(KERN_ERR "platform_get_irq error.\n");
  1273. goto clean_up;
  1274. }
  1275. reg = ioremap(res->start, resource_size(res));
  1276. if (reg == NULL) {
  1277. ret = -ENOMEM;
  1278. printk(KERN_ERR "ioremap error.\n");
  1279. goto clean_up;
  1280. }
  1281. /* initialize ucd */
  1282. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1283. if (r8a66597 == NULL) {
  1284. printk(KERN_ERR "kzalloc error\n");
  1285. goto clean_up;
  1286. }
  1287. spin_lock_init(&r8a66597->lock);
  1288. dev_set_drvdata(&pdev->dev, r8a66597);
  1289. r8a66597->pdata = pdev->dev.platform_data;
  1290. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1291. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1292. device_initialize(&r8a66597->gadget.dev);
  1293. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1294. r8a66597->gadget.is_dualspeed = 1;
  1295. r8a66597->gadget.dev.parent = &pdev->dev;
  1296. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1297. r8a66597->gadget.dev.release = pdev->dev.release;
  1298. r8a66597->gadget.name = udc_name;
  1299. init_timer(&r8a66597->timer);
  1300. r8a66597->timer.function = r8a66597_timer;
  1301. r8a66597->timer.data = (unsigned long)r8a66597;
  1302. r8a66597->reg = (unsigned long)reg;
  1303. #ifdef CONFIG_HAVE_CLK
  1304. if (r8a66597->pdata->on_chip) {
  1305. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1306. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1307. if (IS_ERR(r8a66597->clk)) {
  1308. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1309. clk_name);
  1310. ret = PTR_ERR(r8a66597->clk);
  1311. goto clean_up;
  1312. }
  1313. clk_enable(r8a66597->clk);
  1314. }
  1315. #endif
  1316. disable_controller(r8a66597); /* make sure controller is disabled */
  1317. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1318. udc_name, r8a66597);
  1319. if (ret < 0) {
  1320. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1321. goto clean_up2;
  1322. }
  1323. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1324. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1325. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1326. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1327. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1328. if (i != 0) {
  1329. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1330. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1331. &r8a66597->gadget.ep_list);
  1332. }
  1333. ep->r8a66597 = r8a66597;
  1334. INIT_LIST_HEAD(&ep->queue);
  1335. ep->ep.name = r8a66597_ep_name[i];
  1336. ep->ep.ops = &r8a66597_ep_ops;
  1337. ep->ep.maxpacket = 512;
  1338. }
  1339. r8a66597->ep[0].ep.maxpacket = 64;
  1340. r8a66597->ep[0].pipenum = 0;
  1341. r8a66597->ep[0].fifoaddr = CFIFO;
  1342. r8a66597->ep[0].fifosel = CFIFOSEL;
  1343. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1344. r8a66597->ep[0].fifotrn = 0;
  1345. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1346. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1347. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1348. the_controller = r8a66597;
  1349. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1350. GFP_KERNEL);
  1351. if (r8a66597->ep0_req == NULL)
  1352. goto clean_up3;
  1353. r8a66597->ep0_req->complete = nop_completion;
  1354. init_controller(r8a66597);
  1355. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1356. return 0;
  1357. clean_up3:
  1358. free_irq(irq, r8a66597);
  1359. clean_up2:
  1360. #ifdef CONFIG_HAVE_CLK
  1361. if (r8a66597->pdata->on_chip) {
  1362. clk_disable(r8a66597->clk);
  1363. clk_put(r8a66597->clk);
  1364. }
  1365. #endif
  1366. clean_up:
  1367. if (r8a66597) {
  1368. if (r8a66597->ep0_req)
  1369. r8a66597_free_request(&r8a66597->ep[0].ep,
  1370. r8a66597->ep0_req);
  1371. kfree(r8a66597);
  1372. }
  1373. if (reg)
  1374. iounmap(reg);
  1375. return ret;
  1376. }
  1377. /*-------------------------------------------------------------------------*/
  1378. static struct platform_driver r8a66597_driver = {
  1379. .remove = __exit_p(r8a66597_remove),
  1380. .driver = {
  1381. .name = (char *) udc_name,
  1382. },
  1383. };
  1384. static int __init r8a66597_udc_init(void)
  1385. {
  1386. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1387. }
  1388. module_init(r8a66597_udc_init);
  1389. static void __exit r8a66597_udc_cleanup(void)
  1390. {
  1391. platform_driver_unregister(&r8a66597_driver);
  1392. }
  1393. module_exit(r8a66597_udc_cleanup);
  1394. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1395. MODULE_LICENSE("GPL");
  1396. MODULE_AUTHOR("Yoshihiro Shimoda");