aaci.c 27 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/amba/bus.h>
  21. #include <linux/io.h>
  22. #include <sound/core.h>
  23. #include <sound/initval.h>
  24. #include <sound/ac97_codec.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include "aaci.h"
  28. #include "devdma.h"
  29. #define DRIVER_NAME "aaci-pl041"
  30. /*
  31. * PM support is not complete. Turn it off.
  32. */
  33. #undef CONFIG_PM
  34. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  35. {
  36. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  37. /*
  38. * Ensure that the slot 1/2 RX registers are empty.
  39. */
  40. v = readl(aaci->base + AACI_SLFR);
  41. if (v & SLFR_2RXV)
  42. readl(aaci->base + AACI_SL2RX);
  43. if (v & SLFR_1RXV)
  44. readl(aaci->base + AACI_SL1RX);
  45. writel(maincr, aaci->base + AACI_MAINCR);
  46. }
  47. /*
  48. * P29:
  49. * The recommended use of programming the external codec through slot 1
  50. * and slot 2 data is to use the channels during setup routines and the
  51. * slot register at any other time. The data written into slot 1, slot 2
  52. * and slot 12 registers is transmitted only when their corresponding
  53. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  54. * register.
  55. */
  56. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  57. unsigned short val)
  58. {
  59. struct aaci *aaci = ac97->private_data;
  60. u32 v;
  61. int timeout = 5000;
  62. if (ac97->num >= 4)
  63. return;
  64. mutex_lock(&aaci->ac97_sem);
  65. aaci_ac97_select_codec(aaci, ac97);
  66. /*
  67. * P54: You must ensure that AACI_SL2TX is always written
  68. * to, if required, before data is written to AACI_SL1TX.
  69. */
  70. writel(val << 4, aaci->base + AACI_SL2TX);
  71. writel(reg << 12, aaci->base + AACI_SL1TX);
  72. /*
  73. * Wait for the transmission of both slots to complete.
  74. */
  75. do {
  76. v = readl(aaci->base + AACI_SLFR);
  77. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
  78. if (!timeout)
  79. dev_err(&aaci->dev->dev,
  80. "timeout waiting for write to complete\n");
  81. mutex_unlock(&aaci->ac97_sem);
  82. }
  83. /*
  84. * Read an AC'97 register.
  85. */
  86. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  87. {
  88. struct aaci *aaci = ac97->private_data;
  89. u32 v;
  90. int timeout = 5000;
  91. int retries = 10;
  92. if (ac97->num >= 4)
  93. return ~0;
  94. mutex_lock(&aaci->ac97_sem);
  95. aaci_ac97_select_codec(aaci, ac97);
  96. /*
  97. * Write the register address to slot 1.
  98. */
  99. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  100. /*
  101. * Wait for the transmission to complete.
  102. */
  103. do {
  104. v = readl(aaci->base + AACI_SLFR);
  105. } while ((v & SLFR_1TXB) && --timeout);
  106. if (!timeout) {
  107. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  108. v = ~0;
  109. goto out;
  110. }
  111. /*
  112. * Give the AC'97 codec more than enough time
  113. * to respond. (42us = ~2 frames at 48kHz.)
  114. */
  115. udelay(42);
  116. /*
  117. * Wait for slot 2 to indicate data.
  118. */
  119. timeout = 5000;
  120. do {
  121. cond_resched();
  122. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  123. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
  124. if (!timeout) {
  125. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  126. v = ~0;
  127. goto out;
  128. }
  129. do {
  130. v = readl(aaci->base + AACI_SL1RX) >> 12;
  131. if (v == reg) {
  132. v = readl(aaci->base + AACI_SL2RX) >> 4;
  133. break;
  134. } else if (--retries) {
  135. dev_warn(&aaci->dev->dev,
  136. "ac97 read back fail. retry\n");
  137. continue;
  138. } else {
  139. dev_warn(&aaci->dev->dev,
  140. "wrong ac97 register read back (%x != %x)\n",
  141. v, reg);
  142. v = ~0;
  143. }
  144. } while (retries);
  145. out:
  146. mutex_unlock(&aaci->ac97_sem);
  147. return v;
  148. }
  149. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  150. {
  151. u32 val;
  152. int timeout = 5000;
  153. do {
  154. val = readl(aacirun->base + AACI_SR);
  155. } while (val & (SR_TXB|SR_RXB) && timeout--);
  156. }
  157. /*
  158. * Interrupt support.
  159. */
  160. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  161. {
  162. if (mask & ISR_ORINTR) {
  163. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  164. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  165. }
  166. if (mask & ISR_RXTOINTR) {
  167. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  168. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  169. }
  170. if (mask & ISR_RXINTR) {
  171. struct aaci_runtime *aacirun = &aaci->capture;
  172. void *ptr;
  173. if (!aacirun->substream || !aacirun->start) {
  174. dev_warn(&aaci->dev->dev, "RX interrupt???\n");
  175. writel(0, aacirun->base + AACI_IE);
  176. return;
  177. }
  178. ptr = aacirun->ptr;
  179. do {
  180. unsigned int len = aacirun->fifosz;
  181. u32 val;
  182. if (aacirun->bytes <= 0) {
  183. aacirun->bytes += aacirun->period;
  184. aacirun->ptr = ptr;
  185. spin_unlock(&aaci->lock);
  186. snd_pcm_period_elapsed(aacirun->substream);
  187. spin_lock(&aaci->lock);
  188. }
  189. if (!(aacirun->cr & CR_EN))
  190. break;
  191. val = readl(aacirun->base + AACI_SR);
  192. if (!(val & SR_RXHF))
  193. break;
  194. if (!(val & SR_RXFF))
  195. len >>= 1;
  196. aacirun->bytes -= len;
  197. /* reading 16 bytes at a time */
  198. for( ; len > 0; len -= 16) {
  199. asm(
  200. "ldmia %1, {r0, r1, r2, r3}\n\t"
  201. "stmia %0!, {r0, r1, r2, r3}"
  202. : "+r" (ptr)
  203. : "r" (aacirun->fifo)
  204. : "r0", "r1", "r2", "r3", "cc");
  205. if (ptr >= aacirun->end)
  206. ptr = aacirun->start;
  207. }
  208. } while(1);
  209. aacirun->ptr = ptr;
  210. }
  211. if (mask & ISR_URINTR) {
  212. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  213. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  214. }
  215. if (mask & ISR_TXINTR) {
  216. struct aaci_runtime *aacirun = &aaci->playback;
  217. void *ptr;
  218. if (!aacirun->substream || !aacirun->start) {
  219. dev_warn(&aaci->dev->dev, "TX interrupt???\n");
  220. writel(0, aacirun->base + AACI_IE);
  221. return;
  222. }
  223. ptr = aacirun->ptr;
  224. do {
  225. unsigned int len = aacirun->fifosz;
  226. u32 val;
  227. if (aacirun->bytes <= 0) {
  228. aacirun->bytes += aacirun->period;
  229. aacirun->ptr = ptr;
  230. spin_unlock(&aaci->lock);
  231. snd_pcm_period_elapsed(aacirun->substream);
  232. spin_lock(&aaci->lock);
  233. }
  234. if (!(aacirun->cr & CR_EN))
  235. break;
  236. val = readl(aacirun->base + AACI_SR);
  237. if (!(val & SR_TXHE))
  238. break;
  239. if (!(val & SR_TXFE))
  240. len >>= 1;
  241. aacirun->bytes -= len;
  242. /* writing 16 bytes at a time */
  243. for ( ; len > 0; len -= 16) {
  244. asm(
  245. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  246. "stmia %1, {r0, r1, r2, r3}"
  247. : "+r" (ptr)
  248. : "r" (aacirun->fifo)
  249. : "r0", "r1", "r2", "r3", "cc");
  250. if (ptr >= aacirun->end)
  251. ptr = aacirun->start;
  252. }
  253. } while (1);
  254. aacirun->ptr = ptr;
  255. }
  256. }
  257. static irqreturn_t aaci_irq(int irq, void *devid)
  258. {
  259. struct aaci *aaci = devid;
  260. u32 mask;
  261. int i;
  262. spin_lock(&aaci->lock);
  263. mask = readl(aaci->base + AACI_ALLINTS);
  264. if (mask) {
  265. u32 m = mask;
  266. for (i = 0; i < 4; i++, m >>= 7) {
  267. if (m & 0x7f) {
  268. aaci_fifo_irq(aaci, i, m);
  269. }
  270. }
  271. }
  272. spin_unlock(&aaci->lock);
  273. return mask ? IRQ_HANDLED : IRQ_NONE;
  274. }
  275. /*
  276. * ALSA support.
  277. */
  278. struct aaci_stream {
  279. unsigned char codec_idx;
  280. unsigned char rate_idx;
  281. };
  282. static struct aaci_stream aaci_streams[] = {
  283. [ACSTREAM_FRONT] = {
  284. .codec_idx = 0,
  285. .rate_idx = AC97_RATES_FRONT_DAC,
  286. },
  287. [ACSTREAM_SURROUND] = {
  288. .codec_idx = 0,
  289. .rate_idx = AC97_RATES_SURR_DAC,
  290. },
  291. [ACSTREAM_LFE] = {
  292. .codec_idx = 0,
  293. .rate_idx = AC97_RATES_LFE_DAC,
  294. },
  295. };
  296. static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
  297. {
  298. struct aaci_stream *s = aaci_streams + streamid;
  299. return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
  300. }
  301. static unsigned int rate_list[] = {
  302. 5512, 8000, 11025, 16000, 22050, 32000, 44100,
  303. 48000, 64000, 88200, 96000, 176400, 192000
  304. };
  305. /*
  306. * Double-rate rule: we can support double rate iff channels == 2
  307. * (unimplemented)
  308. */
  309. static int
  310. aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  311. {
  312. struct aaci *aaci = rule->private;
  313. unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
  314. struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
  315. switch (c->max) {
  316. case 6:
  317. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
  318. case 4:
  319. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
  320. case 2:
  321. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
  322. }
  323. return snd_interval_list(hw_param_interval(p, rule->var),
  324. ARRAY_SIZE(rate_list), rate_list,
  325. rate_mask);
  326. }
  327. static struct snd_pcm_hardware aaci_hw_info = {
  328. .info = SNDRV_PCM_INFO_MMAP |
  329. SNDRV_PCM_INFO_MMAP_VALID |
  330. SNDRV_PCM_INFO_INTERLEAVED |
  331. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  332. SNDRV_PCM_INFO_RESUME,
  333. /*
  334. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  335. * words. It also doesn't support 12-bit at all.
  336. */
  337. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  338. /* should this be continuous or knot? */
  339. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  340. .rate_max = 48000,
  341. .rate_min = 4000,
  342. .channels_min = 2,
  343. .channels_max = 6,
  344. .buffer_bytes_max = 64 * 1024,
  345. .period_bytes_min = 256,
  346. .period_bytes_max = PAGE_SIZE,
  347. .periods_min = 4,
  348. .periods_max = PAGE_SIZE / 16,
  349. };
  350. static int __aaci_pcm_open(struct aaci *aaci,
  351. struct snd_pcm_substream *substream,
  352. struct aaci_runtime *aacirun)
  353. {
  354. struct snd_pcm_runtime *runtime = substream->runtime;
  355. int ret;
  356. aacirun->substream = substream;
  357. runtime->private_data = aacirun;
  358. runtime->hw = aaci_hw_info;
  359. /*
  360. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  361. * mode, each 32-bit word contains one sample. If we're in
  362. * compact mode, each 32-bit word contains two samples, effectively
  363. * halving the FIFO size. However, we don't know for sure which
  364. * we'll be using at this point. We set this to the lower limit.
  365. */
  366. runtime->hw.fifo_size = aaci->fifosize * 2;
  367. /*
  368. * Add rule describing hardware rate dependency
  369. * on the number of channels.
  370. */
  371. ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  372. aaci_rule_rate_by_channels, aaci,
  373. SNDRV_PCM_HW_PARAM_CHANNELS,
  374. SNDRV_PCM_HW_PARAM_RATE, -1);
  375. if (ret)
  376. goto out;
  377. ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
  378. DRIVER_NAME, aaci);
  379. if (ret)
  380. goto out;
  381. return 0;
  382. out:
  383. return ret;
  384. }
  385. /*
  386. * Common ALSA stuff
  387. */
  388. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  389. {
  390. struct aaci *aaci = substream->private_data;
  391. struct aaci_runtime *aacirun = substream->runtime->private_data;
  392. WARN_ON(aacirun->cr & CR_EN);
  393. aacirun->substream = NULL;
  394. free_irq(aaci->dev->irq[0], aaci);
  395. return 0;
  396. }
  397. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  398. {
  399. struct aaci_runtime *aacirun = substream->runtime->private_data;
  400. /*
  401. * This must not be called with the device enabled.
  402. */
  403. WARN_ON(aacirun->cr & CR_EN);
  404. if (aacirun->pcm_open)
  405. snd_ac97_pcm_close(aacirun->pcm);
  406. aacirun->pcm_open = 0;
  407. /*
  408. * Clear out the DMA and any allocated buffers.
  409. */
  410. devdma_hw_free(NULL, substream);
  411. return 0;
  412. }
  413. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  414. struct aaci_runtime *aacirun,
  415. struct snd_pcm_hw_params *params)
  416. {
  417. int err;
  418. aaci_pcm_hw_free(substream);
  419. if (aacirun->pcm_open) {
  420. snd_ac97_pcm_close(aacirun->pcm);
  421. aacirun->pcm_open = 0;
  422. }
  423. err = devdma_hw_alloc(NULL, substream,
  424. params_buffer_bytes(params));
  425. if (err < 0)
  426. goto out;
  427. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  428. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  429. params_channels(params),
  430. aacirun->pcm->r[0].slots);
  431. else
  432. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  433. params_channels(params),
  434. aacirun->pcm->r[0].slots);
  435. if (err)
  436. goto out;
  437. aacirun->pcm_open = 1;
  438. out:
  439. return err;
  440. }
  441. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  442. {
  443. struct snd_pcm_runtime *runtime = substream->runtime;
  444. struct aaci_runtime *aacirun = runtime->private_data;
  445. aacirun->start = (void *)runtime->dma_area;
  446. aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream);
  447. aacirun->ptr = aacirun->start;
  448. aacirun->period =
  449. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  450. return 0;
  451. }
  452. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  453. {
  454. struct snd_pcm_runtime *runtime = substream->runtime;
  455. struct aaci_runtime *aacirun = runtime->private_data;
  456. ssize_t bytes = aacirun->ptr - aacirun->start;
  457. return bytes_to_frames(runtime, bytes);
  458. }
  459. static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
  460. {
  461. return devdma_mmap(NULL, substream, vma);
  462. }
  463. /*
  464. * Playback specific ALSA stuff
  465. */
  466. static const u32 channels_to_txmask[] = {
  467. [2] = CR_SL3 | CR_SL4,
  468. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  469. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  470. };
  471. /*
  472. * We can support two and four channel audio. Unfortunately
  473. * six channel audio requires a non-standard channel ordering:
  474. * 2 -> FL(3), FR(4)
  475. * 4 -> FL(3), FR(4), SL(7), SR(8)
  476. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  477. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  478. * This requires an ALSA configuration file to correct.
  479. */
  480. static unsigned int channel_list[] = { 2, 4, 6 };
  481. static int
  482. aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  483. {
  484. struct aaci *aaci = rule->private;
  485. unsigned int chan_mask = 1 << 0, slots;
  486. /*
  487. * pcms[0] is the our 5.1 PCM instance.
  488. */
  489. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  490. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  491. chan_mask |= 1 << 1;
  492. if (slots & (1 << AC97_SLOT_LFE))
  493. chan_mask |= 1 << 2;
  494. }
  495. return snd_interval_list(hw_param_interval(p, rule->var),
  496. ARRAY_SIZE(channel_list), channel_list,
  497. chan_mask);
  498. }
  499. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  500. {
  501. struct aaci *aaci = substream->private_data;
  502. int ret;
  503. /*
  504. * Add rule describing channel dependency.
  505. */
  506. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  507. SNDRV_PCM_HW_PARAM_CHANNELS,
  508. aaci_rule_channels, aaci,
  509. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  510. if (ret)
  511. return ret;
  512. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  513. ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
  514. } else {
  515. ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
  516. }
  517. return ret;
  518. }
  519. static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
  520. struct snd_pcm_hw_params *params)
  521. {
  522. struct aaci *aaci = substream->private_data;
  523. struct aaci_runtime *aacirun = substream->runtime->private_data;
  524. unsigned int channels = params_channels(params);
  525. int ret;
  526. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  527. !channels_to_txmask[channels]);
  528. ret = aaci_pcm_hw_params(substream, aacirun, params);
  529. /*
  530. * Enable FIFO, compact mode, 16 bits per sample.
  531. * FIXME: double rate slots?
  532. */
  533. if (ret >= 0) {
  534. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  535. aacirun->cr |= channels_to_txmask[channels];
  536. aacirun->fifosz = aaci->fifosize * 4;
  537. if (aacirun->cr & CR_COMPACT)
  538. aacirun->fifosz >>= 1;
  539. }
  540. return ret;
  541. }
  542. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  543. {
  544. u32 ie;
  545. ie = readl(aacirun->base + AACI_IE);
  546. ie &= ~(IE_URIE|IE_TXIE);
  547. writel(ie, aacirun->base + AACI_IE);
  548. aacirun->cr &= ~CR_EN;
  549. aaci_chan_wait_ready(aacirun);
  550. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  551. }
  552. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  553. {
  554. u32 ie;
  555. aaci_chan_wait_ready(aacirun);
  556. aacirun->cr |= CR_EN;
  557. ie = readl(aacirun->base + AACI_IE);
  558. ie |= IE_URIE | IE_TXIE;
  559. writel(ie, aacirun->base + AACI_IE);
  560. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  561. }
  562. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  563. {
  564. struct aaci *aaci = substream->private_data;
  565. struct aaci_runtime *aacirun = substream->runtime->private_data;
  566. unsigned long flags;
  567. int ret = 0;
  568. spin_lock_irqsave(&aaci->lock, flags);
  569. switch (cmd) {
  570. case SNDRV_PCM_TRIGGER_START:
  571. aaci_pcm_playback_start(aacirun);
  572. break;
  573. case SNDRV_PCM_TRIGGER_RESUME:
  574. aaci_pcm_playback_start(aacirun);
  575. break;
  576. case SNDRV_PCM_TRIGGER_STOP:
  577. aaci_pcm_playback_stop(aacirun);
  578. break;
  579. case SNDRV_PCM_TRIGGER_SUSPEND:
  580. aaci_pcm_playback_stop(aacirun);
  581. break;
  582. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  583. break;
  584. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  585. break;
  586. default:
  587. ret = -EINVAL;
  588. }
  589. spin_unlock_irqrestore(&aaci->lock, flags);
  590. return ret;
  591. }
  592. static struct snd_pcm_ops aaci_playback_ops = {
  593. .open = aaci_pcm_open,
  594. .close = aaci_pcm_close,
  595. .ioctl = snd_pcm_lib_ioctl,
  596. .hw_params = aaci_pcm_playback_hw_params,
  597. .hw_free = aaci_pcm_hw_free,
  598. .prepare = aaci_pcm_prepare,
  599. .trigger = aaci_pcm_playback_trigger,
  600. .pointer = aaci_pcm_pointer,
  601. .mmap = aaci_pcm_mmap,
  602. };
  603. static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
  604. struct snd_pcm_hw_params *params)
  605. {
  606. struct aaci *aaci = substream->private_data;
  607. struct aaci_runtime *aacirun = substream->runtime->private_data;
  608. int ret;
  609. ret = aaci_pcm_hw_params(substream, aacirun, params);
  610. if (ret >= 0) {
  611. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  612. /* Line in record: slot 3 and 4 */
  613. aacirun->cr |= CR_SL3 | CR_SL4;
  614. aacirun->fifosz = aaci->fifosize * 4;
  615. if (aacirun->cr & CR_COMPACT)
  616. aacirun->fifosz >>= 1;
  617. }
  618. return ret;
  619. }
  620. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  621. {
  622. u32 ie;
  623. aaci_chan_wait_ready(aacirun);
  624. ie = readl(aacirun->base + AACI_IE);
  625. ie &= ~(IE_ORIE | IE_RXIE);
  626. writel(ie, aacirun->base+AACI_IE);
  627. aacirun->cr &= ~CR_EN;
  628. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  629. }
  630. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  631. {
  632. u32 ie;
  633. aaci_chan_wait_ready(aacirun);
  634. #ifdef DEBUG
  635. /* RX Timeout value: bits 28:17 in RXCR */
  636. aacirun->cr |= 0xf << 17;
  637. #endif
  638. aacirun->cr |= CR_EN;
  639. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  640. ie = readl(aacirun->base + AACI_IE);
  641. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  642. writel(ie, aacirun->base + AACI_IE);
  643. }
  644. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  645. {
  646. struct aaci *aaci = substream->private_data;
  647. struct aaci_runtime *aacirun = substream->runtime->private_data;
  648. unsigned long flags;
  649. int ret = 0;
  650. spin_lock_irqsave(&aaci->lock, flags);
  651. switch (cmd) {
  652. case SNDRV_PCM_TRIGGER_START:
  653. aaci_pcm_capture_start(aacirun);
  654. break;
  655. case SNDRV_PCM_TRIGGER_RESUME:
  656. aaci_pcm_capture_start(aacirun);
  657. break;
  658. case SNDRV_PCM_TRIGGER_STOP:
  659. aaci_pcm_capture_stop(aacirun);
  660. break;
  661. case SNDRV_PCM_TRIGGER_SUSPEND:
  662. aaci_pcm_capture_stop(aacirun);
  663. break;
  664. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  665. break;
  666. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  667. break;
  668. default:
  669. ret = -EINVAL;
  670. }
  671. spin_unlock_irqrestore(&aaci->lock, flags);
  672. return ret;
  673. }
  674. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  675. {
  676. struct snd_pcm_runtime *runtime = substream->runtime;
  677. struct aaci *aaci = substream->private_data;
  678. aaci_pcm_prepare(substream);
  679. /* allow changing of sample rate */
  680. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  681. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  682. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  683. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  684. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  685. return 0;
  686. }
  687. static struct snd_pcm_ops aaci_capture_ops = {
  688. .open = aaci_pcm_open,
  689. .close = aaci_pcm_close,
  690. .ioctl = snd_pcm_lib_ioctl,
  691. .hw_params = aaci_pcm_capture_hw_params,
  692. .hw_free = aaci_pcm_hw_free,
  693. .prepare = aaci_pcm_capture_prepare,
  694. .trigger = aaci_pcm_capture_trigger,
  695. .pointer = aaci_pcm_pointer,
  696. .mmap = aaci_pcm_mmap,
  697. };
  698. /*
  699. * Power Management.
  700. */
  701. #ifdef CONFIG_PM
  702. static int aaci_do_suspend(struct snd_card *card, unsigned int state)
  703. {
  704. struct aaci *aaci = card->private_data;
  705. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  706. snd_pcm_suspend_all(aaci->pcm);
  707. return 0;
  708. }
  709. static int aaci_do_resume(struct snd_card *card, unsigned int state)
  710. {
  711. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  712. return 0;
  713. }
  714. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  715. {
  716. struct snd_card *card = amba_get_drvdata(dev);
  717. return card ? aaci_do_suspend(card) : 0;
  718. }
  719. static int aaci_resume(struct amba_device *dev)
  720. {
  721. struct snd_card *card = amba_get_drvdata(dev);
  722. return card ? aaci_do_resume(card) : 0;
  723. }
  724. #else
  725. #define aaci_do_suspend NULL
  726. #define aaci_do_resume NULL
  727. #define aaci_suspend NULL
  728. #define aaci_resume NULL
  729. #endif
  730. static struct ac97_pcm ac97_defs[] __devinitdata = {
  731. [0] = { /* Front PCM */
  732. .exclusive = 1,
  733. .r = {
  734. [0] = {
  735. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  736. (1 << AC97_SLOT_PCM_RIGHT) |
  737. (1 << AC97_SLOT_PCM_CENTER) |
  738. (1 << AC97_SLOT_PCM_SLEFT) |
  739. (1 << AC97_SLOT_PCM_SRIGHT) |
  740. (1 << AC97_SLOT_LFE),
  741. },
  742. },
  743. },
  744. [1] = { /* PCM in */
  745. .stream = 1,
  746. .exclusive = 1,
  747. .r = {
  748. [0] = {
  749. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  750. (1 << AC97_SLOT_PCM_RIGHT),
  751. },
  752. },
  753. },
  754. [2] = { /* Mic in */
  755. .stream = 1,
  756. .exclusive = 1,
  757. .r = {
  758. [0] = {
  759. .slots = (1 << AC97_SLOT_MIC),
  760. },
  761. },
  762. }
  763. };
  764. static struct snd_ac97_bus_ops aaci_bus_ops = {
  765. .write = aaci_ac97_write,
  766. .read = aaci_ac97_read,
  767. };
  768. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  769. {
  770. struct snd_ac97_template ac97_template;
  771. struct snd_ac97_bus *ac97_bus;
  772. struct snd_ac97 *ac97;
  773. int ret;
  774. writel(0, aaci->base + AC97_POWERDOWN);
  775. /*
  776. * Assert AACIRESET for 2us
  777. */
  778. writel(0, aaci->base + AACI_RESET);
  779. udelay(2);
  780. writel(RESET_NRST, aaci->base + AACI_RESET);
  781. /*
  782. * Give the AC'97 codec more than enough time
  783. * to wake up. (42us = ~2 frames at 48kHz.)
  784. */
  785. udelay(42);
  786. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  787. if (ret)
  788. goto out;
  789. ac97_bus->clock = 48000;
  790. aaci->ac97_bus = ac97_bus;
  791. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  792. ac97_template.private_data = aaci;
  793. ac97_template.num = 0;
  794. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  795. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  796. if (ret)
  797. goto out;
  798. aaci->ac97 = ac97;
  799. /*
  800. * Disable AC97 PC Beep input on audio codecs.
  801. */
  802. if (ac97_is_audio(ac97))
  803. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  804. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  805. if (ret)
  806. goto out;
  807. aaci->playback.pcm = &ac97_bus->pcms[0];
  808. aaci->capture.pcm = &ac97_bus->pcms[1];
  809. out:
  810. return ret;
  811. }
  812. static void aaci_free_card(struct snd_card *card)
  813. {
  814. struct aaci *aaci = card->private_data;
  815. if (aaci->base)
  816. iounmap(aaci->base);
  817. }
  818. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  819. {
  820. struct aaci *aaci;
  821. struct snd_card *card;
  822. int err;
  823. err = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  824. THIS_MODULE, sizeof(struct aaci), &card);
  825. if (err < 0)
  826. return NULL;
  827. card->private_free = aaci_free_card;
  828. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  829. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  830. snprintf(card->longname, sizeof(card->longname),
  831. "%s at 0x%016llx, irq %d",
  832. card->shortname, (unsigned long long)dev->res.start,
  833. dev->irq[0]);
  834. aaci = card->private_data;
  835. mutex_init(&aaci->ac97_sem);
  836. spin_lock_init(&aaci->lock);
  837. aaci->card = card;
  838. aaci->dev = dev;
  839. /* Set MAINCR to allow slot 1 and 2 data IO */
  840. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  841. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  842. return aaci;
  843. }
  844. static int __devinit aaci_init_pcm(struct aaci *aaci)
  845. {
  846. struct snd_pcm *pcm;
  847. int ret;
  848. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  849. if (ret == 0) {
  850. aaci->pcm = pcm;
  851. pcm->private_data = aaci;
  852. pcm->info_flags = 0;
  853. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  854. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  855. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  856. }
  857. return ret;
  858. }
  859. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  860. {
  861. struct aaci_runtime *aacirun = &aaci->playback;
  862. int i;
  863. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  864. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  865. writel(0, aacirun->fifo);
  866. writel(0, aacirun->base + AACI_TXCR);
  867. /*
  868. * Re-initialise the AACI after the FIFO depth test, to
  869. * ensure that the FIFOs are empty. Unfortunately, merely
  870. * disabling the channel doesn't clear the FIFO.
  871. */
  872. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  873. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  874. /*
  875. * If we hit 4096, we failed. Go back to the specified
  876. * fifo depth.
  877. */
  878. if (i == 4096)
  879. i = 8;
  880. return i;
  881. }
  882. static int __devinit aaci_probe(struct amba_device *dev, struct amba_id *id)
  883. {
  884. struct aaci *aaci;
  885. int ret, i;
  886. ret = amba_request_regions(dev, NULL);
  887. if (ret)
  888. return ret;
  889. aaci = aaci_init_card(dev);
  890. if (!aaci) {
  891. ret = -ENOMEM;
  892. goto out;
  893. }
  894. aaci->base = ioremap(dev->res.start, resource_size(&dev->res));
  895. if (!aaci->base) {
  896. ret = -ENOMEM;
  897. goto out;
  898. }
  899. /*
  900. * Playback uses AACI channel 0
  901. */
  902. aaci->playback.base = aaci->base + AACI_CSCH1;
  903. aaci->playback.fifo = aaci->base + AACI_DR1;
  904. /*
  905. * Capture uses AACI channel 0
  906. */
  907. aaci->capture.base = aaci->base + AACI_CSCH1;
  908. aaci->capture.fifo = aaci->base + AACI_DR1;
  909. for (i = 0; i < 4; i++) {
  910. void __iomem *base = aaci->base + i * 0x14;
  911. writel(0, base + AACI_IE);
  912. writel(0, base + AACI_TXCR);
  913. writel(0, base + AACI_RXCR);
  914. }
  915. writel(0x1fff, aaci->base + AACI_INTCLR);
  916. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  917. ret = aaci_probe_ac97(aaci);
  918. if (ret)
  919. goto out;
  920. /*
  921. * Size the FIFOs (must be multiple of 16).
  922. */
  923. aaci->fifosize = aaci_size_fifo(aaci);
  924. if (aaci->fifosize & 15) {
  925. printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
  926. aaci->fifosize);
  927. ret = -ENODEV;
  928. goto out;
  929. }
  930. ret = aaci_init_pcm(aaci);
  931. if (ret)
  932. goto out;
  933. snd_card_set_dev(aaci->card, &dev->dev);
  934. ret = snd_card_register(aaci->card);
  935. if (ret == 0) {
  936. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  937. aaci->fifosize);
  938. amba_set_drvdata(dev, aaci->card);
  939. return ret;
  940. }
  941. out:
  942. if (aaci)
  943. snd_card_free(aaci->card);
  944. amba_release_regions(dev);
  945. return ret;
  946. }
  947. static int __devexit aaci_remove(struct amba_device *dev)
  948. {
  949. struct snd_card *card = amba_get_drvdata(dev);
  950. amba_set_drvdata(dev, NULL);
  951. if (card) {
  952. struct aaci *aaci = card->private_data;
  953. writel(0, aaci->base + AACI_MAINCR);
  954. snd_card_free(card);
  955. amba_release_regions(dev);
  956. }
  957. return 0;
  958. }
  959. static struct amba_id aaci_ids[] = {
  960. {
  961. .id = 0x00041041,
  962. .mask = 0x000fffff,
  963. },
  964. { 0, 0 },
  965. };
  966. static struct amba_driver aaci_driver = {
  967. .drv = {
  968. .name = DRIVER_NAME,
  969. },
  970. .probe = aaci_probe,
  971. .remove = __devexit_p(aaci_remove),
  972. .suspend = aaci_suspend,
  973. .resume = aaci_resume,
  974. .id_table = aaci_ids,
  975. };
  976. static int __init aaci_init(void)
  977. {
  978. return amba_driver_register(&aaci_driver);
  979. }
  980. static void __exit aaci_exit(void)
  981. {
  982. amba_driver_unregister(&aaci_driver);
  983. }
  984. module_init(aaci_init);
  985. module_exit(aaci_exit);
  986. MODULE_LICENSE("GPL");
  987. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");