arch_timer.c 12 KB

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  1. /*
  2. * linux/arch/arm/kernel/arch_timer.c
  3. *
  4. * Copyright (C) 2011 ARM Ltd.
  5. * All Rights Reserved
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/device.h>
  15. #include <linux/smp.h>
  16. #include <linux/cpu.h>
  17. #include <linux/jiffies.h>
  18. #include <linux/clockchips.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/io.h>
  22. #include <asm/delay.h>
  23. #include <asm/localtimer.h>
  24. #include <asm/arch_timer.h>
  25. #include <asm/sched_clock.h>
  26. static u32 arch_timer_rate;
  27. enum ppi_nr {
  28. PHYS_SECURE_PPI,
  29. PHYS_NONSECURE_PPI,
  30. VIRT_PPI,
  31. HYP_PPI,
  32. MAX_TIMER_PPI
  33. };
  34. static int arch_timer_ppi[MAX_TIMER_PPI];
  35. static struct clock_event_device __percpu **arch_timer_evt;
  36. static struct delay_timer arch_delay_timer;
  37. static bool arch_timer_use_virtual = true;
  38. /*
  39. * Architected system timer support.
  40. */
  41. #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
  42. #define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
  43. #define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
  44. #define ARCH_TIMER_REG_CTRL 0
  45. #define ARCH_TIMER_REG_FREQ 1
  46. #define ARCH_TIMER_REG_TVAL 2
  47. #define ARCH_TIMER_PHYS_ACCESS 0
  48. #define ARCH_TIMER_VIRT_ACCESS 1
  49. /*
  50. * These register accessors are marked inline so the compiler can
  51. * nicely work out which register we want, and chuck away the rest of
  52. * the code. At least it does so with a recent GCC (4.6.3).
  53. */
  54. static inline void arch_timer_reg_write(const int access, const int reg, u32 val)
  55. {
  56. if (access == ARCH_TIMER_PHYS_ACCESS) {
  57. switch (reg) {
  58. case ARCH_TIMER_REG_CTRL:
  59. asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
  60. break;
  61. case ARCH_TIMER_REG_TVAL:
  62. asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
  63. break;
  64. }
  65. }
  66. if (access == ARCH_TIMER_VIRT_ACCESS) {
  67. switch (reg) {
  68. case ARCH_TIMER_REG_CTRL:
  69. asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
  70. break;
  71. case ARCH_TIMER_REG_TVAL:
  72. asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
  73. break;
  74. }
  75. }
  76. isb();
  77. }
  78. static inline u32 arch_timer_reg_read(const int access, const int reg)
  79. {
  80. u32 val = 0;
  81. if (access == ARCH_TIMER_PHYS_ACCESS) {
  82. switch (reg) {
  83. case ARCH_TIMER_REG_CTRL:
  84. asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
  85. break;
  86. case ARCH_TIMER_REG_TVAL:
  87. asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
  88. break;
  89. case ARCH_TIMER_REG_FREQ:
  90. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
  91. break;
  92. }
  93. }
  94. if (access == ARCH_TIMER_VIRT_ACCESS) {
  95. switch (reg) {
  96. case ARCH_TIMER_REG_CTRL:
  97. asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
  98. break;
  99. case ARCH_TIMER_REG_TVAL:
  100. asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val));
  101. break;
  102. }
  103. }
  104. return val;
  105. }
  106. static inline u64 arch_counter_get_cntpct(void)
  107. {
  108. u64 cval;
  109. asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
  110. return cval;
  111. }
  112. static inline u64 arch_counter_get_cntvct(void)
  113. {
  114. u64 cval;
  115. asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
  116. return cval;
  117. }
  118. static irqreturn_t inline timer_handler(const int access,
  119. struct clock_event_device *evt)
  120. {
  121. unsigned long ctrl;
  122. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
  123. if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
  124. ctrl |= ARCH_TIMER_CTRL_IT_MASK;
  125. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
  126. evt->event_handler(evt);
  127. return IRQ_HANDLED;
  128. }
  129. return IRQ_NONE;
  130. }
  131. static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
  132. {
  133. struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  134. return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
  135. }
  136. static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
  137. {
  138. struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  139. return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
  140. }
  141. static inline void timer_set_mode(const int access, int mode)
  142. {
  143. unsigned long ctrl;
  144. switch (mode) {
  145. case CLOCK_EVT_MODE_UNUSED:
  146. case CLOCK_EVT_MODE_SHUTDOWN:
  147. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
  148. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  149. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
  150. break;
  151. default:
  152. break;
  153. }
  154. }
  155. static void arch_timer_set_mode_virt(enum clock_event_mode mode,
  156. struct clock_event_device *clk)
  157. {
  158. timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
  159. }
  160. static void arch_timer_set_mode_phys(enum clock_event_mode mode,
  161. struct clock_event_device *clk)
  162. {
  163. timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
  164. }
  165. static inline void set_next_event(const int access, unsigned long evt)
  166. {
  167. unsigned long ctrl;
  168. ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
  169. ctrl |= ARCH_TIMER_CTRL_ENABLE;
  170. ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
  171. arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
  172. arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
  173. }
  174. static int arch_timer_set_next_event_virt(unsigned long evt,
  175. struct clock_event_device *unused)
  176. {
  177. set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
  178. return 0;
  179. }
  180. static int arch_timer_set_next_event_phys(unsigned long evt,
  181. struct clock_event_device *unused)
  182. {
  183. set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
  184. return 0;
  185. }
  186. static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
  187. {
  188. clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
  189. clk->name = "arch_sys_timer";
  190. clk->rating = 450;
  191. if (arch_timer_use_virtual) {
  192. clk->irq = arch_timer_ppi[VIRT_PPI];
  193. clk->set_mode = arch_timer_set_mode_virt;
  194. clk->set_next_event = arch_timer_set_next_event_virt;
  195. } else {
  196. clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
  197. clk->set_mode = arch_timer_set_mode_phys;
  198. clk->set_next_event = arch_timer_set_next_event_phys;
  199. }
  200. clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
  201. clockevents_config_and_register(clk, arch_timer_rate,
  202. 0xf, 0x7fffffff);
  203. *__this_cpu_ptr(arch_timer_evt) = clk;
  204. if (arch_timer_use_virtual)
  205. enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
  206. else {
  207. enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
  208. if (arch_timer_ppi[PHYS_NONSECURE_PPI])
  209. enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
  210. }
  211. return 0;
  212. }
  213. static int arch_timer_available(void)
  214. {
  215. u32 freq;
  216. if (arch_timer_rate == 0) {
  217. freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS,
  218. ARCH_TIMER_REG_FREQ);
  219. /* Check the timer frequency. */
  220. if (freq == 0) {
  221. pr_warn("Architected timer frequency not available\n");
  222. return -EINVAL;
  223. }
  224. arch_timer_rate = freq;
  225. }
  226. pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
  227. (unsigned long)arch_timer_rate / 1000000,
  228. (unsigned long)(arch_timer_rate / 10000) % 100,
  229. arch_timer_use_virtual ? "virt" : "phys");
  230. return 0;
  231. }
  232. static u32 notrace arch_counter_get_cntpct32(void)
  233. {
  234. cycle_t cnt = arch_counter_get_cntpct();
  235. /*
  236. * The sched_clock infrastructure only knows about counters
  237. * with at most 32bits. Forget about the upper 24 bits for the
  238. * time being...
  239. */
  240. return (u32)cnt;
  241. }
  242. static u32 notrace arch_counter_get_cntvct32(void)
  243. {
  244. cycle_t cnt = arch_counter_get_cntvct();
  245. /*
  246. * The sched_clock infrastructure only knows about counters
  247. * with at most 32bits. Forget about the upper 24 bits for the
  248. * time being...
  249. */
  250. return (u32)cnt;
  251. }
  252. static cycle_t arch_counter_read(struct clocksource *cs)
  253. {
  254. /*
  255. * Always use the physical counter for the clocksource.
  256. * CNTHCTL.PL1PCTEN must be set to 1.
  257. */
  258. return arch_counter_get_cntpct();
  259. }
  260. static unsigned long arch_timer_read_current_timer(void)
  261. {
  262. return arch_counter_get_cntpct();
  263. }
  264. static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
  265. {
  266. /*
  267. * Always use the physical counter for the clocksource.
  268. * CNTHCTL.PL1PCTEN must be set to 1.
  269. */
  270. return arch_counter_get_cntpct();
  271. }
  272. static struct clocksource clocksource_counter = {
  273. .name = "arch_sys_counter",
  274. .rating = 400,
  275. .read = arch_counter_read,
  276. .mask = CLOCKSOURCE_MASK(56),
  277. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  278. };
  279. static struct cyclecounter cyclecounter = {
  280. .read = arch_counter_read_cc,
  281. .mask = CLOCKSOURCE_MASK(56),
  282. };
  283. static struct timecounter timecounter;
  284. struct timecounter *arch_timer_get_timecounter(void)
  285. {
  286. return &timecounter;
  287. }
  288. static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
  289. {
  290. pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
  291. clk->irq, smp_processor_id());
  292. if (arch_timer_use_virtual)
  293. disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
  294. else {
  295. disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
  296. if (arch_timer_ppi[PHYS_NONSECURE_PPI])
  297. disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
  298. }
  299. clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
  300. }
  301. static struct local_timer_ops arch_timer_ops __cpuinitdata = {
  302. .setup = arch_timer_setup,
  303. .stop = arch_timer_stop,
  304. };
  305. static struct clock_event_device arch_timer_global_evt;
  306. static int __init arch_timer_register(void)
  307. {
  308. int err;
  309. int ppi;
  310. err = arch_timer_available();
  311. if (err)
  312. goto out;
  313. arch_timer_evt = alloc_percpu(struct clock_event_device *);
  314. if (!arch_timer_evt) {
  315. err = -ENOMEM;
  316. goto out;
  317. }
  318. clocksource_register_hz(&clocksource_counter, arch_timer_rate);
  319. cyclecounter.mult = clocksource_counter.mult;
  320. cyclecounter.shift = clocksource_counter.shift;
  321. timecounter_init(&timecounter, &cyclecounter,
  322. arch_counter_get_cntpct());
  323. if (arch_timer_use_virtual) {
  324. ppi = arch_timer_ppi[VIRT_PPI];
  325. err = request_percpu_irq(ppi, arch_timer_handler_virt,
  326. "arch_timer", arch_timer_evt);
  327. } else {
  328. ppi = arch_timer_ppi[PHYS_SECURE_PPI];
  329. err = request_percpu_irq(ppi, arch_timer_handler_phys,
  330. "arch_timer", arch_timer_evt);
  331. if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
  332. ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
  333. err = request_percpu_irq(ppi, arch_timer_handler_phys,
  334. "arch_timer", arch_timer_evt);
  335. if (err)
  336. free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
  337. arch_timer_evt);
  338. }
  339. }
  340. if (err) {
  341. pr_err("arch_timer: can't register interrupt %d (%d)\n",
  342. ppi, err);
  343. goto out_free;
  344. }
  345. err = local_timer_register(&arch_timer_ops);
  346. if (err) {
  347. /*
  348. * We couldn't register as a local timer (could be
  349. * because we're on a UP platform, or because some
  350. * other local timer is already present...). Try as a
  351. * global timer instead.
  352. */
  353. arch_timer_global_evt.cpumask = cpumask_of(0);
  354. err = arch_timer_setup(&arch_timer_global_evt);
  355. }
  356. if (err)
  357. goto out_free_irq;
  358. /* Use the architected timer for the delay loop. */
  359. arch_delay_timer.read_current_timer = &arch_timer_read_current_timer;
  360. arch_delay_timer.freq = arch_timer_rate;
  361. register_current_timer_delay(&arch_delay_timer);
  362. return 0;
  363. out_free_irq:
  364. if (arch_timer_use_virtual)
  365. free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
  366. else {
  367. free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
  368. arch_timer_evt);
  369. if (arch_timer_ppi[PHYS_NONSECURE_PPI])
  370. free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
  371. arch_timer_evt);
  372. }
  373. out_free:
  374. free_percpu(arch_timer_evt);
  375. out:
  376. return err;
  377. }
  378. static const struct of_device_id arch_timer_of_match[] __initconst = {
  379. { .compatible = "arm,armv7-timer", },
  380. {},
  381. };
  382. int __init arch_timer_of_register(void)
  383. {
  384. struct device_node *np;
  385. u32 freq;
  386. int i;
  387. np = of_find_matching_node(NULL, arch_timer_of_match);
  388. if (!np) {
  389. pr_err("arch_timer: can't find DT node\n");
  390. return -ENODEV;
  391. }
  392. /* Try to determine the frequency from the device tree or CNTFRQ */
  393. if (!of_property_read_u32(np, "clock-frequency", &freq))
  394. arch_timer_rate = freq;
  395. for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
  396. arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
  397. of_node_put(np);
  398. /*
  399. * If no interrupt provided for virtual timer, we'll have to
  400. * stick to the physical timer. It'd better be accessible...
  401. */
  402. if (!arch_timer_ppi[VIRT_PPI]) {
  403. arch_timer_use_virtual = false;
  404. if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
  405. !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
  406. pr_warn("arch_timer: No interrupt available, giving up\n");
  407. return -EINVAL;
  408. }
  409. }
  410. return arch_timer_register();
  411. }
  412. int __init arch_timer_sched_clock_init(void)
  413. {
  414. u32 (*cnt32)(void);
  415. int err;
  416. err = arch_timer_available();
  417. if (err)
  418. return err;
  419. if (arch_timer_use_virtual)
  420. cnt32 = arch_counter_get_cntvct32;
  421. else
  422. cnt32 = arch_counter_get_cntpct32;
  423. setup_sched_clock(cnt32, 32, arch_timer_rate);
  424. return 0;
  425. }