setup_64.c 33 KB

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  1. /*
  2. * Copyright (C) 1995 Linus Torvalds
  3. */
  4. /*
  5. * This file handles the architecture-dependent parts of initialization
  6. */
  7. #include <linux/errno.h>
  8. #include <linux/sched.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mm.h>
  11. #include <linux/stddef.h>
  12. #include <linux/unistd.h>
  13. #include <linux/ptrace.h>
  14. #include <linux/slab.h>
  15. #include <linux/user.h>
  16. #include <linux/screen_info.h>
  17. #include <linux/ioport.h>
  18. #include <linux/delay.h>
  19. #include <linux/init.h>
  20. #include <linux/initrd.h>
  21. #include <linux/highmem.h>
  22. #include <linux/bootmem.h>
  23. #include <linux/module.h>
  24. #include <asm/processor.h>
  25. #include <linux/console.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/crash_dump.h>
  28. #include <linux/root_dev.h>
  29. #include <linux/pci.h>
  30. #include <asm/pci-direct.h>
  31. #include <linux/efi.h>
  32. #include <linux/acpi.h>
  33. #include <linux/kallsyms.h>
  34. #include <linux/edd.h>
  35. #include <linux/iscsi_ibft.h>
  36. #include <linux/mmzone.h>
  37. #include <linux/kexec.h>
  38. #include <linux/cpufreq.h>
  39. #include <linux/dmi.h>
  40. #include <linux/dma-mapping.h>
  41. #include <linux/ctype.h>
  42. #include <linux/sort.h>
  43. #include <linux/uaccess.h>
  44. #include <linux/init_ohci1394_dma.h>
  45. #include <asm/mtrr.h>
  46. #include <asm/uaccess.h>
  47. #include <asm/system.h>
  48. #include <asm/vsyscall.h>
  49. #include <asm/io.h>
  50. #include <asm/smp.h>
  51. #include <asm/msr.h>
  52. #include <asm/desc.h>
  53. #include <video/edid.h>
  54. #include <asm/e820.h>
  55. #include <asm/dma.h>
  56. #include <asm/gart.h>
  57. #include <asm/mpspec.h>
  58. #include <asm/mmu_context.h>
  59. #include <asm/proto.h>
  60. #include <asm/setup.h>
  61. #include <asm/numa.h>
  62. #include <asm/sections.h>
  63. #include <asm/dmi.h>
  64. #include <asm/cacheflush.h>
  65. #include <asm/mce.h>
  66. #include <asm/ds.h>
  67. #include <asm/topology.h>
  68. #include <asm/trampoline.h>
  69. #include <mach_apic.h>
  70. #ifdef CONFIG_PARAVIRT
  71. #include <asm/paravirt.h>
  72. #else
  73. #define ARCH_SETUP
  74. #endif
  75. /*
  76. * Machine setup..
  77. */
  78. struct cpuinfo_x86 boot_cpu_data __read_mostly;
  79. EXPORT_SYMBOL(boot_cpu_data);
  80. __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  81. unsigned long mmu_cr4_features;
  82. /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  83. int bootloader_type;
  84. unsigned long saved_video_mode;
  85. int force_mwait __cpuinitdata;
  86. /*
  87. * Early DMI memory
  88. */
  89. int dmi_alloc_index;
  90. char dmi_alloc_data[DMI_MAX_DATA];
  91. /*
  92. * Setup options
  93. */
  94. struct screen_info screen_info;
  95. EXPORT_SYMBOL(screen_info);
  96. struct sys_desc_table_struct {
  97. unsigned short length;
  98. unsigned char table[0];
  99. };
  100. struct edid_info edid_info;
  101. EXPORT_SYMBOL_GPL(edid_info);
  102. extern int root_mountflags;
  103. char __initdata command_line[COMMAND_LINE_SIZE];
  104. static struct resource standard_io_resources[] = {
  105. { .name = "dma1", .start = 0x00, .end = 0x1f,
  106. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  107. { .name = "pic1", .start = 0x20, .end = 0x21,
  108. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  109. { .name = "timer0", .start = 0x40, .end = 0x43,
  110. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  111. { .name = "timer1", .start = 0x50, .end = 0x53,
  112. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  113. { .name = "keyboard", .start = 0x60, .end = 0x6f,
  114. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  115. { .name = "dma page reg", .start = 0x80, .end = 0x8f,
  116. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  117. { .name = "pic2", .start = 0xa0, .end = 0xa1,
  118. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  119. { .name = "dma2", .start = 0xc0, .end = 0xdf,
  120. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  121. { .name = "fpu", .start = 0xf0, .end = 0xff,
  122. .flags = IORESOURCE_BUSY | IORESOURCE_IO }
  123. };
  124. #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
  125. static struct resource data_resource = {
  126. .name = "Kernel data",
  127. .start = 0,
  128. .end = 0,
  129. .flags = IORESOURCE_RAM,
  130. };
  131. static struct resource code_resource = {
  132. .name = "Kernel code",
  133. .start = 0,
  134. .end = 0,
  135. .flags = IORESOURCE_RAM,
  136. };
  137. static struct resource bss_resource = {
  138. .name = "Kernel bss",
  139. .start = 0,
  140. .end = 0,
  141. .flags = IORESOURCE_RAM,
  142. };
  143. static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
  144. #ifdef CONFIG_PROC_VMCORE
  145. /* elfcorehdr= specifies the location of elf core header
  146. * stored by the crashed kernel. This option will be passed
  147. * by kexec loader to the capture kernel.
  148. */
  149. static int __init setup_elfcorehdr(char *arg)
  150. {
  151. char *end;
  152. if (!arg)
  153. return -EINVAL;
  154. elfcorehdr_addr = memparse(arg, &end);
  155. return end > arg ? 0 : -EINVAL;
  156. }
  157. early_param("elfcorehdr", setup_elfcorehdr);
  158. #endif
  159. #ifndef CONFIG_NUMA
  160. static void __init
  161. contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
  162. {
  163. unsigned long bootmap_size, bootmap;
  164. bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
  165. bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
  166. PAGE_SIZE);
  167. if (bootmap == -1L)
  168. panic("Cannot find bootmem map of size %ld\n", bootmap_size);
  169. bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
  170. e820_register_active_regions(0, start_pfn, end_pfn);
  171. free_bootmem_with_active_regions(0, end_pfn);
  172. early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
  173. reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
  174. }
  175. #endif
  176. #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
  177. struct edd edd;
  178. #ifdef CONFIG_EDD_MODULE
  179. EXPORT_SYMBOL(edd);
  180. #endif
  181. /**
  182. * copy_edd() - Copy the BIOS EDD information
  183. * from boot_params into a safe place.
  184. *
  185. */
  186. static inline void copy_edd(void)
  187. {
  188. memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
  189. sizeof(edd.mbr_signature));
  190. memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
  191. edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
  192. edd.edd_info_nr = boot_params.eddbuf_entries;
  193. }
  194. #else
  195. static inline void copy_edd(void)
  196. {
  197. }
  198. #endif
  199. #ifdef CONFIG_KEXEC
  200. static void __init reserve_crashkernel(void)
  201. {
  202. unsigned long long total_mem;
  203. unsigned long long crash_size, crash_base;
  204. int ret;
  205. total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
  206. ret = parse_crashkernel(boot_command_line, total_mem,
  207. &crash_size, &crash_base);
  208. if (ret == 0 && crash_size) {
  209. if (crash_base <= 0) {
  210. printk(KERN_INFO "crashkernel reservation failed - "
  211. "you have to specify a base address\n");
  212. return;
  213. }
  214. if (reserve_bootmem(crash_base, crash_size,
  215. BOOTMEM_EXCLUSIVE) < 0) {
  216. printk(KERN_INFO "crashkernel reservation failed - "
  217. "memory is in use\n");
  218. return;
  219. }
  220. printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
  221. "for crashkernel (System RAM: %ldMB)\n",
  222. (unsigned long)(crash_size >> 20),
  223. (unsigned long)(crash_base >> 20),
  224. (unsigned long)(total_mem >> 20));
  225. crashk_res.start = crash_base;
  226. crashk_res.end = crash_base + crash_size - 1;
  227. insert_resource(&iomem_resource, &crashk_res);
  228. }
  229. }
  230. #else
  231. static inline void __init reserve_crashkernel(void)
  232. {}
  233. #endif
  234. /* Overridden in paravirt.c if CONFIG_PARAVIRT */
  235. void __attribute__((weak)) __init memory_setup(void)
  236. {
  237. machine_specific_memory_setup();
  238. }
  239. static void __init parse_setup_data(void)
  240. {
  241. struct setup_data *data;
  242. unsigned long pa_data;
  243. if (boot_params.hdr.version < 0x0209)
  244. return;
  245. pa_data = boot_params.hdr.setup_data;
  246. while (pa_data) {
  247. data = early_ioremap(pa_data, PAGE_SIZE);
  248. switch (data->type) {
  249. default:
  250. break;
  251. }
  252. #ifndef CONFIG_DEBUG_BOOT_PARAMS
  253. free_early(pa_data, pa_data+sizeof(*data)+data->len);
  254. #endif
  255. pa_data = data->next;
  256. early_iounmap(data, PAGE_SIZE);
  257. }
  258. }
  259. /*
  260. * setup_arch - architecture-specific boot-time initializations
  261. *
  262. * Note: On x86_64, fixmaps are ready for use even before this is called.
  263. */
  264. void __init setup_arch(char **cmdline_p)
  265. {
  266. unsigned i;
  267. printk(KERN_INFO "Command line: %s\n", boot_command_line);
  268. ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
  269. screen_info = boot_params.screen_info;
  270. edid_info = boot_params.edid_info;
  271. saved_video_mode = boot_params.hdr.vid_mode;
  272. bootloader_type = boot_params.hdr.type_of_loader;
  273. #ifdef CONFIG_BLK_DEV_RAM
  274. rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
  275. rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
  276. rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
  277. #endif
  278. #ifdef CONFIG_EFI
  279. if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
  280. "EL64", 4))
  281. efi_enabled = 1;
  282. #endif
  283. ARCH_SETUP
  284. memory_setup();
  285. copy_edd();
  286. if (!boot_params.hdr.root_flags)
  287. root_mountflags &= ~MS_RDONLY;
  288. init_mm.start_code = (unsigned long) &_text;
  289. init_mm.end_code = (unsigned long) &_etext;
  290. init_mm.end_data = (unsigned long) &_edata;
  291. init_mm.brk = (unsigned long) &_end;
  292. code_resource.start = virt_to_phys(&_text);
  293. code_resource.end = virt_to_phys(&_etext)-1;
  294. data_resource.start = virt_to_phys(&_etext);
  295. data_resource.end = virt_to_phys(&_edata)-1;
  296. bss_resource.start = virt_to_phys(&__bss_start);
  297. bss_resource.end = virt_to_phys(&__bss_stop)-1;
  298. early_identify_cpu(&boot_cpu_data);
  299. strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
  300. *cmdline_p = command_line;
  301. parse_setup_data();
  302. parse_early_param();
  303. #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
  304. if (init_ohci1394_dma_early)
  305. init_ohci1394_dma_on_all_controllers();
  306. #endif
  307. finish_e820_parsing();
  308. /* after parse_early_param, so could debug it */
  309. insert_resource(&iomem_resource, &code_resource);
  310. insert_resource(&iomem_resource, &data_resource);
  311. insert_resource(&iomem_resource, &bss_resource);
  312. early_gart_iommu_check();
  313. e820_register_active_regions(0, 0, -1UL);
  314. /*
  315. * partially used pages are not usable - thus
  316. * we are rounding upwards:
  317. */
  318. end_pfn = e820_end_of_ram();
  319. /* update e820 for memory not covered by WB MTRRs */
  320. mtrr_bp_init();
  321. if (mtrr_trim_uncached_memory(end_pfn)) {
  322. e820_register_active_regions(0, 0, -1UL);
  323. end_pfn = e820_end_of_ram();
  324. }
  325. num_physpages = end_pfn;
  326. check_efer();
  327. max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
  328. if (efi_enabled)
  329. efi_init();
  330. vsmp_init();
  331. dmi_scan_machine();
  332. io_delay_init();
  333. #ifdef CONFIG_SMP
  334. /* setup to use the early static init tables during kernel startup */
  335. x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
  336. x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
  337. #ifdef CONFIG_NUMA
  338. x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
  339. #endif
  340. #endif
  341. #ifdef CONFIG_ACPI
  342. /*
  343. * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
  344. * Call this early for SRAT node setup.
  345. */
  346. acpi_boot_table_init();
  347. #endif
  348. /* How many end-of-memory variables you have, grandma! */
  349. max_low_pfn = end_pfn;
  350. max_pfn = end_pfn;
  351. high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
  352. /* Remove active ranges so rediscovery with NUMA-awareness happens */
  353. remove_all_active_ranges();
  354. #ifdef CONFIG_ACPI_NUMA
  355. /*
  356. * Parse SRAT to discover nodes.
  357. */
  358. acpi_numa_init();
  359. #endif
  360. #ifdef CONFIG_NUMA
  361. numa_initmem_init(0, end_pfn);
  362. #else
  363. contig_initmem_init(0, end_pfn);
  364. #endif
  365. dma32_reserve_bootmem();
  366. #ifdef CONFIG_ACPI_SLEEP
  367. /*
  368. * Reserve low memory region for sleep support.
  369. */
  370. acpi_reserve_bootmem();
  371. #endif
  372. if (efi_enabled)
  373. efi_reserve_bootmem();
  374. /*
  375. * Find and reserve possible boot-time SMP configuration:
  376. */
  377. find_smp_config();
  378. #ifdef CONFIG_BLK_DEV_INITRD
  379. if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
  380. unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
  381. unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
  382. unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
  383. unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
  384. if (ramdisk_end <= end_of_mem) {
  385. /*
  386. * don't need to reserve again, already reserved early
  387. * in x86_64_start_kernel, and early_res_to_bootmem
  388. * convert that to reserved in bootmem
  389. */
  390. initrd_start = ramdisk_image + PAGE_OFFSET;
  391. initrd_end = initrd_start+ramdisk_size;
  392. } else {
  393. free_bootmem(ramdisk_image, ramdisk_size);
  394. printk(KERN_ERR "initrd extends beyond end of memory "
  395. "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
  396. ramdisk_end, end_of_mem);
  397. initrd_start = 0;
  398. }
  399. }
  400. #endif
  401. reserve_crashkernel();
  402. reserve_ibft_region();
  403. paging_init();
  404. map_vsyscall();
  405. early_quirks();
  406. #ifdef CONFIG_ACPI
  407. /*
  408. * Read APIC and some other early information from ACPI tables.
  409. */
  410. acpi_boot_init();
  411. #endif
  412. init_cpu_to_node();
  413. /*
  414. * get boot-time SMP configuration:
  415. */
  416. if (smp_found_config)
  417. get_smp_config();
  418. init_apic_mappings();
  419. ioapic_init_mappings();
  420. /*
  421. * We trust e820 completely. No explicit ROM probing in memory.
  422. */
  423. e820_reserve_resources();
  424. e820_mark_nosave_regions();
  425. /* request I/O space for devices used on all i[345]86 PCs */
  426. for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
  427. request_resource(&ioport_resource, &standard_io_resources[i]);
  428. e820_setup_gap();
  429. #ifdef CONFIG_VT
  430. #if defined(CONFIG_VGA_CONSOLE)
  431. if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
  432. conswitchp = &vga_con;
  433. #elif defined(CONFIG_DUMMY_CONSOLE)
  434. conswitchp = &dummy_con;
  435. #endif
  436. #endif
  437. }
  438. static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
  439. {
  440. unsigned int *v;
  441. if (c->extended_cpuid_level < 0x80000004)
  442. return 0;
  443. v = (unsigned int *) c->x86_model_id;
  444. cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  445. cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  446. cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  447. c->x86_model_id[48] = 0;
  448. return 1;
  449. }
  450. static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
  451. {
  452. unsigned int n, dummy, eax, ebx, ecx, edx;
  453. n = c->extended_cpuid_level;
  454. if (n >= 0x80000005) {
  455. cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
  456. printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
  457. "D cache %dK (%d bytes/line)\n",
  458. edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
  459. c->x86_cache_size = (ecx>>24) + (edx>>24);
  460. /* On K8 L1 TLB is inclusive, so don't count it */
  461. c->x86_tlbsize = 0;
  462. }
  463. if (n >= 0x80000006) {
  464. cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
  465. ecx = cpuid_ecx(0x80000006);
  466. c->x86_cache_size = ecx >> 16;
  467. c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
  468. printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
  469. c->x86_cache_size, ecx & 0xFF);
  470. }
  471. if (n >= 0x80000008) {
  472. cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
  473. c->x86_virt_bits = (eax >> 8) & 0xff;
  474. c->x86_phys_bits = eax & 0xff;
  475. }
  476. }
  477. #ifdef CONFIG_NUMA
  478. static int __cpuinit nearby_node(int apicid)
  479. {
  480. int i, node;
  481. for (i = apicid - 1; i >= 0; i--) {
  482. node = apicid_to_node[i];
  483. if (node != NUMA_NO_NODE && node_online(node))
  484. return node;
  485. }
  486. for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
  487. node = apicid_to_node[i];
  488. if (node != NUMA_NO_NODE && node_online(node))
  489. return node;
  490. }
  491. return first_node(node_online_map); /* Shouldn't happen */
  492. }
  493. #endif
  494. #ifdef CONFIG_PCI_MMCONFIG
  495. struct pci_hostbridge_probe {
  496. u32 bus;
  497. u32 slot;
  498. u32 vendor;
  499. u32 device;
  500. };
  501. static u64 __cpuinitdata fam10h_pci_mmconf_base;
  502. static int __cpuinitdata fam10h_pci_mmconf_base_status;
  503. static struct pci_hostbridge_probe pci_probes[] __cpuinitdata = {
  504. { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
  505. { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
  506. };
  507. struct range {
  508. u64 start;
  509. u64 end;
  510. };
  511. static int __cpuinit cmp_range(const void *x1, const void *x2)
  512. {
  513. const struct range *r1 = x1;
  514. const struct range *r2 = x2;
  515. int start1, start2;
  516. start1 = r1->start >> 32;
  517. start2 = r2->start >> 32;
  518. return start1 - start2;
  519. }
  520. /*[47:0] */
  521. /* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
  522. #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
  523. #define BASE_VALID(b) ((b != (0xfdULL << 32)) && (b != (0xfeULL << 32)))
  524. static void __cpuinit get_fam10h_pci_mmconf_base(void)
  525. {
  526. int i;
  527. unsigned bus;
  528. unsigned slot;
  529. int found;
  530. u64 val;
  531. u32 address;
  532. u64 tom2;
  533. u64 base = FAM10H_PCI_MMCONF_BASE;
  534. int hi_mmio_num;
  535. struct range range[8];
  536. /* only try to get setting from BSP */
  537. /* -1 or 1 */
  538. if (fam10h_pci_mmconf_base_status)
  539. return;
  540. if (!early_pci_allowed())
  541. goto fail;
  542. found = 0;
  543. for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
  544. u32 id;
  545. u16 device;
  546. u16 vendor;
  547. bus = pci_probes[i].bus;
  548. slot = pci_probes[i].slot;
  549. id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
  550. vendor = id & 0xffff;
  551. device = (id>>16) & 0xffff;
  552. if (pci_probes[i].vendor == vendor &&
  553. pci_probes[i].device == device) {
  554. found = 1;
  555. break;
  556. }
  557. }
  558. if (!found)
  559. goto fail;
  560. /* SYS_CFG */
  561. address = MSR_K8_SYSCFG;
  562. rdmsrl(address, val);
  563. /* TOP_MEM2 is not enabled? */
  564. if (!(val & (1<<21))) {
  565. tom2 = 0;
  566. } else {
  567. /* TOP_MEM2 */
  568. address = MSR_K8_TOP_MEM2;
  569. rdmsrl(address, val);
  570. tom2 = val & (0xffffULL<<32);
  571. }
  572. if (base <= tom2)
  573. base = tom2 + (1ULL<<32);
  574. /*
  575. * need to check if the range is in the high mmio range that is
  576. * above 4G
  577. */
  578. hi_mmio_num = 0;
  579. for (i = 0; i < 8; i++) {
  580. u32 reg;
  581. u64 start;
  582. u64 end;
  583. reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
  584. if (!(reg & 3))
  585. continue;
  586. start = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
  587. reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
  588. end = (((u64)reg) << 8) & (0xffULL << 32); /* 39:16 on 31:8*/
  589. if (!end)
  590. continue;
  591. range[hi_mmio_num].start = start;
  592. range[hi_mmio_num].end = end;
  593. hi_mmio_num++;
  594. }
  595. if (!hi_mmio_num)
  596. goto out;
  597. /* sort the range */
  598. sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
  599. if (range[hi_mmio_num - 1].end < base)
  600. goto out;
  601. if (range[0].start > base)
  602. goto out;
  603. /* need to find one window */
  604. base = range[0].start - (1ULL << 32);
  605. if ((base > tom2) && BASE_VALID(base))
  606. goto out;
  607. base = range[hi_mmio_num - 1].end + (1ULL << 32);
  608. if ((base > tom2) && BASE_VALID(base))
  609. goto out;
  610. /* need to find window between ranges */
  611. if (hi_mmio_num > 1)
  612. for (i = 0; i < hi_mmio_num - 1; i++) {
  613. if (range[i + 1].start > (range[i].end + (1ULL << 32))) {
  614. base = range[i].end + (1ULL << 32);
  615. if ((base > tom2) && BASE_VALID(base))
  616. goto out;
  617. }
  618. }
  619. fail:
  620. fam10h_pci_mmconf_base_status = -1;
  621. return;
  622. out:
  623. fam10h_pci_mmconf_base = base;
  624. fam10h_pci_mmconf_base_status = 1;
  625. }
  626. #endif
  627. static void __cpuinit fam10h_check_enable_mmcfg(struct cpuinfo_x86 *c)
  628. {
  629. #ifdef CONFIG_PCI_MMCONFIG
  630. u64 val;
  631. u32 address;
  632. address = MSR_FAM10H_MMIO_CONF_BASE;
  633. rdmsrl(address, val);
  634. /* try to make sure that AP's setting is identical to BSP setting */
  635. if (val & FAM10H_MMIO_CONF_ENABLE) {
  636. u64 base;
  637. base = val & (0xffffULL << 32);
  638. if (fam10h_pci_mmconf_base_status <= 0) {
  639. fam10h_pci_mmconf_base = base;
  640. fam10h_pci_mmconf_base_status = 1;
  641. return;
  642. } else if (fam10h_pci_mmconf_base == base)
  643. return;
  644. }
  645. /*
  646. * if it is not enabled, try to enable it and assume only one segment
  647. * with 256 buses
  648. */
  649. get_fam10h_pci_mmconf_base();
  650. if (fam10h_pci_mmconf_base_status <= 0)
  651. return;
  652. printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
  653. val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
  654. (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
  655. val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
  656. FAM10H_MMIO_CONF_ENABLE;
  657. wrmsrl(address, val);
  658. #endif
  659. }
  660. /*
  661. * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  662. * Assumes number of cores is a power of two.
  663. */
  664. static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
  665. {
  666. #ifdef CONFIG_SMP
  667. unsigned bits;
  668. #ifdef CONFIG_NUMA
  669. int cpu = smp_processor_id();
  670. int node = 0;
  671. unsigned apicid = hard_smp_processor_id();
  672. #endif
  673. bits = c->x86_coreid_bits;
  674. /* Low order bits define the core id (index of core in socket) */
  675. c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
  676. /* Convert the initial APIC ID into the socket ID */
  677. c->phys_proc_id = c->initial_apicid >> bits;
  678. #ifdef CONFIG_NUMA
  679. node = c->phys_proc_id;
  680. if (apicid_to_node[apicid] != NUMA_NO_NODE)
  681. node = apicid_to_node[apicid];
  682. if (!node_online(node)) {
  683. /* Two possibilities here:
  684. - The CPU is missing memory and no node was created.
  685. In that case try picking one from a nearby CPU
  686. - The APIC IDs differ from the HyperTransport node IDs
  687. which the K8 northbridge parsing fills in.
  688. Assume they are all increased by a constant offset,
  689. but in the same order as the HT nodeids.
  690. If that doesn't result in a usable node fall back to the
  691. path for the previous case. */
  692. int ht_nodeid = c->initial_apicid;
  693. if (ht_nodeid >= 0 &&
  694. apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
  695. node = apicid_to_node[ht_nodeid];
  696. /* Pick a nearby node */
  697. if (!node_online(node))
  698. node = nearby_node(apicid);
  699. }
  700. numa_set_node(cpu, node);
  701. printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
  702. #endif
  703. #endif
  704. }
  705. static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
  706. {
  707. #ifdef CONFIG_SMP
  708. unsigned bits, ecx;
  709. /* Multi core CPU? */
  710. if (c->extended_cpuid_level < 0x80000008)
  711. return;
  712. ecx = cpuid_ecx(0x80000008);
  713. c->x86_max_cores = (ecx & 0xff) + 1;
  714. /* CPU telling us the core id bits shift? */
  715. bits = (ecx >> 12) & 0xF;
  716. /* Otherwise recompute */
  717. if (bits == 0) {
  718. while ((1 << bits) < c->x86_max_cores)
  719. bits++;
  720. }
  721. c->x86_coreid_bits = bits;
  722. #endif
  723. }
  724. #define ENABLE_C1E_MASK 0x18000000
  725. #define CPUID_PROCESSOR_SIGNATURE 1
  726. #define CPUID_XFAM 0x0ff00000
  727. #define CPUID_XFAM_K8 0x00000000
  728. #define CPUID_XFAM_10H 0x00100000
  729. #define CPUID_XFAM_11H 0x00200000
  730. #define CPUID_XMOD 0x000f0000
  731. #define CPUID_XMOD_REV_F 0x00040000
  732. /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
  733. static __cpuinit int amd_apic_timer_broken(void)
  734. {
  735. u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
  736. switch (eax & CPUID_XFAM) {
  737. case CPUID_XFAM_K8:
  738. if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
  739. break;
  740. case CPUID_XFAM_10H:
  741. case CPUID_XFAM_11H:
  742. rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
  743. if (lo & ENABLE_C1E_MASK)
  744. return 1;
  745. break;
  746. default:
  747. /* err on the side of caution */
  748. return 1;
  749. }
  750. return 0;
  751. }
  752. static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  753. {
  754. early_init_amd_mc(c);
  755. /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
  756. if (c->x86_power & (1<<8))
  757. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  758. }
  759. static void __cpuinit init_amd(struct cpuinfo_x86 *c)
  760. {
  761. unsigned level;
  762. #ifdef CONFIG_SMP
  763. unsigned long value;
  764. /*
  765. * Disable TLB flush filter by setting HWCR.FFDIS on K8
  766. * bit 6 of msr C001_0015
  767. *
  768. * Errata 63 for SH-B3 steppings
  769. * Errata 122 for all steppings (F+ have it disabled by default)
  770. */
  771. if (c->x86 == 15) {
  772. rdmsrl(MSR_K8_HWCR, value);
  773. value |= 1 << 6;
  774. wrmsrl(MSR_K8_HWCR, value);
  775. }
  776. #endif
  777. /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  778. 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  779. clear_cpu_cap(c, 0*32+31);
  780. /* On C+ stepping K8 rep microcode works well for copy/memset */
  781. level = cpuid_eax(1);
  782. if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
  783. level >= 0x0f58))
  784. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  785. if (c->x86 == 0x10 || c->x86 == 0x11)
  786. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  787. /* Enable workaround for FXSAVE leak */
  788. if (c->x86 >= 6)
  789. set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
  790. level = get_model_name(c);
  791. if (!level) {
  792. switch (c->x86) {
  793. case 15:
  794. /* Should distinguish Models here, but this is only
  795. a fallback anyways. */
  796. strcpy(c->x86_model_id, "Hammer");
  797. break;
  798. }
  799. }
  800. display_cacheinfo(c);
  801. /* Multi core CPU? */
  802. if (c->extended_cpuid_level >= 0x80000008)
  803. amd_detect_cmp(c);
  804. if (c->extended_cpuid_level >= 0x80000006 &&
  805. (cpuid_edx(0x80000006) & 0xf000))
  806. num_cache_leaves = 4;
  807. else
  808. num_cache_leaves = 3;
  809. if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
  810. set_cpu_cap(c, X86_FEATURE_K8);
  811. /* MFENCE stops RDTSC speculation */
  812. set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
  813. if (c->x86 == 0x10)
  814. fam10h_check_enable_mmcfg(c);
  815. if (amd_apic_timer_broken())
  816. disable_apic_timer = 1;
  817. if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
  818. unsigned long long tseg;
  819. /*
  820. * Split up direct mapping around the TSEG SMM area.
  821. * Don't do it for gbpages because there seems very little
  822. * benefit in doing so.
  823. */
  824. if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
  825. (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
  826. set_memory_4k((unsigned long)__va(tseg), 1);
  827. }
  828. }
  829. void __cpuinit detect_ht(struct cpuinfo_x86 *c)
  830. {
  831. #ifdef CONFIG_SMP
  832. u32 eax, ebx, ecx, edx;
  833. int index_msb, core_bits;
  834. cpuid(1, &eax, &ebx, &ecx, &edx);
  835. if (!cpu_has(c, X86_FEATURE_HT))
  836. return;
  837. if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
  838. goto out;
  839. smp_num_siblings = (ebx & 0xff0000) >> 16;
  840. if (smp_num_siblings == 1) {
  841. printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
  842. } else if (smp_num_siblings > 1) {
  843. if (smp_num_siblings > NR_CPUS) {
  844. printk(KERN_WARNING "CPU: Unsupported number of "
  845. "siblings %d", smp_num_siblings);
  846. smp_num_siblings = 1;
  847. return;
  848. }
  849. index_msb = get_count_order(smp_num_siblings);
  850. c->phys_proc_id = phys_pkg_id(index_msb);
  851. smp_num_siblings = smp_num_siblings / c->x86_max_cores;
  852. index_msb = get_count_order(smp_num_siblings);
  853. core_bits = get_count_order(c->x86_max_cores);
  854. c->cpu_core_id = phys_pkg_id(index_msb) &
  855. ((1 << core_bits) - 1);
  856. }
  857. out:
  858. if ((c->x86_max_cores * smp_num_siblings) > 1) {
  859. printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
  860. c->phys_proc_id);
  861. printk(KERN_INFO "CPU: Processor Core ID: %d\n",
  862. c->cpu_core_id);
  863. }
  864. #endif
  865. }
  866. /*
  867. * find out the number of processor cores on the die
  868. */
  869. static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
  870. {
  871. unsigned int eax, t;
  872. if (c->cpuid_level < 4)
  873. return 1;
  874. cpuid_count(4, 0, &eax, &t, &t, &t);
  875. if (eax & 0x1f)
  876. return ((eax >> 26) + 1);
  877. else
  878. return 1;
  879. }
  880. static void __cpuinit srat_detect_node(void)
  881. {
  882. #ifdef CONFIG_NUMA
  883. unsigned node;
  884. int cpu = smp_processor_id();
  885. int apicid = hard_smp_processor_id();
  886. /* Don't do the funky fallback heuristics the AMD version employs
  887. for now. */
  888. node = apicid_to_node[apicid];
  889. if (node == NUMA_NO_NODE || !node_online(node))
  890. node = first_node(node_online_map);
  891. numa_set_node(cpu, node);
  892. printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
  893. #endif
  894. }
  895. static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  896. {
  897. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  898. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  899. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  900. }
  901. static void __cpuinit init_intel(struct cpuinfo_x86 *c)
  902. {
  903. /* Cache sizes */
  904. unsigned n;
  905. init_intel_cacheinfo(c);
  906. if (c->cpuid_level > 9) {
  907. unsigned eax = cpuid_eax(10);
  908. /* Check for version and the number of counters */
  909. if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
  910. set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
  911. }
  912. if (cpu_has_ds) {
  913. unsigned int l1, l2;
  914. rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
  915. if (!(l1 & (1<<11)))
  916. set_cpu_cap(c, X86_FEATURE_BTS);
  917. if (!(l1 & (1<<12)))
  918. set_cpu_cap(c, X86_FEATURE_PEBS);
  919. }
  920. if (cpu_has_bts)
  921. ds_init_intel(c);
  922. n = c->extended_cpuid_level;
  923. if (n >= 0x80000008) {
  924. unsigned eax = cpuid_eax(0x80000008);
  925. c->x86_virt_bits = (eax >> 8) & 0xff;
  926. c->x86_phys_bits = eax & 0xff;
  927. /* CPUID workaround for Intel 0F34 CPU */
  928. if (c->x86_vendor == X86_VENDOR_INTEL &&
  929. c->x86 == 0xF && c->x86_model == 0x3 &&
  930. c->x86_mask == 0x4)
  931. c->x86_phys_bits = 36;
  932. }
  933. if (c->x86 == 15)
  934. c->x86_cache_alignment = c->x86_clflush_size * 2;
  935. if (c->x86 == 6)
  936. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  937. set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
  938. c->x86_max_cores = intel_num_cpu_cores(c);
  939. srat_detect_node();
  940. }
  941. static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
  942. {
  943. if (c->x86 == 0x6 && c->x86_model >= 0xf)
  944. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  945. }
  946. static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
  947. {
  948. /* Cache sizes */
  949. unsigned n;
  950. n = c->extended_cpuid_level;
  951. if (n >= 0x80000008) {
  952. unsigned eax = cpuid_eax(0x80000008);
  953. c->x86_virt_bits = (eax >> 8) & 0xff;
  954. c->x86_phys_bits = eax & 0xff;
  955. }
  956. if (c->x86 == 0x6 && c->x86_model >= 0xf) {
  957. c->x86_cache_alignment = c->x86_clflush_size * 2;
  958. set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  959. set_cpu_cap(c, X86_FEATURE_REP_GOOD);
  960. }
  961. set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
  962. }
  963. static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
  964. {
  965. char *v = c->x86_vendor_id;
  966. if (!strcmp(v, "AuthenticAMD"))
  967. c->x86_vendor = X86_VENDOR_AMD;
  968. else if (!strcmp(v, "GenuineIntel"))
  969. c->x86_vendor = X86_VENDOR_INTEL;
  970. else if (!strcmp(v, "CentaurHauls"))
  971. c->x86_vendor = X86_VENDOR_CENTAUR;
  972. else
  973. c->x86_vendor = X86_VENDOR_UNKNOWN;
  974. }
  975. /* Do some early cpuid on the boot CPU to get some parameter that are
  976. needed before check_bugs. Everything advanced is in identify_cpu
  977. below. */
  978. static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
  979. {
  980. u32 tfms, xlvl;
  981. c->loops_per_jiffy = loops_per_jiffy;
  982. c->x86_cache_size = -1;
  983. c->x86_vendor = X86_VENDOR_UNKNOWN;
  984. c->x86_model = c->x86_mask = 0; /* So far unknown... */
  985. c->x86_vendor_id[0] = '\0'; /* Unset */
  986. c->x86_model_id[0] = '\0'; /* Unset */
  987. c->x86_clflush_size = 64;
  988. c->x86_cache_alignment = c->x86_clflush_size;
  989. c->x86_max_cores = 1;
  990. c->x86_coreid_bits = 0;
  991. c->extended_cpuid_level = 0;
  992. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  993. /* Get vendor name */
  994. cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
  995. (unsigned int *)&c->x86_vendor_id[0],
  996. (unsigned int *)&c->x86_vendor_id[8],
  997. (unsigned int *)&c->x86_vendor_id[4]);
  998. get_cpu_vendor(c);
  999. /* Initialize the standard set of capabilities */
  1000. /* Note that the vendor-specific code below might override */
  1001. /* Intel-defined flags: level 0x00000001 */
  1002. if (c->cpuid_level >= 0x00000001) {
  1003. __u32 misc;
  1004. cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
  1005. &c->x86_capability[0]);
  1006. c->x86 = (tfms >> 8) & 0xf;
  1007. c->x86_model = (tfms >> 4) & 0xf;
  1008. c->x86_mask = tfms & 0xf;
  1009. if (c->x86 == 0xf)
  1010. c->x86 += (tfms >> 20) & 0xff;
  1011. if (c->x86 >= 0x6)
  1012. c->x86_model += ((tfms >> 16) & 0xF) << 4;
  1013. if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
  1014. c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
  1015. } else {
  1016. /* Have CPUID level 0 only - unheard of */
  1017. c->x86 = 4;
  1018. }
  1019. c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
  1020. #ifdef CONFIG_SMP
  1021. c->phys_proc_id = c->initial_apicid;
  1022. #endif
  1023. /* AMD-defined flags: level 0x80000001 */
  1024. xlvl = cpuid_eax(0x80000000);
  1025. c->extended_cpuid_level = xlvl;
  1026. if ((xlvl & 0xffff0000) == 0x80000000) {
  1027. if (xlvl >= 0x80000001) {
  1028. c->x86_capability[1] = cpuid_edx(0x80000001);
  1029. c->x86_capability[6] = cpuid_ecx(0x80000001);
  1030. }
  1031. if (xlvl >= 0x80000004)
  1032. get_model_name(c); /* Default name */
  1033. }
  1034. /* Transmeta-defined flags: level 0x80860001 */
  1035. xlvl = cpuid_eax(0x80860000);
  1036. if ((xlvl & 0xffff0000) == 0x80860000) {
  1037. /* Don't set x86_cpuid_level here for now to not confuse. */
  1038. if (xlvl >= 0x80860001)
  1039. c->x86_capability[2] = cpuid_edx(0x80860001);
  1040. }
  1041. c->extended_cpuid_level = cpuid_eax(0x80000000);
  1042. if (c->extended_cpuid_level >= 0x80000007)
  1043. c->x86_power = cpuid_edx(0x80000007);
  1044. clear_cpu_cap(c, X86_FEATURE_PAT);
  1045. switch (c->x86_vendor) {
  1046. case X86_VENDOR_AMD:
  1047. early_init_amd(c);
  1048. if (c->x86 >= 0xf && c->x86 <= 0x11)
  1049. set_cpu_cap(c, X86_FEATURE_PAT);
  1050. break;
  1051. case X86_VENDOR_INTEL:
  1052. early_init_intel(c);
  1053. if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
  1054. set_cpu_cap(c, X86_FEATURE_PAT);
  1055. break;
  1056. case X86_VENDOR_CENTAUR:
  1057. early_init_centaur(c);
  1058. break;
  1059. }
  1060. }
  1061. /*
  1062. * This does the hard work of actually picking apart the CPU stuff...
  1063. */
  1064. void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
  1065. {
  1066. int i;
  1067. early_identify_cpu(c);
  1068. init_scattered_cpuid_features(c);
  1069. c->apicid = phys_pkg_id(0);
  1070. /*
  1071. * Vendor-specific initialization. In this section we
  1072. * canonicalize the feature flags, meaning if there are
  1073. * features a certain CPU supports which CPUID doesn't
  1074. * tell us, CPUID claiming incorrect flags, or other bugs,
  1075. * we handle them here.
  1076. *
  1077. * At the end of this section, c->x86_capability better
  1078. * indicate the features this CPU genuinely supports!
  1079. */
  1080. switch (c->x86_vendor) {
  1081. case X86_VENDOR_AMD:
  1082. init_amd(c);
  1083. break;
  1084. case X86_VENDOR_INTEL:
  1085. init_intel(c);
  1086. break;
  1087. case X86_VENDOR_CENTAUR:
  1088. init_centaur(c);
  1089. break;
  1090. case X86_VENDOR_UNKNOWN:
  1091. default:
  1092. display_cacheinfo(c);
  1093. break;
  1094. }
  1095. detect_ht(c);
  1096. /*
  1097. * On SMP, boot_cpu_data holds the common feature set between
  1098. * all CPUs; so make sure that we indicate which features are
  1099. * common between the CPUs. The first time this routine gets
  1100. * executed, c == &boot_cpu_data.
  1101. */
  1102. if (c != &boot_cpu_data) {
  1103. /* AND the already accumulated flags with these */
  1104. for (i = 0; i < NCAPINTS; i++)
  1105. boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
  1106. }
  1107. /* Clear all flags overriden by options */
  1108. for (i = 0; i < NCAPINTS; i++)
  1109. c->x86_capability[i] &= ~cleared_cpu_caps[i];
  1110. #ifdef CONFIG_X86_MCE
  1111. mcheck_init(c);
  1112. #endif
  1113. select_idle_routine(c);
  1114. #ifdef CONFIG_NUMA
  1115. numa_add_cpu(smp_processor_id());
  1116. #endif
  1117. }
  1118. void __cpuinit identify_boot_cpu(void)
  1119. {
  1120. identify_cpu(&boot_cpu_data);
  1121. }
  1122. void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
  1123. {
  1124. BUG_ON(c == &boot_cpu_data);
  1125. identify_cpu(c);
  1126. mtrr_ap_init();
  1127. }
  1128. static __init int setup_noclflush(char *arg)
  1129. {
  1130. setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
  1131. return 1;
  1132. }
  1133. __setup("noclflush", setup_noclflush);
  1134. void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
  1135. {
  1136. if (c->x86_model_id[0])
  1137. printk(KERN_CONT "%s", c->x86_model_id);
  1138. if (c->x86_mask || c->cpuid_level >= 0)
  1139. printk(KERN_CONT " stepping %02x\n", c->x86_mask);
  1140. else
  1141. printk(KERN_CONT "\n");
  1142. }
  1143. static __init int setup_disablecpuid(char *arg)
  1144. {
  1145. int bit;
  1146. if (get_option(&arg, &bit) && bit < NCAPINTS*32)
  1147. setup_clear_cpu_cap(bit);
  1148. else
  1149. return 0;
  1150. return 1;
  1151. }
  1152. __setup("clearcpuid=", setup_disablecpuid);