i915_drv.c 17 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34. #include "intel_drv.h"
  35. #include <linux/console.h>
  36. #include "drm_crtc_helper.h"
  37. static int i915_modeset = -1;
  38. module_param_named(modeset, i915_modeset, int, 0400);
  39. unsigned int i915_fbpercrtc = 0;
  40. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  41. unsigned int i915_powersave = 1;
  42. module_param_named(powersave, i915_powersave, int, 0400);
  43. unsigned int i915_lvds_downclock = 0;
  44. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  45. static struct drm_driver driver;
  46. extern int intel_agp_enabled;
  47. #define INTEL_VGA_DEVICE(id, info) { \
  48. .class = PCI_CLASS_DISPLAY_VGA << 8, \
  49. .class_mask = 0xffff00, \
  50. .vendor = 0x8086, \
  51. .device = id, \
  52. .subvendor = PCI_ANY_ID, \
  53. .subdevice = PCI_ANY_ID, \
  54. .driver_data = (unsigned long) info }
  55. static const struct intel_device_info intel_i830_info = {
  56. .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  57. .has_overlay = 1, .overlay_needs_physical = 1,
  58. };
  59. static const struct intel_device_info intel_845g_info = {
  60. .gen = 2,
  61. .has_overlay = 1, .overlay_needs_physical = 1,
  62. };
  63. static const struct intel_device_info intel_i85x_info = {
  64. .gen = 2, .is_i85x = 1, .is_mobile = 1,
  65. .cursor_needs_physical = 1,
  66. .has_overlay = 1, .overlay_needs_physical = 1,
  67. };
  68. static const struct intel_device_info intel_i865g_info = {
  69. .gen = 2,
  70. .has_overlay = 1, .overlay_needs_physical = 1,
  71. };
  72. static const struct intel_device_info intel_i915g_info = {
  73. .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  74. .has_overlay = 1, .overlay_needs_physical = 1,
  75. };
  76. static const struct intel_device_info intel_i915gm_info = {
  77. .gen = 3, .is_mobile = 1,
  78. .cursor_needs_physical = 1,
  79. .has_overlay = 1, .overlay_needs_physical = 1,
  80. .supports_tv = 1,
  81. };
  82. static const struct intel_device_info intel_i945g_info = {
  83. .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  84. .has_overlay = 1, .overlay_needs_physical = 1,
  85. };
  86. static const struct intel_device_info intel_i945gm_info = {
  87. .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  88. .has_hotplug = 1, .cursor_needs_physical = 1,
  89. .has_overlay = 1, .overlay_needs_physical = 1,
  90. .supports_tv = 1,
  91. };
  92. static const struct intel_device_info intel_i965g_info = {
  93. .gen = 4, .is_broadwater = 1,
  94. .has_hotplug = 1,
  95. .has_overlay = 1,
  96. };
  97. static const struct intel_device_info intel_i965gm_info = {
  98. .gen = 4, .is_crestline = 1,
  99. .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
  100. .has_overlay = 1,
  101. .supports_tv = 1,
  102. };
  103. static const struct intel_device_info intel_g33_info = {
  104. .gen = 3, .is_g33 = 1,
  105. .need_gfx_hws = 1, .has_hotplug = 1,
  106. .has_overlay = 1,
  107. };
  108. static const struct intel_device_info intel_g45_info = {
  109. .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  110. .has_pipe_cxsr = 1, .has_hotplug = 1,
  111. };
  112. static const struct intel_device_info intel_gm45_info = {
  113. .gen = 4, .is_g4x = 1,
  114. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
  115. .has_pipe_cxsr = 1, .has_hotplug = 1,
  116. .supports_tv = 1,
  117. };
  118. static const struct intel_device_info intel_pineview_info = {
  119. .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  120. .need_gfx_hws = 1, .has_hotplug = 1,
  121. .has_overlay = 1,
  122. };
  123. static const struct intel_device_info intel_ironlake_d_info = {
  124. .gen = 5, .is_ironlake = 1,
  125. .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
  126. };
  127. static const struct intel_device_info intel_ironlake_m_info = {
  128. .gen = 5, .is_ironlake = 1, .is_mobile = 1,
  129. .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
  130. };
  131. static const struct intel_device_info intel_sandybridge_d_info = {
  132. .gen = 6,
  133. .need_gfx_hws = 1, .has_hotplug = 1,
  134. };
  135. static const struct intel_device_info intel_sandybridge_m_info = {
  136. .gen = 6, .is_mobile = 1,
  137. .need_gfx_hws = 1, .has_hotplug = 1,
  138. };
  139. static const struct pci_device_id pciidlist[] = { /* aka */
  140. INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
  141. INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
  142. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
  143. INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
  144. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
  145. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
  146. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
  147. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
  148. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
  149. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
  150. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
  151. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
  152. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
  153. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
  154. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
  155. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
  156. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
  157. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
  158. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
  159. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
  160. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
  161. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
  162. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
  163. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
  164. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
  165. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
  166. INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
  167. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  168. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  169. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  170. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  171. INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  172. INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  173. INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  174. INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  175. INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  176. INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  177. INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  178. {0, 0, 0}
  179. };
  180. #if defined(CONFIG_DRM_I915_KMS)
  181. MODULE_DEVICE_TABLE(pci, pciidlist);
  182. #endif
  183. #define INTEL_PCH_DEVICE_ID_MASK 0xff00
  184. #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
  185. void intel_detect_pch (struct drm_device *dev)
  186. {
  187. struct drm_i915_private *dev_priv = dev->dev_private;
  188. struct pci_dev *pch;
  189. /*
  190. * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  191. * make graphics device passthrough work easy for VMM, that only
  192. * need to expose ISA bridge to let driver know the real hardware
  193. * underneath. This is a requirement from virtualization team.
  194. */
  195. pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  196. if (pch) {
  197. if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  198. int id;
  199. id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  200. if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  201. dev_priv->pch_type = PCH_CPT;
  202. DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  203. }
  204. }
  205. pci_dev_put(pch);
  206. }
  207. }
  208. static int i915_drm_freeze(struct drm_device *dev)
  209. {
  210. struct drm_i915_private *dev_priv = dev->dev_private;
  211. pci_save_state(dev->pdev);
  212. /* If KMS is active, we do the leavevt stuff here */
  213. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  214. int error = i915_gem_idle(dev);
  215. if (error) {
  216. dev_err(&dev->pdev->dev,
  217. "GEM idle failed, resume might fail\n");
  218. return error;
  219. }
  220. drm_irq_uninstall(dev);
  221. }
  222. i915_save_state(dev);
  223. intel_opregion_fini(dev);
  224. /* Modeset on resume, not lid events */
  225. dev_priv->modeset_on_lid = 0;
  226. return 0;
  227. }
  228. int i915_suspend(struct drm_device *dev, pm_message_t state)
  229. {
  230. int error;
  231. if (!dev || !dev->dev_private) {
  232. DRM_ERROR("dev: %p\n", dev);
  233. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  234. return -ENODEV;
  235. }
  236. if (state.event == PM_EVENT_PRETHAW)
  237. return 0;
  238. error = i915_drm_freeze(dev);
  239. if (error)
  240. return error;
  241. if (state.event == PM_EVENT_SUSPEND) {
  242. /* Shut down the device */
  243. pci_disable_device(dev->pdev);
  244. pci_set_power_state(dev->pdev, PCI_D3hot);
  245. }
  246. return 0;
  247. }
  248. static int i915_drm_thaw(struct drm_device *dev)
  249. {
  250. struct drm_i915_private *dev_priv = dev->dev_private;
  251. int error = 0;
  252. i915_restore_state(dev);
  253. intel_opregion_setup(dev);
  254. /* KMS EnterVT equivalent */
  255. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  256. mutex_lock(&dev->struct_mutex);
  257. dev_priv->mm.suspended = 0;
  258. error = i915_gem_init_ringbuffer(dev);
  259. mutex_unlock(&dev->struct_mutex);
  260. drm_irq_install(dev);
  261. /* Resume the modeset for every activated CRTC */
  262. drm_helper_resume_force_mode(dev);
  263. }
  264. intel_opregion_init(dev);
  265. dev_priv->modeset_on_lid = 0;
  266. return error;
  267. }
  268. int i915_resume(struct drm_device *dev)
  269. {
  270. if (pci_enable_device(dev->pdev))
  271. return -EIO;
  272. pci_set_master(dev->pdev);
  273. return i915_drm_thaw(dev);
  274. }
  275. static int i965_reset_complete(struct drm_device *dev)
  276. {
  277. u8 gdrst;
  278. pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
  279. return gdrst & 0x1;
  280. }
  281. /**
  282. * i965_reset - reset chip after a hang
  283. * @dev: drm device to reset
  284. * @flags: reset domains
  285. *
  286. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  287. * reset or otherwise an error code.
  288. *
  289. * Procedure is fairly simple:
  290. * - reset the chip using the reset reg
  291. * - re-init context state
  292. * - re-init hardware status page
  293. * - re-init ring buffer
  294. * - re-init interrupt state
  295. * - re-init display
  296. */
  297. int i965_reset(struct drm_device *dev, u8 flags)
  298. {
  299. drm_i915_private_t *dev_priv = dev->dev_private;
  300. u8 gdrst;
  301. /*
  302. * We really should only reset the display subsystem if we actually
  303. * need to
  304. */
  305. bool need_display = true;
  306. mutex_lock(&dev->struct_mutex);
  307. /*
  308. * Clear request list
  309. */
  310. i915_gem_retire_requests(dev);
  311. if (need_display)
  312. i915_save_display(dev);
  313. /*
  314. * Set the domains we want to reset (GRDOM/bits 2 and 3) as
  315. * well as the reset bit (GR/bit 0). Setting the GR bit
  316. * triggers the reset; when done, the hardware will clear it.
  317. */
  318. pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
  319. pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
  320. /* Wait for the hardware to reset (but no more than 500 ms) */
  321. if (wait_for(i965_reset_complete(dev), 500)) {
  322. WARN(true, "i915: Failed to reset chip\n");
  323. mutex_unlock(&dev->struct_mutex);
  324. return -EIO;
  325. }
  326. /* Ok, now get things going again... */
  327. /*
  328. * Everything depends on having the GTT running, so we need to start
  329. * there. Fortunately we don't need to do this unless we reset the
  330. * chip at a PCI level.
  331. *
  332. * Next we need to restore the context, but we don't use those
  333. * yet either...
  334. *
  335. * Ring buffer needs to be re-initialized in the KMS case, or if X
  336. * was running at the time of the reset (i.e. we weren't VT
  337. * switched away).
  338. */
  339. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  340. !dev_priv->mm.suspended) {
  341. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  342. dev_priv->mm.suspended = 0;
  343. ring->init(dev, ring);
  344. mutex_unlock(&dev->struct_mutex);
  345. drm_irq_uninstall(dev);
  346. drm_irq_install(dev);
  347. mutex_lock(&dev->struct_mutex);
  348. }
  349. /*
  350. * Display needs restore too...
  351. */
  352. if (need_display)
  353. i915_restore_display(dev);
  354. mutex_unlock(&dev->struct_mutex);
  355. return 0;
  356. }
  357. static int __devinit
  358. i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  359. {
  360. return drm_get_pci_dev(pdev, ent, &driver);
  361. }
  362. static void
  363. i915_pci_remove(struct pci_dev *pdev)
  364. {
  365. struct drm_device *dev = pci_get_drvdata(pdev);
  366. drm_put_dev(dev);
  367. }
  368. static int i915_pm_suspend(struct device *dev)
  369. {
  370. struct pci_dev *pdev = to_pci_dev(dev);
  371. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  372. int error;
  373. if (!drm_dev || !drm_dev->dev_private) {
  374. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  375. return -ENODEV;
  376. }
  377. error = i915_drm_freeze(drm_dev);
  378. if (error)
  379. return error;
  380. pci_disable_device(pdev);
  381. pci_set_power_state(pdev, PCI_D3hot);
  382. return 0;
  383. }
  384. static int i915_pm_resume(struct device *dev)
  385. {
  386. struct pci_dev *pdev = to_pci_dev(dev);
  387. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  388. return i915_resume(drm_dev);
  389. }
  390. static int i915_pm_freeze(struct device *dev)
  391. {
  392. struct pci_dev *pdev = to_pci_dev(dev);
  393. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  394. if (!drm_dev || !drm_dev->dev_private) {
  395. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  396. return -ENODEV;
  397. }
  398. return i915_drm_freeze(drm_dev);
  399. }
  400. static int i915_pm_thaw(struct device *dev)
  401. {
  402. struct pci_dev *pdev = to_pci_dev(dev);
  403. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  404. return i915_drm_thaw(drm_dev);
  405. }
  406. static int i915_pm_poweroff(struct device *dev)
  407. {
  408. struct pci_dev *pdev = to_pci_dev(dev);
  409. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  410. return i915_drm_freeze(drm_dev);
  411. }
  412. static const struct dev_pm_ops i915_pm_ops = {
  413. .suspend = i915_pm_suspend,
  414. .resume = i915_pm_resume,
  415. .freeze = i915_pm_freeze,
  416. .thaw = i915_pm_thaw,
  417. .poweroff = i915_pm_poweroff,
  418. .restore = i915_pm_resume,
  419. };
  420. static struct vm_operations_struct i915_gem_vm_ops = {
  421. .fault = i915_gem_fault,
  422. .open = drm_gem_vm_open,
  423. .close = drm_gem_vm_close,
  424. };
  425. static struct drm_driver driver = {
  426. /* don't use mtrr's here, the Xserver or user space app should
  427. * deal with them for intel hardware.
  428. */
  429. .driver_features =
  430. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  431. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  432. .load = i915_driver_load,
  433. .unload = i915_driver_unload,
  434. .open = i915_driver_open,
  435. .lastclose = i915_driver_lastclose,
  436. .preclose = i915_driver_preclose,
  437. .postclose = i915_driver_postclose,
  438. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  439. .suspend = i915_suspend,
  440. .resume = i915_resume,
  441. .device_is_agp = i915_driver_device_is_agp,
  442. .enable_vblank = i915_enable_vblank,
  443. .disable_vblank = i915_disable_vblank,
  444. .irq_preinstall = i915_driver_irq_preinstall,
  445. .irq_postinstall = i915_driver_irq_postinstall,
  446. .irq_uninstall = i915_driver_irq_uninstall,
  447. .irq_handler = i915_driver_irq_handler,
  448. .reclaim_buffers = drm_core_reclaim_buffers,
  449. .master_create = i915_master_create,
  450. .master_destroy = i915_master_destroy,
  451. #if defined(CONFIG_DEBUG_FS)
  452. .debugfs_init = i915_debugfs_init,
  453. .debugfs_cleanup = i915_debugfs_cleanup,
  454. #endif
  455. .gem_init_object = i915_gem_init_object,
  456. .gem_free_object = i915_gem_free_object,
  457. .gem_vm_ops = &i915_gem_vm_ops,
  458. .ioctls = i915_ioctls,
  459. .fops = {
  460. .owner = THIS_MODULE,
  461. .open = drm_open,
  462. .release = drm_release,
  463. .unlocked_ioctl = drm_ioctl,
  464. .mmap = drm_gem_mmap,
  465. .poll = drm_poll,
  466. .fasync = drm_fasync,
  467. .read = drm_read,
  468. #ifdef CONFIG_COMPAT
  469. .compat_ioctl = i915_compat_ioctl,
  470. #endif
  471. },
  472. .pci_driver = {
  473. .name = DRIVER_NAME,
  474. .id_table = pciidlist,
  475. .probe = i915_pci_probe,
  476. .remove = i915_pci_remove,
  477. .driver.pm = &i915_pm_ops,
  478. },
  479. .name = DRIVER_NAME,
  480. .desc = DRIVER_DESC,
  481. .date = DRIVER_DATE,
  482. .major = DRIVER_MAJOR,
  483. .minor = DRIVER_MINOR,
  484. .patchlevel = DRIVER_PATCHLEVEL,
  485. };
  486. static int __init i915_init(void)
  487. {
  488. if (!intel_agp_enabled) {
  489. DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  490. return -ENODEV;
  491. }
  492. driver.num_ioctls = i915_max_ioctl;
  493. i915_gem_shrinker_init();
  494. /*
  495. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  496. * explicitly disabled with the module pararmeter.
  497. *
  498. * Otherwise, just follow the parameter (defaulting to off).
  499. *
  500. * Allow optional vga_text_mode_force boot option to override
  501. * the default behavior.
  502. */
  503. #if defined(CONFIG_DRM_I915_KMS)
  504. if (i915_modeset != 0)
  505. driver.driver_features |= DRIVER_MODESET;
  506. #endif
  507. if (i915_modeset == 1)
  508. driver.driver_features |= DRIVER_MODESET;
  509. #ifdef CONFIG_VGA_CONSOLE
  510. if (vgacon_text_force() && i915_modeset == -1)
  511. driver.driver_features &= ~DRIVER_MODESET;
  512. #endif
  513. if (!(driver.driver_features & DRIVER_MODESET)) {
  514. driver.suspend = i915_suspend;
  515. driver.resume = i915_resume;
  516. }
  517. return drm_init(&driver);
  518. }
  519. static void __exit i915_exit(void)
  520. {
  521. i915_gem_shrinker_exit();
  522. drm_exit(&driver);
  523. }
  524. module_init(i915_init);
  525. module_exit(i915_exit);
  526. MODULE_AUTHOR(DRIVER_AUTHOR);
  527. MODULE_DESCRIPTION(DRIVER_DESC);
  528. MODULE_LICENSE("GPL and additional rights");