entry.S 11 KB

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  1. /*
  2. * arch/sh/kernel/cpu/sh3/entry.S
  3. *
  4. * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
  5. * Copyright (C) 2003 - 2006 Paul Mundt
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/sys.h>
  12. #include <linux/errno.h>
  13. #include <linux/linkage.h>
  14. #include <asm/asm-offsets.h>
  15. #include <asm/thread_info.h>
  16. #include <asm/unistd.h>
  17. #include <cpu/mmu_context.h>
  18. #include <asm/page.h>
  19. #include <asm/cache.h>
  20. ! NOTE:
  21. ! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
  22. ! to be jumped is too far, but it causes illegal slot exception.
  23. /*
  24. * entry.S contains the system-call and fault low-level handling routines.
  25. * This also contains the timer-interrupt handler, as well as all interrupts
  26. * and faults that can result in a task-switch.
  27. *
  28. * NOTE: This code handles signal-recognition, which happens every time
  29. * after a timer-interrupt and after each system call.
  30. *
  31. * NOTE: This code uses a convention that instructions in the delay slot
  32. * of a transfer-control instruction are indented by an extra space, thus:
  33. *
  34. * jmp @k0 ! control-transfer instruction
  35. * ldc k1, ssr ! delay slot
  36. *
  37. * Stack layout in 'ret_from_syscall':
  38. * ptrace needs to have all regs on the stack.
  39. * if the order here is changed, it needs to be
  40. * updated in ptrace.c and ptrace.h
  41. *
  42. * r0
  43. * ...
  44. * r15 = stack pointer
  45. * spc
  46. * pr
  47. * ssr
  48. * gbr
  49. * mach
  50. * macl
  51. * syscall #
  52. *
  53. */
  54. #if defined(CONFIG_KGDB)
  55. NMI_VEC = 0x1c0 ! Must catch early for debounce
  56. #endif
  57. /* Offsets to the stack */
  58. OFF_R0 = 0 /* Return value. New ABI also arg4 */
  59. OFF_R1 = 4 /* New ABI: arg5 */
  60. OFF_R2 = 8 /* New ABI: arg6 */
  61. OFF_R3 = 12 /* New ABI: syscall_nr */
  62. OFF_R4 = 16 /* New ABI: arg0 */
  63. OFF_R5 = 20 /* New ABI: arg1 */
  64. OFF_R6 = 24 /* New ABI: arg2 */
  65. OFF_R7 = 28 /* New ABI: arg3 */
  66. OFF_SP = (15*4)
  67. OFF_PC = (16*4)
  68. OFF_SR = (16*4+8)
  69. OFF_TRA = (16*4+6*4)
  70. #define k0 r0
  71. #define k1 r1
  72. #define k2 r2
  73. #define k3 r3
  74. #define k4 r4
  75. #define g_imask r6 /* r6_bank1 */
  76. #define k_g_imask r6_bank /* r6_bank1 */
  77. #define current r7 /* r7_bank1 */
  78. #include <asm/entry-macros.S>
  79. /*
  80. * Kernel mode register usage:
  81. * k0 scratch
  82. * k1 scratch
  83. * k2 scratch (Exception code)
  84. * k3 scratch (Return address)
  85. * k4 scratch
  86. * k5 reserved
  87. * k6 Global Interrupt Mask (0--15 << 4)
  88. * k7 CURRENT_THREAD_INFO (pointer to current thread info)
  89. */
  90. !
  91. ! TLB Miss / Initial Page write exception handling
  92. ! _and_
  93. ! TLB hits, but the access violate the protection.
  94. ! It can be valid access, such as stack grow and/or C-O-W.
  95. !
  96. !
  97. ! Find the pmd/pte entry and loadtlb
  98. ! If it's not found, cause address error (SEGV)
  99. !
  100. ! Although this could be written in assembly language (and it'd be faster),
  101. ! this first version depends *much* on C implementation.
  102. !
  103. #if defined(CONFIG_MMU)
  104. .align 2
  105. ENTRY(tlb_miss_load)
  106. bra call_handle_tlbmiss
  107. mov #0, r5
  108. .align 2
  109. ENTRY(tlb_miss_store)
  110. bra call_handle_tlbmiss
  111. mov #1, r5
  112. .align 2
  113. ENTRY(initial_page_write)
  114. bra call_handle_tlbmiss
  115. mov #2, r5
  116. .align 2
  117. ENTRY(tlb_protection_violation_load)
  118. bra call_do_page_fault
  119. mov #0, r5
  120. .align 2
  121. ENTRY(tlb_protection_violation_store)
  122. bra call_do_page_fault
  123. mov #1, r5
  124. call_handle_tlbmiss:
  125. setup_frame_reg
  126. mov.l 1f, r0
  127. mov r5, r8
  128. mov.l @r0, r6
  129. mov.l 2f, r0
  130. sts pr, r10
  131. jsr @r0
  132. mov r15, r4
  133. !
  134. tst r0, r0
  135. bf/s 0f
  136. lds r10, pr
  137. rts
  138. nop
  139. 0:
  140. mov r8, r5
  141. call_do_page_fault:
  142. mov.l 1f, r0
  143. mov.l @r0, r6
  144. sti
  145. mov.l 3f, r0
  146. mov.l 4f, r1
  147. mov r15, r4
  148. jmp @r0
  149. lds r1, pr
  150. .align 2
  151. 1: .long MMU_TEA
  152. 2: .long handle_tlbmiss
  153. 3: .long do_page_fault
  154. 4: .long ret_from_exception
  155. .align 2
  156. ENTRY(address_error_load)
  157. bra call_dae
  158. mov #0,r5 ! writeaccess = 0
  159. .align 2
  160. ENTRY(address_error_store)
  161. bra call_dae
  162. mov #1,r5 ! writeaccess = 1
  163. .align 2
  164. call_dae:
  165. mov.l 1f, r0
  166. mov.l @r0, r6 ! address
  167. mov.l 2f, r0
  168. jmp @r0
  169. mov r15, r4 ! regs
  170. .align 2
  171. 1: .long MMU_TEA
  172. 2: .long do_address_error
  173. #endif /* CONFIG_MMU */
  174. #if defined(CONFIG_SH_STANDARD_BIOS)
  175. /* Unwind the stack and jmp to the debug entry */
  176. ENTRY(sh_bios_handler)
  177. mov.l 1f, r8
  178. bsr restore_regs
  179. nop
  180. lds k2, pr ! restore pr
  181. mov k4, r15
  182. !
  183. mov.l 2f, k0
  184. mov.l @k0, k0
  185. jmp @k0
  186. ldc k3, ssr
  187. .align 2
  188. 1: .long 0x300000f0
  189. 2: .long gdb_vbr_vector
  190. #endif /* CONFIG_SH_STANDARD_BIOS */
  191. ! restore_regs()
  192. ! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack
  193. ! - switch bank
  194. ! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack
  195. ! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra
  196. ! k2 returns original pr
  197. ! k3 returns original sr
  198. ! k4 returns original stack pointer
  199. ! r8 passes SR bitmask, overwritten with restored data on return
  200. ! r9 trashed
  201. ! BL=0 on entry, on exit BL=1 (depending on r8).
  202. ENTRY(restore_regs)
  203. mov.l @r15+, r0
  204. mov.l @r15+, r1
  205. mov.l @r15+, r2
  206. mov.l @r15+, r3
  207. mov.l @r15+, r4
  208. mov.l @r15+, r5
  209. mov.l @r15+, r6
  210. mov.l @r15+, r7
  211. !
  212. stc sr, r9
  213. or r8, r9
  214. ldc r9, sr
  215. !
  216. mov.l @r15+, r8
  217. mov.l @r15+, r9
  218. mov.l @r15+, r10
  219. mov.l @r15+, r11
  220. mov.l @r15+, r12
  221. mov.l @r15+, r13
  222. mov.l @r15+, r14
  223. mov.l @r15+, k4 ! original stack pointer
  224. ldc.l @r15+, spc
  225. mov.l @r15+, k2 ! original PR
  226. mov.l @r15+, k3 ! original SR
  227. ldc.l @r15+, gbr
  228. lds.l @r15+, mach
  229. lds.l @r15+, macl
  230. rts
  231. add #4, r15 ! Skip syscall number
  232. restore_all:
  233. mov.l 7f, r8
  234. bsr restore_regs
  235. nop
  236. lds k2, pr ! restore pr
  237. !
  238. ! Calculate new SR value
  239. mov k3, k2 ! original SR value
  240. mov #0xf0, k1
  241. extu.b k1, k1
  242. not k1, k1
  243. and k1, k2 ! Mask original SR value
  244. !
  245. mov k3, k0 ! Calculate IMASK-bits
  246. shlr2 k0
  247. and #0x3c, k0
  248. cmp/eq #0x3c, k0
  249. bt/s 6f
  250. shll2 k0
  251. mov g_imask, k0
  252. !
  253. 6: or k0, k2 ! Set the IMASK-bits
  254. ldc k2, ssr
  255. !
  256. #if defined(CONFIG_KGDB)
  257. ! Clear in_nmi
  258. mov.l 6f, k0
  259. mov #0, k1
  260. mov.b k1, @k0
  261. #endif
  262. mov k4, r15
  263. rte
  264. nop
  265. .align 2
  266. 5: .long 0x00001000 ! DSP
  267. #ifdef CONFIG_KGDB
  268. 6: .long in_nmi
  269. #endif
  270. 7: .long 0x30000000
  271. ! common exception handler
  272. #include "../../entry-common.S"
  273. ! Exception Vector Base
  274. !
  275. ! Should be aligned page boundary.
  276. !
  277. .balign 4096,0,4096
  278. ENTRY(vbr_base)
  279. .long 0
  280. !
  281. ! 0x100: General exception vector
  282. !
  283. .balign 256,0,256
  284. general_exception:
  285. #ifndef CONFIG_CPU_SUBTYPE_SHX3
  286. bra handle_exception
  287. sts pr, k3 ! save original pr value in k3
  288. #else
  289. mov.l 1f, k4
  290. mov.l @k4, k4
  291. ! Is EXPEVT larger than 0x800?
  292. mov #0x8, k0
  293. shll8 k0
  294. cmp/hs k0, k4
  295. bf 0f
  296. ! then add 0x580 (k2 is 0xd80 or 0xda0)
  297. mov #0x58, k0
  298. shll2 k0
  299. shll2 k0
  300. add k0, k4
  301. 0:
  302. ! Setup stack and save DSP context (k0 contains original r15 on return)
  303. bsr prepare_stack
  304. nop
  305. ! Save registers / Switch to bank 0
  306. mov k4, k2 ! keep vector in k2
  307. mov.l 1f, k4 ! SR bits to clear in k4
  308. bsr save_regs ! needs original pr value in k3
  309. nop
  310. bra handle_exception_special
  311. nop
  312. .align 2
  313. 1: .long EXPEVT
  314. #endif
  315. ! prepare_stack()
  316. ! - roll back gRB
  317. ! - switch to kernel stack
  318. ! k0 returns original sp (after roll back)
  319. ! k1 trashed
  320. ! k2 trashed
  321. prepare_stack:
  322. #ifdef CONFIG_GUSA
  323. ! Check for roll back gRB (User and Kernel)
  324. mov r15, k0
  325. shll k0
  326. bf/s 1f
  327. shll k0
  328. bf/s 1f
  329. stc spc, k1
  330. stc r0_bank, k0
  331. cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0)
  332. bt/s 2f
  333. stc r1_bank, k1
  334. add #-2, k0
  335. add r15, k0
  336. ldc k0, spc ! PC = saved r0 + r15 - 2
  337. 2: mov k1, r15 ! SP = r1
  338. 1:
  339. #endif
  340. ! Switch to kernel stack if needed
  341. stc ssr, k0 ! Is it from kernel space?
  342. shll k0 ! Check MD bit (bit30) by shifting it into...
  343. shll k0 ! ...the T bit
  344. bt/s 1f ! It's a kernel to kernel transition.
  345. mov r15, k0 ! save original stack to k0
  346. /* User space to kernel */
  347. mov #(THREAD_SIZE >> 10), k1
  348. shll8 k1 ! k1 := THREAD_SIZE
  349. shll2 k1
  350. add current, k1
  351. mov k1, r15 ! change to kernel stack
  352. !
  353. 1:
  354. rts
  355. nop
  356. !
  357. ! 0x400: Instruction and Data TLB miss exception vector
  358. !
  359. .balign 1024,0,1024
  360. tlb_miss:
  361. sts pr, k3 ! save original pr value in k3
  362. handle_exception:
  363. mova exception_data, k0
  364. ! Setup stack and save DSP context (k0 contains original r15 on return)
  365. bsr prepare_stack
  366. PREF(k0)
  367. ! Save registers / Switch to bank 0
  368. mov.l 5f, k2 ! vector register address
  369. mov.l 1f, k4 ! SR bits to clear in k4
  370. bsr save_regs ! needs original pr value in k3
  371. mov.l @k2, k2 ! read out vector and keep in k2
  372. handle_exception_special:
  373. ! Setup return address and jump to exception handler
  374. mov.l 7f, r9 ! fetch return address
  375. stc r2_bank, r0 ! k2 (vector)
  376. mov.l 6f, r10
  377. shlr2 r0
  378. shlr r0
  379. mov.l @(r0, r10), r10
  380. jmp @r10
  381. lds r9, pr ! put return address in pr
  382. .align L1_CACHE_SHIFT
  383. ! save_regs()
  384. ! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack
  385. ! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack
  386. ! - switch bank
  387. ! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
  388. ! k0 contains original stack pointer*
  389. ! k1 trashed
  390. ! k3 passes original pr*
  391. ! k4 passes SR bitmask
  392. ! BL=1 on entry, on exit BL=0.
  393. ENTRY(save_regs)
  394. mov #-1, r1
  395. mov.l k1, @-r15 ! set TRA (default: -1)
  396. sts.l macl, @-r15
  397. sts.l mach, @-r15
  398. stc.l gbr, @-r15
  399. stc.l ssr, @-r15
  400. mov.l k3, @-r15 ! original pr in k3
  401. stc.l spc, @-r15
  402. mov.l k0, @-r15 ! original stack pointer in k0
  403. mov.l r14, @-r15
  404. mov.l r13, @-r15
  405. mov.l r12, @-r15
  406. mov.l r11, @-r15
  407. mov.l r10, @-r15
  408. mov.l r9, @-r15
  409. mov.l r8, @-r15
  410. mov.l 0f, k3 ! SR bits to set in k3
  411. ! fall-through
  412. ! save_low_regs()
  413. ! - modify SR for bank switch
  414. ! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
  415. ! k3 passes bits to set in SR
  416. ! k4 passes bits to clear in SR
  417. ENTRY(save_low_regs)
  418. stc sr, r8
  419. or k3, r8
  420. and k4, r8
  421. ldc r8, sr
  422. mov.l r7, @-r15
  423. mov.l r6, @-r15
  424. mov.l r5, @-r15
  425. mov.l r4, @-r15
  426. mov.l r3, @-r15
  427. mov.l r2, @-r15
  428. mov.l r1, @-r15
  429. rts
  430. mov.l r0, @-r15
  431. !
  432. ! 0x600: Interrupt / NMI vector
  433. !
  434. .balign 512,0,512
  435. ENTRY(handle_interrupt)
  436. #if defined(CONFIG_KGDB)
  437. mov.l 2f, k2
  438. ! Debounce (filter nested NMI)
  439. mov.l @k2, k0
  440. mov.l 9f, k1
  441. cmp/eq k1, k0
  442. bf 11f
  443. mov.l 10f, k1
  444. tas.b @k1
  445. bt 11f
  446. rte
  447. nop
  448. .align 2
  449. 9: .long NMI_VEC
  450. 10: .long in_nmi
  451. 11:
  452. #endif /* defined(CONFIG_KGDB) */
  453. sts pr, k3 ! save original pr value in k3
  454. mova exception_data, k0
  455. ! Setup stack and save DSP context (k0 contains original r15 on return)
  456. bsr prepare_stack
  457. PREF(k0)
  458. ! Save registers / Switch to bank 0
  459. mov.l 1f, k4 ! SR bits to clear in k4
  460. bsr save_regs ! needs original pr value in k3
  461. mov #-1, k2 ! default vector kept in k2
  462. stc sr, r0 ! get status register
  463. shlr2 r0
  464. and #0x3c, r0
  465. cmp/eq #0x3c, r0
  466. bf 9f
  467. TRACE_IRQS_OFF
  468. 9:
  469. ! Setup return address and jump to do_IRQ
  470. mov.l 4f, r9 ! fetch return address
  471. lds r9, pr ! put return address in pr
  472. mov.l 2f, r4
  473. mov.l 3f, r9
  474. mov.l @r4, r4 ! pass INTEVT vector as arg0
  475. jmp @r9
  476. mov r15, r5 ! pass saved registers as arg1
  477. ENTRY(exception_none)
  478. rts
  479. nop
  480. .align L1_CACHE_SHIFT
  481. exception_data:
  482. 0: .long 0x000080f0 ! FD=1, IMASK=15
  483. 1: .long 0xcfffffff ! RB=0, BL=0
  484. 2: .long INTEVT
  485. 3: .long do_IRQ
  486. 4: .long ret_from_irq
  487. 5: .long EXPEVT
  488. 6: .long exception_handling_table
  489. 7: .long ret_from_exception