azt3328.c 62 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005, 2006, 2007 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * Note that "conformant" != "compliant"!! this chip's mixer register layout
  42. * *differs* from the standard AC97 layout:
  43. * they chose to not implement the headphone register (which is not a
  44. * problem since it's merely optional), yet when doing this, they committed
  45. * the grave sin of letting other registers follow immediately instead of
  46. * keeping a headphone dummy register, thereby shifting the mixer register
  47. * addresses illegally. So far unfortunately it looks like the very flexible
  48. * ALSA AC97 support is still not enough to easily compensate for such a
  49. * grave layout violation despite all tweaks and quirks mechanisms it offers.
  50. * - builtin genuine OPL3
  51. * - full duplex 16bit playback/record at independent sampling rate
  52. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  53. * - game port (legacy address support)
  54. * - builtin 3D enhancement (said to be YAMAHA Ymersion)
  55. * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
  56. * features supported)
  57. * - built-in General DirectX timer having a 20 bits counter
  58. * with 1us resolution (see below!)
  59. * - I2S serial port for external DAC
  60. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  61. * - supports hardware volume control
  62. * - single chip low cost solution (128 pin QFP)
  63. * - supports programmable Sub-vendor and Sub-system ID
  64. * required for Microsoft's logo compliance (FIXME: where?)
  65. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  66. *
  67. * Note that this driver now is actually *better* than the Windows driver,
  68. * since it additionally supports the card's 1MHz DirectX timer - just try
  69. * the following snd-seq module parameters etc.:
  70. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  71. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  72. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  73. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  74. * - "pmidi -p 128:0 jazz.mid"
  75. *
  76. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  77. * in some systems (resulting in sound crackling/clicking/popping),
  78. * probably because they don't have a DMA FIFO buffer or so.
  79. * Overview (PCI ID/PCI subID/PCI rev.):
  80. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  81. * - unknown performance: 0x50DC/0x1801/10
  82. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  83. *
  84. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  85. * supposed to be very fast and supposed to get rid of crackling much
  86. * better than a VIA, yet ironically I still get crackling, like many other
  87. * people with the same chipset.
  88. * Possible remedies:
  89. * - plug card into a different PCI slot, preferrably one that isn't shared
  90. * too much (this helps a lot, but not completely!)
  91. * - get rid of PCI VGA card, use AGP instead
  92. * - upgrade or downgrade BIOS
  93. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  94. * Not too helpful.
  95. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  96. *
  97. * BUGS
  98. * - full-duplex might *still* be problematic, not fully tested recently
  99. * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
  100. * if you set PCM output switch to "pre 3D" instead of "post 3D".
  101. * If this can't be set, then get a mixer application that Isn't Stupid (tm)
  102. * (e.g. kmix, gamix) - unfortunately several are!!
  103. *
  104. * TODO
  105. * - test MPU401 MIDI playback etc.
  106. * - add some power micro-management (disable various units of the card
  107. * as long as they're unused). However this requires I/O ports which I
  108. * haven't figured out yet and which thus might not even exist...
  109. * The standard suspend/resume functionality could probably make use of
  110. * some improvement, too...
  111. * - figure out what all unknown port bits are responsible for
  112. * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
  113. * fully accept our quite incompatible ""AC97"" mixer and thus save some
  114. * code (but I'm not too optimistic that doing this is possible at all)
  115. */
  116. #include <asm/io.h>
  117. #include <linux/init.h>
  118. #include <linux/pci.h>
  119. #include <linux/delay.h>
  120. #include <linux/slab.h>
  121. #include <linux/gameport.h>
  122. #include <linux/moduleparam.h>
  123. #include <linux/dma-mapping.h>
  124. #include <sound/core.h>
  125. #include <sound/control.h>
  126. #include <sound/pcm.h>
  127. #include <sound/rawmidi.h>
  128. #include <sound/mpu401.h>
  129. #include <sound/opl3.h>
  130. #include <sound/initval.h>
  131. #include "azt3328.h"
  132. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  133. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  134. MODULE_LICENSE("GPL");
  135. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  136. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  137. #define SUPPORT_JOYSTICK 1
  138. #endif
  139. #define DEBUG_MISC 0
  140. #define DEBUG_CALLS 0
  141. #define DEBUG_MIXER 0
  142. #define DEBUG_PLAY_REC 0
  143. #define DEBUG_IO 0
  144. #define DEBUG_TIMER 0
  145. #define MIXER_TESTING 0
  146. #if DEBUG_MISC
  147. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  148. #else
  149. #define snd_azf3328_dbgmisc(format, args...)
  150. #endif
  151. #if DEBUG_CALLS
  152. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  153. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  154. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  155. #else
  156. #define snd_azf3328_dbgcalls(format, args...)
  157. #define snd_azf3328_dbgcallenter()
  158. #define snd_azf3328_dbgcallleave()
  159. #endif
  160. #if DEBUG_MIXER
  161. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  162. #else
  163. #define snd_azf3328_dbgmixer(format, args...)
  164. #endif
  165. #if DEBUG_PLAY_REC
  166. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  167. #else
  168. #define snd_azf3328_dbgplay(format, args...)
  169. #endif
  170. #if DEBUG_MISC
  171. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  172. #else
  173. #define snd_azf3328_dbgtimer(format, args...)
  174. #endif
  175. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  176. module_param_array(index, int, NULL, 0444);
  177. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  178. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  179. module_param_array(id, charp, NULL, 0444);
  180. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  181. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  182. module_param_array(enable, bool, NULL, 0444);
  183. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  184. #ifdef SUPPORT_JOYSTICK
  185. static int joystick[SNDRV_CARDS];
  186. module_param_array(joystick, bool, NULL, 0444);
  187. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  188. #endif
  189. static int seqtimer_scaling = 128;
  190. module_param(seqtimer_scaling, int, 0444);
  191. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  192. struct snd_azf3328 {
  193. /* often-used fields towards beginning, then grouped */
  194. unsigned long codec_port;
  195. unsigned long io2_port;
  196. unsigned long mpu_port;
  197. unsigned long synth_port;
  198. unsigned long mixer_port;
  199. spinlock_t reg_lock;
  200. struct snd_timer *timer;
  201. struct snd_pcm *pcm;
  202. struct snd_pcm_substream *playback_substream;
  203. struct snd_pcm_substream *capture_substream;
  204. unsigned int is_playing;
  205. unsigned int is_recording;
  206. struct snd_card *card;
  207. struct snd_rawmidi *rmidi;
  208. #ifdef SUPPORT_JOYSTICK
  209. struct gameport *gameport;
  210. #endif
  211. struct pci_dev *pci;
  212. int irq;
  213. #ifdef CONFIG_PM
  214. /* register value containers for power management
  215. * Note: not always full I/O range preserved (just like Win driver!) */
  216. u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2];
  217. u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2];
  218. u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
  219. u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2];
  220. u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
  221. #endif
  222. };
  223. static const struct pci_device_id snd_azf3328_ids[] = {
  224. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  225. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  226. { 0, }
  227. };
  228. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  229. static inline void
  230. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  231. {
  232. outb(value, chip->codec_port + reg);
  233. }
  234. static inline u8
  235. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  236. {
  237. return inb(chip->codec_port + reg);
  238. }
  239. static inline void
  240. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  241. {
  242. outw(value, chip->codec_port + reg);
  243. }
  244. static inline u16
  245. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  246. {
  247. return inw(chip->codec_port + reg);
  248. }
  249. static inline void
  250. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  251. {
  252. outl(value, chip->codec_port + reg);
  253. }
  254. static inline void
  255. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  256. {
  257. outb(value, chip->io2_port + reg);
  258. }
  259. static inline u8
  260. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  261. {
  262. return inb(chip->io2_port + reg);
  263. }
  264. static inline void
  265. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  266. {
  267. outw(value, chip->mixer_port + reg);
  268. }
  269. static inline u16
  270. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  271. {
  272. return inw(chip->mixer_port + reg);
  273. }
  274. static void
  275. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  276. {
  277. unsigned long portbase = chip->mixer_port + reg + 1;
  278. unsigned char oldval;
  279. /* the mute bit is on the *second* (i.e. right) register of a
  280. * left/right channel setting */
  281. oldval = inb(portbase);
  282. if (do_mute)
  283. oldval |= 0x80;
  284. else
  285. oldval &= ~0x80;
  286. outb(oldval, portbase);
  287. }
  288. static void
  289. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  290. {
  291. unsigned long portbase = chip->mixer_port + reg;
  292. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  293. int left_done = 0, right_done = 0;
  294. snd_azf3328_dbgcallenter();
  295. if (chan_sel & SET_CHAN_LEFT)
  296. curr_vol_left = inb(portbase + 1);
  297. else
  298. left_done = 1;
  299. if (chan_sel & SET_CHAN_RIGHT)
  300. curr_vol_right = inb(portbase + 0);
  301. else
  302. right_done = 1;
  303. /* take care of muting flag (0x80) contained in left channel */
  304. if (curr_vol_left & 0x80)
  305. dst_vol_left |= 0x80;
  306. else
  307. dst_vol_left &= ~0x80;
  308. do {
  309. if (!left_done) {
  310. if (curr_vol_left > dst_vol_left)
  311. curr_vol_left--;
  312. else
  313. if (curr_vol_left < dst_vol_left)
  314. curr_vol_left++;
  315. else
  316. left_done = 1;
  317. outb(curr_vol_left, portbase + 1);
  318. }
  319. if (!right_done) {
  320. if (curr_vol_right > dst_vol_right)
  321. curr_vol_right--;
  322. else
  323. if (curr_vol_right < dst_vol_right)
  324. curr_vol_right++;
  325. else
  326. right_done = 1;
  327. /* during volume change, the right channel is crackling
  328. * somewhat more than the left channel, unfortunately.
  329. * This seems to be a hardware issue. */
  330. outb(curr_vol_right, portbase + 0);
  331. }
  332. if (delay)
  333. mdelay(delay);
  334. } while ((!left_done) || (!right_done));
  335. snd_azf3328_dbgcallleave();
  336. }
  337. /*
  338. * general mixer element
  339. */
  340. struct azf3328_mixer_reg {
  341. unsigned int reg;
  342. unsigned int lchan_shift, rchan_shift;
  343. unsigned int mask;
  344. unsigned int invert: 1;
  345. unsigned int stereo: 1;
  346. unsigned int enum_c: 4;
  347. };
  348. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  349. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  350. (mask << 16) | \
  351. (invert << 24) | \
  352. (stereo << 25) | \
  353. (enum_c << 26))
  354. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  355. {
  356. r->reg = val & 0xff;
  357. r->lchan_shift = (val >> 8) & 0x0f;
  358. r->rchan_shift = (val >> 12) & 0x0f;
  359. r->mask = (val >> 16) & 0xff;
  360. r->invert = (val >> 24) & 1;
  361. r->stereo = (val >> 25) & 1;
  362. r->enum_c = (val >> 26) & 0x0f;
  363. }
  364. /*
  365. * mixer switches/volumes
  366. */
  367. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  368. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  369. .info = snd_azf3328_info_mixer, \
  370. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  371. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  372. }
  373. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  374. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  375. .info = snd_azf3328_info_mixer, \
  376. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  377. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  378. }
  379. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  380. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  381. .info = snd_azf3328_info_mixer, \
  382. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  383. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  384. }
  385. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  386. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  387. .info = snd_azf3328_info_mixer, \
  388. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  389. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  390. }
  391. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  392. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  393. .info = snd_azf3328_info_mixer_enum, \
  394. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  395. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  396. }
  397. static int
  398. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  399. struct snd_ctl_elem_info *uinfo)
  400. {
  401. struct azf3328_mixer_reg reg;
  402. snd_azf3328_dbgcallenter();
  403. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  404. uinfo->type = reg.mask == 1 ?
  405. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  406. uinfo->count = reg.stereo + 1;
  407. uinfo->value.integer.min = 0;
  408. uinfo->value.integer.max = reg.mask;
  409. snd_azf3328_dbgcallleave();
  410. return 0;
  411. }
  412. static int
  413. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  414. struct snd_ctl_elem_value *ucontrol)
  415. {
  416. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  417. struct azf3328_mixer_reg reg;
  418. unsigned int oreg, val;
  419. snd_azf3328_dbgcallenter();
  420. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  421. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  422. val = (oreg >> reg.lchan_shift) & reg.mask;
  423. if (reg.invert)
  424. val = reg.mask - val;
  425. ucontrol->value.integer.value[0] = val;
  426. if (reg.stereo) {
  427. val = (oreg >> reg.rchan_shift) & reg.mask;
  428. if (reg.invert)
  429. val = reg.mask - val;
  430. ucontrol->value.integer.value[1] = val;
  431. }
  432. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  433. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  434. reg.reg, oreg,
  435. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  436. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  437. snd_azf3328_dbgcallleave();
  438. return 0;
  439. }
  440. static int
  441. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  442. struct snd_ctl_elem_value *ucontrol)
  443. {
  444. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  445. struct azf3328_mixer_reg reg;
  446. unsigned int oreg, nreg, val;
  447. snd_azf3328_dbgcallenter();
  448. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  449. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  450. val = ucontrol->value.integer.value[0] & reg.mask;
  451. if (reg.invert)
  452. val = reg.mask - val;
  453. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  454. nreg |= (val << reg.lchan_shift);
  455. if (reg.stereo) {
  456. val = ucontrol->value.integer.value[1] & reg.mask;
  457. if (reg.invert)
  458. val = reg.mask - val;
  459. nreg &= ~(reg.mask << reg.rchan_shift);
  460. nreg |= (val << reg.rchan_shift);
  461. }
  462. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  463. snd_azf3328_mixer_write_volume_gradually(
  464. chip, reg.reg, nreg >> 8, nreg & 0xff,
  465. /* just set both channels, doesn't matter */
  466. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  467. 0);
  468. else
  469. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  470. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  471. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  472. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  473. oreg, reg.lchan_shift, reg.rchan_shift,
  474. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  475. snd_azf3328_dbgcallleave();
  476. return (nreg != oreg);
  477. }
  478. static int
  479. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  480. struct snd_ctl_elem_info *uinfo)
  481. {
  482. static const char * const texts1[] = {
  483. "Mic1", "Mic2"
  484. };
  485. static const char * const texts2[] = {
  486. "Mix", "Mic"
  487. };
  488. static const char * const texts3[] = {
  489. "Mic", "CD", "Video", "Aux",
  490. "Line", "Mix", "Mix Mono", "Phone"
  491. };
  492. static const char * const texts4[] = {
  493. "pre 3D", "post 3D"
  494. };
  495. struct azf3328_mixer_reg reg;
  496. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  497. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  498. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  499. uinfo->value.enumerated.items = reg.enum_c;
  500. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  501. uinfo->value.enumerated.item = reg.enum_c - 1U;
  502. if (reg.reg == IDX_MIXER_ADVCTL2) {
  503. switch(reg.lchan_shift) {
  504. case 8: /* modem out sel */
  505. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  506. break;
  507. case 9: /* mono sel source */
  508. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  509. break;
  510. case 15: /* PCM Out Path */
  511. strcpy(uinfo->value.enumerated.name, texts4[uinfo->value.enumerated.item]);
  512. break;
  513. }
  514. } else
  515. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  516. );
  517. return 0;
  518. }
  519. static int
  520. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  521. struct snd_ctl_elem_value *ucontrol)
  522. {
  523. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  524. struct azf3328_mixer_reg reg;
  525. unsigned short val;
  526. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  527. val = snd_azf3328_mixer_inw(chip, reg.reg);
  528. if (reg.reg == IDX_MIXER_REC_SELECT) {
  529. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  530. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  531. } else
  532. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  533. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  534. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  535. reg.lchan_shift, reg.enum_c);
  536. return 0;
  537. }
  538. static int
  539. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  540. struct snd_ctl_elem_value *ucontrol)
  541. {
  542. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  543. struct azf3328_mixer_reg reg;
  544. unsigned int oreg, nreg, val;
  545. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  546. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  547. val = oreg;
  548. if (reg.reg == IDX_MIXER_REC_SELECT) {
  549. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  550. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  551. return -EINVAL;
  552. val = (ucontrol->value.enumerated.item[0] << 8) |
  553. (ucontrol->value.enumerated.item[1] << 0);
  554. } else {
  555. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  556. return -EINVAL;
  557. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  558. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  559. }
  560. snd_azf3328_mixer_outw(chip, reg.reg, val);
  561. nreg = val;
  562. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  563. return (nreg != oreg);
  564. }
  565. static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  566. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  567. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  568. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  569. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  570. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  571. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  572. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  573. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  574. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  575. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  576. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  577. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  578. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  579. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  580. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  581. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  582. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  583. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  584. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  585. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  586. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  587. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  588. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  589. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  590. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  591. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  592. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  593. AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
  594. AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
  595. AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
  596. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  597. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  598. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  599. AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  600. AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  601. #if MIXER_TESTING
  602. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  603. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  604. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  605. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  606. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  607. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  608. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  609. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  610. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  611. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  612. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  613. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  614. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  615. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  616. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  617. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  618. #endif
  619. };
  620. static u16 __devinitdata snd_azf3328_init_values[][2] = {
  621. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  622. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  623. { IDX_MIXER_BASSTREBLE, 0x0000 },
  624. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  625. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  626. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  627. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  628. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  629. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  630. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  631. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  632. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  633. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  634. };
  635. static int __devinit
  636. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  637. {
  638. struct snd_card *card;
  639. const struct snd_kcontrol_new *sw;
  640. unsigned int idx;
  641. int err;
  642. snd_azf3328_dbgcallenter();
  643. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  644. card = chip->card;
  645. /* mixer reset */
  646. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  647. /* mute and zero volume channels */
  648. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  649. snd_azf3328_mixer_outw(chip,
  650. snd_azf3328_init_values[idx][0],
  651. snd_azf3328_init_values[idx][1]);
  652. }
  653. /* add mixer controls */
  654. sw = snd_azf3328_mixer_controls;
  655. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  656. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  657. return err;
  658. }
  659. snd_component_add(card, "AZF3328 mixer");
  660. strcpy(card->mixername, "AZF3328 mixer");
  661. snd_azf3328_dbgcallleave();
  662. return 0;
  663. }
  664. static int
  665. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  666. struct snd_pcm_hw_params *hw_params)
  667. {
  668. int res;
  669. snd_azf3328_dbgcallenter();
  670. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  671. snd_azf3328_dbgcallleave();
  672. return res;
  673. }
  674. static int
  675. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  676. {
  677. snd_azf3328_dbgcallenter();
  678. snd_pcm_lib_free_pages(substream);
  679. snd_azf3328_dbgcallleave();
  680. return 0;
  681. }
  682. static void
  683. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  684. unsigned int reg,
  685. unsigned int bitrate,
  686. unsigned int format_width,
  687. unsigned int channels
  688. )
  689. {
  690. u16 val = 0xff00;
  691. unsigned long flags;
  692. snd_azf3328_dbgcallenter();
  693. switch (bitrate) {
  694. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  695. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  696. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  697. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  698. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  699. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  700. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  701. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  702. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  703. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  704. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  705. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  706. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  707. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  708. default:
  709. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  710. val |= SOUNDFORMAT_FREQ_44100;
  711. break;
  712. }
  713. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  714. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  715. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  716. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  717. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  718. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  719. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  720. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  721. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  722. if (channels == 2)
  723. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  724. if (format_width == 16)
  725. val |= SOUNDFORMAT_FLAG_16BIT;
  726. spin_lock_irqsave(&chip->reg_lock, flags);
  727. /* set bitrate/format */
  728. snd_azf3328_codec_outw(chip, reg, val);
  729. /* changing the bitrate/format settings switches off the
  730. * audio output with an annoying click in case of 8/16bit format change
  731. * (maybe shutting down DAC/ADC?), thus immediately
  732. * do some tweaking to reenable it and get rid of the clicking
  733. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  734. * FIXME: does this have some side effects for full-duplex
  735. * or other dramatic side effects? */
  736. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  737. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  738. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  739. DMA_PLAY_SOMETHING1 |
  740. DMA_PLAY_SOMETHING2 |
  741. SOMETHING_ALMOST_ALWAYS_SET |
  742. DMA_EPILOGUE_SOMETHING |
  743. DMA_SOMETHING_ELSE
  744. );
  745. spin_unlock_irqrestore(&chip->reg_lock, flags);
  746. snd_azf3328_dbgcallleave();
  747. }
  748. static void
  749. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  750. long unsigned int addr,
  751. unsigned int count,
  752. unsigned int size,
  753. int do_recording)
  754. {
  755. unsigned long flags, portbase;
  756. unsigned int is_running;
  757. snd_azf3328_dbgcallenter();
  758. if (do_recording) {
  759. /* access capture registers, i.e. skip playback reg section */
  760. portbase = chip->codec_port + 0x20;
  761. is_running = chip->is_recording;
  762. } else {
  763. /* access the playback register section */
  764. portbase = chip->codec_port + 0x00;
  765. is_running = chip->is_playing;
  766. }
  767. /* AZF3328 uses a two buffer pointer DMA playback approach */
  768. if (!is_running) {
  769. unsigned long addr_area2;
  770. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  771. count_areas = size/2;
  772. addr_area2 = addr+count_areas;
  773. count_areas--; /* max. index */
  774. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  775. /* build combined I/O buffer length word */
  776. count_tmp = count_areas;
  777. count_areas |= (count_tmp << 16);
  778. spin_lock_irqsave(&chip->reg_lock, flags);
  779. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  780. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  781. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  782. spin_unlock_irqrestore(&chip->reg_lock, flags);
  783. }
  784. snd_azf3328_dbgcallleave();
  785. }
  786. static int
  787. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  788. {
  789. #if 0
  790. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  791. struct snd_pcm_runtime *runtime = substream->runtime;
  792. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  793. unsigned int count = snd_pcm_lib_period_bytes(substream);
  794. #endif
  795. snd_azf3328_dbgcallenter();
  796. #if 0
  797. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  798. runtime->rate,
  799. snd_pcm_format_width(runtime->format),
  800. runtime->channels);
  801. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  802. #endif
  803. snd_azf3328_dbgcallleave();
  804. return 0;
  805. }
  806. static int
  807. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  808. {
  809. #if 0
  810. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  811. struct snd_pcm_runtime *runtime = substream->runtime;
  812. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  813. unsigned int count = snd_pcm_lib_period_bytes(substream);
  814. #endif
  815. snd_azf3328_dbgcallenter();
  816. #if 0
  817. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  818. runtime->rate,
  819. snd_pcm_format_width(runtime->format),
  820. runtime->channels);
  821. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  822. #endif
  823. snd_azf3328_dbgcallleave();
  824. return 0;
  825. }
  826. static int
  827. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  828. {
  829. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  830. struct snd_pcm_runtime *runtime = substream->runtime;
  831. int result = 0;
  832. unsigned int status1;
  833. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  834. switch (cmd) {
  835. case SNDRV_PCM_TRIGGER_START:
  836. snd_azf3328_dbgplay("START PLAYBACK\n");
  837. /* mute WaveOut */
  838. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  839. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  840. runtime->rate,
  841. snd_pcm_format_width(runtime->format),
  842. runtime->channels);
  843. spin_lock(&chip->reg_lock);
  844. /* stop playback */
  845. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  846. status1 &= ~DMA_RESUME;
  847. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  848. /* FIXME: clear interrupts or what??? */
  849. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  850. spin_unlock(&chip->reg_lock);
  851. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  852. snd_pcm_lib_period_bytes(substream),
  853. snd_pcm_lib_buffer_bytes(substream),
  854. 0);
  855. spin_lock(&chip->reg_lock);
  856. #ifdef WIN9X
  857. /* FIXME: enable playback/recording??? */
  858. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  859. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  860. /* start playback again */
  861. /* FIXME: what is this value (0x0010)??? */
  862. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  863. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  864. #else /* NT4 */
  865. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  866. 0x0000);
  867. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  868. DMA_PLAY_SOMETHING1);
  869. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  870. DMA_PLAY_SOMETHING1 |
  871. DMA_PLAY_SOMETHING2);
  872. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  873. DMA_RESUME |
  874. SOMETHING_ALMOST_ALWAYS_SET |
  875. DMA_EPILOGUE_SOMETHING |
  876. DMA_SOMETHING_ELSE);
  877. #endif
  878. spin_unlock(&chip->reg_lock);
  879. /* now unmute WaveOut */
  880. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  881. chip->is_playing = 1;
  882. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  883. break;
  884. case SNDRV_PCM_TRIGGER_RESUME:
  885. snd_azf3328_dbgplay("RESUME PLAYBACK\n");
  886. /* resume playback if we were active */
  887. if (chip->is_playing)
  888. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  889. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
  890. break;
  891. case SNDRV_PCM_TRIGGER_STOP:
  892. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  893. /* mute WaveOut */
  894. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  895. spin_lock(&chip->reg_lock);
  896. /* stop playback */
  897. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  898. status1 &= ~DMA_RESUME;
  899. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  900. /* hmm, is this really required? we're resetting the same bit
  901. * immediately thereafter... */
  902. status1 |= DMA_PLAY_SOMETHING1;
  903. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  904. status1 &= ~DMA_PLAY_SOMETHING1;
  905. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  906. spin_unlock(&chip->reg_lock);
  907. /* now unmute WaveOut */
  908. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  909. chip->is_playing = 0;
  910. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  911. break;
  912. case SNDRV_PCM_TRIGGER_SUSPEND:
  913. snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
  914. /* make sure playback is stopped */
  915. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  916. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
  917. break;
  918. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  919. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  920. break;
  921. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  922. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  923. break;
  924. default:
  925. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  926. return -EINVAL;
  927. }
  928. snd_azf3328_dbgcallleave();
  929. return result;
  930. }
  931. /* this is just analogous to playback; I'm not quite sure whether recording
  932. * should actually be triggered like that */
  933. static int
  934. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  935. {
  936. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  937. struct snd_pcm_runtime *runtime = substream->runtime;
  938. int result = 0;
  939. unsigned int status1;
  940. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  941. switch (cmd) {
  942. case SNDRV_PCM_TRIGGER_START:
  943. snd_azf3328_dbgplay("START CAPTURE\n");
  944. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  945. runtime->rate,
  946. snd_pcm_format_width(runtime->format),
  947. runtime->channels);
  948. spin_lock(&chip->reg_lock);
  949. /* stop recording */
  950. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  951. status1 &= ~DMA_RESUME;
  952. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  953. /* FIXME: clear interrupts or what??? */
  954. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  955. spin_unlock(&chip->reg_lock);
  956. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  957. snd_pcm_lib_period_bytes(substream),
  958. snd_pcm_lib_buffer_bytes(substream),
  959. 1);
  960. spin_lock(&chip->reg_lock);
  961. #ifdef WIN9X
  962. /* FIXME: enable playback/recording??? */
  963. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  964. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  965. /* start capture again */
  966. /* FIXME: what is this value (0x0010)??? */
  967. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  968. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  969. #else
  970. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  971. 0x0000);
  972. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  973. DMA_PLAY_SOMETHING1);
  974. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  975. DMA_PLAY_SOMETHING1 |
  976. DMA_PLAY_SOMETHING2);
  977. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  978. DMA_RESUME |
  979. SOMETHING_ALMOST_ALWAYS_SET |
  980. DMA_EPILOGUE_SOMETHING |
  981. DMA_SOMETHING_ELSE);
  982. #endif
  983. spin_unlock(&chip->reg_lock);
  984. chip->is_recording = 1;
  985. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  986. break;
  987. case SNDRV_PCM_TRIGGER_RESUME:
  988. snd_azf3328_dbgplay("RESUME CAPTURE\n");
  989. /* resume recording if we were active */
  990. if (chip->is_recording)
  991. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  992. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
  993. break;
  994. case SNDRV_PCM_TRIGGER_STOP:
  995. snd_azf3328_dbgplay("STOP CAPTURE\n");
  996. spin_lock(&chip->reg_lock);
  997. /* stop recording */
  998. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  999. status1 &= ~DMA_RESUME;
  1000. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1001. status1 |= DMA_PLAY_SOMETHING1;
  1002. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1003. status1 &= ~DMA_PLAY_SOMETHING1;
  1004. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  1005. spin_unlock(&chip->reg_lock);
  1006. chip->is_recording = 0;
  1007. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  1008. break;
  1009. case SNDRV_PCM_TRIGGER_SUSPEND:
  1010. snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
  1011. /* make sure recording is stopped */
  1012. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1013. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
  1014. break;
  1015. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1016. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1017. break;
  1018. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1019. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1020. break;
  1021. default:
  1022. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  1023. return -EINVAL;
  1024. }
  1025. snd_azf3328_dbgcallleave();
  1026. return result;
  1027. }
  1028. static snd_pcm_uframes_t
  1029. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  1030. {
  1031. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1032. unsigned long bufptr, result;
  1033. snd_pcm_uframes_t frmres;
  1034. #ifdef QUERY_HARDWARE
  1035. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  1036. #else
  1037. bufptr = substream->runtime->dma_addr;
  1038. #endif
  1039. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  1040. /* calculate offset */
  1041. result -= bufptr;
  1042. frmres = bytes_to_frames( substream->runtime, result);
  1043. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  1044. return frmres;
  1045. }
  1046. static snd_pcm_uframes_t
  1047. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  1048. {
  1049. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1050. unsigned long bufptr, result;
  1051. snd_pcm_uframes_t frmres;
  1052. #ifdef QUERY_HARDWARE
  1053. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1054. #else
  1055. bufptr = substream->runtime->dma_addr;
  1056. #endif
  1057. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1058. /* calculate offset */
  1059. result -= bufptr;
  1060. frmres = bytes_to_frames( substream->runtime, result);
  1061. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1062. return frmres;
  1063. }
  1064. static irqreturn_t
  1065. snd_azf3328_interrupt(int irq, void *dev_id)
  1066. {
  1067. struct snd_azf3328 *chip = dev_id;
  1068. u8 status, which;
  1069. static unsigned long irq_count;
  1070. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1071. /* fast path out, to ease interrupt sharing */
  1072. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1073. return IRQ_NONE; /* must be interrupt for another device */
  1074. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1075. irq_count,
  1076. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1077. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1078. status);
  1079. if (status & IRQ_TIMER) {
  1080. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1081. if (chip->timer)
  1082. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1083. /* ACK timer */
  1084. spin_lock(&chip->reg_lock);
  1085. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1086. spin_unlock(&chip->reg_lock);
  1087. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1088. }
  1089. if (status & IRQ_PLAYBACK) {
  1090. spin_lock(&chip->reg_lock);
  1091. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1092. /* ack all IRQ types immediately */
  1093. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1094. spin_unlock(&chip->reg_lock);
  1095. if (chip->pcm && chip->playback_substream) {
  1096. snd_pcm_period_elapsed(chip->playback_substream);
  1097. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1098. which,
  1099. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1100. } else
  1101. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1102. if (which & IRQ_PLAY_SOMETHING)
  1103. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1104. }
  1105. if (status & IRQ_RECORDING) {
  1106. spin_lock(&chip->reg_lock);
  1107. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1108. /* ack all IRQ types immediately */
  1109. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1110. spin_unlock(&chip->reg_lock);
  1111. if (chip->pcm && chip->capture_substream) {
  1112. snd_pcm_period_elapsed(chip->capture_substream);
  1113. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1114. which,
  1115. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1116. } else
  1117. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1118. if (which & IRQ_REC_SOMETHING)
  1119. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1120. }
  1121. /* MPU401 has less critical IRQ requirements
  1122. * than timer and playback/recording, right? */
  1123. if (status & IRQ_MPU401) {
  1124. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1125. /* hmm, do we have to ack the IRQ here somehow?
  1126. * If so, then I don't know how... */
  1127. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1128. }
  1129. irq_count++;
  1130. return IRQ_HANDLED;
  1131. }
  1132. /*****************************************************************/
  1133. static const struct snd_pcm_hardware snd_azf3328_playback =
  1134. {
  1135. /* FIXME!! Correct? */
  1136. .info = SNDRV_PCM_INFO_MMAP |
  1137. SNDRV_PCM_INFO_INTERLEAVED |
  1138. SNDRV_PCM_INFO_MMAP_VALID,
  1139. .formats = SNDRV_PCM_FMTBIT_S8 |
  1140. SNDRV_PCM_FMTBIT_U8 |
  1141. SNDRV_PCM_FMTBIT_S16_LE |
  1142. SNDRV_PCM_FMTBIT_U16_LE,
  1143. .rates = SNDRV_PCM_RATE_5512 |
  1144. SNDRV_PCM_RATE_8000_48000 |
  1145. SNDRV_PCM_RATE_KNOT,
  1146. .rate_min = 4000,
  1147. .rate_max = 66200,
  1148. .channels_min = 1,
  1149. .channels_max = 2,
  1150. .buffer_bytes_max = 65536,
  1151. .period_bytes_min = 64,
  1152. .period_bytes_max = 65536,
  1153. .periods_min = 1,
  1154. .periods_max = 1024,
  1155. /* FIXME: maybe that card actually has a FIFO?
  1156. * Hmm, it seems newer revisions do have one, but we still don't know
  1157. * its size... */
  1158. .fifo_size = 0,
  1159. };
  1160. static const struct snd_pcm_hardware snd_azf3328_capture =
  1161. {
  1162. /* FIXME */
  1163. .info = SNDRV_PCM_INFO_MMAP |
  1164. SNDRV_PCM_INFO_INTERLEAVED |
  1165. SNDRV_PCM_INFO_MMAP_VALID,
  1166. .formats = SNDRV_PCM_FMTBIT_S8 |
  1167. SNDRV_PCM_FMTBIT_U8 |
  1168. SNDRV_PCM_FMTBIT_S16_LE |
  1169. SNDRV_PCM_FMTBIT_U16_LE,
  1170. .rates = SNDRV_PCM_RATE_5512 |
  1171. SNDRV_PCM_RATE_8000_48000 |
  1172. SNDRV_PCM_RATE_KNOT,
  1173. .rate_min = 4000,
  1174. .rate_max = 66200,
  1175. .channels_min = 1,
  1176. .channels_max = 2,
  1177. .buffer_bytes_max = 65536,
  1178. .period_bytes_min = 64,
  1179. .period_bytes_max = 65536,
  1180. .periods_min = 1,
  1181. .periods_max = 1024,
  1182. .fifo_size = 0,
  1183. };
  1184. static unsigned int snd_azf3328_fixed_rates[] = {
  1185. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1186. 44100, 48000, 66200 };
  1187. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1188. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1189. .list = snd_azf3328_fixed_rates,
  1190. .mask = 0,
  1191. };
  1192. /*****************************************************************/
  1193. static int
  1194. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1195. {
  1196. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1197. struct snd_pcm_runtime *runtime = substream->runtime;
  1198. snd_azf3328_dbgcallenter();
  1199. chip->playback_substream = substream;
  1200. runtime->hw = snd_azf3328_playback;
  1201. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1202. &snd_azf3328_hw_constraints_rates);
  1203. snd_azf3328_dbgcallleave();
  1204. return 0;
  1205. }
  1206. static int
  1207. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1208. {
  1209. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1210. struct snd_pcm_runtime *runtime = substream->runtime;
  1211. snd_azf3328_dbgcallenter();
  1212. chip->capture_substream = substream;
  1213. runtime->hw = snd_azf3328_capture;
  1214. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1215. &snd_azf3328_hw_constraints_rates);
  1216. snd_azf3328_dbgcallleave();
  1217. return 0;
  1218. }
  1219. static int
  1220. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1221. {
  1222. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1223. snd_azf3328_dbgcallenter();
  1224. chip->playback_substream = NULL;
  1225. snd_azf3328_dbgcallleave();
  1226. return 0;
  1227. }
  1228. static int
  1229. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1230. {
  1231. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1232. snd_azf3328_dbgcallenter();
  1233. chip->capture_substream = NULL;
  1234. snd_azf3328_dbgcallleave();
  1235. return 0;
  1236. }
  1237. /******************************************************************/
  1238. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1239. .open = snd_azf3328_playback_open,
  1240. .close = snd_azf3328_playback_close,
  1241. .ioctl = snd_pcm_lib_ioctl,
  1242. .hw_params = snd_azf3328_hw_params,
  1243. .hw_free = snd_azf3328_hw_free,
  1244. .prepare = snd_azf3328_playback_prepare,
  1245. .trigger = snd_azf3328_playback_trigger,
  1246. .pointer = snd_azf3328_playback_pointer
  1247. };
  1248. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1249. .open = snd_azf3328_capture_open,
  1250. .close = snd_azf3328_capture_close,
  1251. .ioctl = snd_pcm_lib_ioctl,
  1252. .hw_params = snd_azf3328_hw_params,
  1253. .hw_free = snd_azf3328_hw_free,
  1254. .prepare = snd_azf3328_capture_prepare,
  1255. .trigger = snd_azf3328_capture_trigger,
  1256. .pointer = snd_azf3328_capture_pointer
  1257. };
  1258. static int __devinit
  1259. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1260. {
  1261. struct snd_pcm *pcm;
  1262. int err;
  1263. snd_azf3328_dbgcallenter();
  1264. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1265. return err;
  1266. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1267. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1268. pcm->private_data = chip;
  1269. pcm->info_flags = 0;
  1270. strcpy(pcm->name, chip->card->shortname);
  1271. chip->pcm = pcm;
  1272. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1273. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1274. snd_azf3328_dbgcallleave();
  1275. return 0;
  1276. }
  1277. /******************************************************************/
  1278. #ifdef SUPPORT_JOYSTICK
  1279. static int __devinit
  1280. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1281. {
  1282. struct gameport *gp;
  1283. struct resource *r;
  1284. if (!joystick[dev])
  1285. return -ENODEV;
  1286. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1287. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1288. return -EBUSY;
  1289. }
  1290. chip->gameport = gp = gameport_allocate_port();
  1291. if (!gp) {
  1292. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1293. release_and_free_resource(r);
  1294. return -ENOMEM;
  1295. }
  1296. gameport_set_name(gp, "AZF3328 Gameport");
  1297. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1298. gameport_set_dev_parent(gp, &chip->pci->dev);
  1299. gp->io = 0x200;
  1300. gameport_set_port_data(gp, r);
  1301. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1302. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1303. gameport_register_port(chip->gameport);
  1304. return 0;
  1305. }
  1306. static void
  1307. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1308. {
  1309. if (chip->gameport) {
  1310. struct resource *r = gameport_get_port_data(chip->gameport);
  1311. gameport_unregister_port(chip->gameport);
  1312. chip->gameport = NULL;
  1313. /* disable gameport */
  1314. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1315. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1316. release_and_free_resource(r);
  1317. }
  1318. }
  1319. #else
  1320. static inline int
  1321. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1322. static inline void
  1323. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1324. #endif
  1325. /******************************************************************/
  1326. static int
  1327. snd_azf3328_free(struct snd_azf3328 *chip)
  1328. {
  1329. if (chip->irq < 0)
  1330. goto __end_hw;
  1331. /* reset (close) mixer */
  1332. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1333. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1334. /* interrupt setup - mask everything (FIXME!) */
  1335. /* well, at least we know how to disable the timer IRQ */
  1336. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1337. synchronize_irq(chip->irq);
  1338. __end_hw:
  1339. snd_azf3328_free_joystick(chip);
  1340. if (chip->irq >= 0)
  1341. free_irq(chip->irq, chip);
  1342. pci_release_regions(chip->pci);
  1343. pci_disable_device(chip->pci);
  1344. kfree(chip);
  1345. return 0;
  1346. }
  1347. static int
  1348. snd_azf3328_dev_free(struct snd_device *device)
  1349. {
  1350. struct snd_azf3328 *chip = device->device_data;
  1351. return snd_azf3328_free(chip);
  1352. }
  1353. /******************************************************************/
  1354. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1355. *** but announcing those attributes to user-space would make programs
  1356. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1357. *** timer IRQ storm.
  1358. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1359. *** calculate real timer countdown values internally.
  1360. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1361. ***/
  1362. static int
  1363. snd_azf3328_timer_start(struct snd_timer *timer)
  1364. {
  1365. struct snd_azf3328 *chip;
  1366. unsigned long flags;
  1367. unsigned int delay;
  1368. snd_azf3328_dbgcallenter();
  1369. chip = snd_timer_chip(timer);
  1370. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1371. if (delay < 49) {
  1372. /* uhoh, that's not good, since user-space won't know about
  1373. * this timing tweak
  1374. * (we need to do it to avoid a lockup, though) */
  1375. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1376. delay = 49; /* minimum time is 49 ticks */
  1377. }
  1378. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1379. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1380. spin_lock_irqsave(&chip->reg_lock, flags);
  1381. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1382. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1383. snd_azf3328_dbgcallleave();
  1384. return 0;
  1385. }
  1386. static int
  1387. snd_azf3328_timer_stop(struct snd_timer *timer)
  1388. {
  1389. struct snd_azf3328 *chip;
  1390. unsigned long flags;
  1391. snd_azf3328_dbgcallenter();
  1392. chip = snd_timer_chip(timer);
  1393. spin_lock_irqsave(&chip->reg_lock, flags);
  1394. /* disable timer countdown and interrupt */
  1395. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1396. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1397. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1398. snd_azf3328_dbgcallleave();
  1399. return 0;
  1400. }
  1401. static int
  1402. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1403. unsigned long *num, unsigned long *den)
  1404. {
  1405. snd_azf3328_dbgcallenter();
  1406. *num = 1;
  1407. *den = 1024000 / seqtimer_scaling;
  1408. snd_azf3328_dbgcallleave();
  1409. return 0;
  1410. }
  1411. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1412. .flags = SNDRV_TIMER_HW_AUTO,
  1413. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1414. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1415. .start = snd_azf3328_timer_start,
  1416. .stop = snd_azf3328_timer_stop,
  1417. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1418. };
  1419. static int __devinit
  1420. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1421. {
  1422. struct snd_timer *timer = NULL;
  1423. struct snd_timer_id tid;
  1424. int err;
  1425. snd_azf3328_dbgcallenter();
  1426. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1427. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1428. tid.card = chip->card->number;
  1429. tid.device = device;
  1430. tid.subdevice = 0;
  1431. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1432. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1433. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1434. goto out;
  1435. }
  1436. strcpy(timer->name, "AZF3328 timer");
  1437. timer->private_data = chip;
  1438. timer->hw = snd_azf3328_timer_hw;
  1439. chip->timer = timer;
  1440. err = 0;
  1441. out:
  1442. snd_azf3328_dbgcallleave();
  1443. return err;
  1444. }
  1445. /******************************************************************/
  1446. #if 0
  1447. /* check whether a bit can be modified */
  1448. static void
  1449. snd_azf3328_test_bit(unsigned int reg, int bit)
  1450. {
  1451. unsigned char val, valoff, valon;
  1452. val = inb(reg);
  1453. outb(val & ~(1 << bit), reg);
  1454. valoff = inb(reg);
  1455. outb(val|(1 << bit), reg);
  1456. valon = inb(reg);
  1457. outb(val, reg);
  1458. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1459. }
  1460. #endif
  1461. #if DEBUG_MISC
  1462. static void
  1463. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1464. {
  1465. u16 tmp;
  1466. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1467. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1468. for (tmp=0; tmp <= 0x01; tmp += 1)
  1469. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1470. for (tmp = 0; tmp < AZF_IO_SIZE_CODEC; tmp += 2)
  1471. snd_azf3328_dbgmisc("codec 0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inw(chip, tmp));
  1472. for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
  1473. snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n", tmp, snd_azf3328_mixer_inw(chip, tmp));
  1474. }
  1475. #else
  1476. static inline void
  1477. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) {}
  1478. #endif
  1479. static int __devinit
  1480. snd_azf3328_create(struct snd_card *card,
  1481. struct pci_dev *pci,
  1482. unsigned long device_type,
  1483. struct snd_azf3328 ** rchip)
  1484. {
  1485. struct snd_azf3328 *chip;
  1486. int err;
  1487. static struct snd_device_ops ops = {
  1488. .dev_free = snd_azf3328_dev_free,
  1489. };
  1490. u16 tmp;
  1491. *rchip = NULL;
  1492. if ((err = pci_enable_device(pci)) < 0)
  1493. return err;
  1494. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1495. if (chip == NULL) {
  1496. err = -ENOMEM;
  1497. goto out_err;
  1498. }
  1499. spin_lock_init(&chip->reg_lock);
  1500. chip->card = card;
  1501. chip->pci = pci;
  1502. chip->irq = -1;
  1503. /* check if we can restrict PCI DMA transfers to 24 bits */
  1504. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1505. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1506. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1507. err = -ENXIO;
  1508. goto out_err;
  1509. }
  1510. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1511. goto out_err;
  1512. }
  1513. chip->codec_port = pci_resource_start(pci, 0);
  1514. chip->io2_port = pci_resource_start(pci, 1);
  1515. chip->mpu_port = pci_resource_start(pci, 2);
  1516. chip->synth_port = pci_resource_start(pci, 3);
  1517. chip->mixer_port = pci_resource_start(pci, 4);
  1518. if (request_irq(pci->irq, snd_azf3328_interrupt,
  1519. IRQF_SHARED, card->shortname, chip)) {
  1520. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1521. err = -EBUSY;
  1522. goto out_err;
  1523. }
  1524. chip->irq = pci->irq;
  1525. pci_set_master(pci);
  1526. synchronize_irq(chip->irq);
  1527. snd_azf3328_debug_show_ports(chip);
  1528. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1529. goto out_err;
  1530. }
  1531. /* create mixer interface & switches */
  1532. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1533. goto out_err;
  1534. #if 0
  1535. /* set very low bitrate to reduce noise and power consumption? */
  1536. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1537. #endif
  1538. /* standard chip init stuff */
  1539. /* default IRQ init value */
  1540. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1541. spin_lock_irq(&chip->reg_lock);
  1542. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1543. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1544. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1545. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1546. spin_unlock_irq(&chip->reg_lock);
  1547. snd_card_set_dev(card, &pci->dev);
  1548. *rchip = chip;
  1549. err = 0;
  1550. goto out;
  1551. out_err:
  1552. if (chip)
  1553. snd_azf3328_free(chip);
  1554. pci_disable_device(pci);
  1555. out:
  1556. return err;
  1557. }
  1558. static int __devinit
  1559. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1560. {
  1561. static int dev;
  1562. struct snd_card *card;
  1563. struct snd_azf3328 *chip;
  1564. struct snd_opl3 *opl3;
  1565. int err;
  1566. snd_azf3328_dbgcallenter();
  1567. if (dev >= SNDRV_CARDS)
  1568. return -ENODEV;
  1569. if (!enable[dev]) {
  1570. dev++;
  1571. return -ENOENT;
  1572. }
  1573. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1574. if (card == NULL)
  1575. return -ENOMEM;
  1576. strcpy(card->driver, "AZF3328");
  1577. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1578. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1579. goto out_err;
  1580. }
  1581. card->private_data = chip;
  1582. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1583. chip->mpu_port, MPU401_INFO_INTEGRATED,
  1584. pci->irq, 0, &chip->rmidi)) < 0) {
  1585. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1586. goto out_err;
  1587. }
  1588. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1589. goto out_err;
  1590. }
  1591. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1592. goto out_err;
  1593. }
  1594. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1595. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1596. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1597. chip->synth_port, chip->synth_port+2 );
  1598. } else {
  1599. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1600. goto out_err;
  1601. }
  1602. }
  1603. opl3->private_data = chip;
  1604. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1605. card->shortname, chip->codec_port, chip->irq);
  1606. if ((err = snd_card_register(card)) < 0) {
  1607. goto out_err;
  1608. }
  1609. #ifdef MODULE
  1610. printk(
  1611. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
  1612. "azt3328: Hardware was completely undocumented, unfortunately.\n"
  1613. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1614. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1615. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1616. #endif
  1617. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1618. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1619. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1620. pci_set_drvdata(pci, card);
  1621. dev++;
  1622. err = 0;
  1623. goto out;
  1624. out_err:
  1625. snd_card_free(card);
  1626. out:
  1627. snd_azf3328_dbgcallleave();
  1628. return err;
  1629. }
  1630. static void __devexit
  1631. snd_azf3328_remove(struct pci_dev *pci)
  1632. {
  1633. snd_azf3328_dbgcallenter();
  1634. snd_card_free(pci_get_drvdata(pci));
  1635. pci_set_drvdata(pci, NULL);
  1636. snd_azf3328_dbgcallleave();
  1637. }
  1638. #ifdef CONFIG_PM
  1639. static int
  1640. snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
  1641. {
  1642. struct snd_card *card = pci_get_drvdata(pci);
  1643. struct snd_azf3328 *chip = card->private_data;
  1644. int reg;
  1645. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1646. snd_pcm_suspend_all(chip->pcm);
  1647. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1648. chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2);
  1649. /* make sure to disable master volume etc. to prevent looping sound */
  1650. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
  1651. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  1652. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1653. chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2);
  1654. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1655. chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2);
  1656. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1657. chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2);
  1658. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1659. chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2);
  1660. pci_disable_device(pci);
  1661. pci_save_state(pci);
  1662. pci_set_power_state(pci, pci_choose_state(pci, state));
  1663. return 0;
  1664. }
  1665. static int
  1666. snd_azf3328_resume(struct pci_dev *pci)
  1667. {
  1668. struct snd_card *card = pci_get_drvdata(pci);
  1669. struct snd_azf3328 *chip = card->private_data;
  1670. int reg;
  1671. pci_set_power_state(pci, PCI_D0);
  1672. pci_restore_state(pci);
  1673. if (pci_enable_device(pci) < 0) {
  1674. printk(KERN_ERR "azt3328: pci_enable_device failed, "
  1675. "disabling device\n");
  1676. snd_card_disconnect(card);
  1677. return -EIO;
  1678. }
  1679. pci_set_master(pci);
  1680. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1681. outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2);
  1682. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1683. outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2);
  1684. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1685. outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2);
  1686. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1687. outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2);
  1688. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1689. outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2);
  1690. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1691. return 0;
  1692. }
  1693. #endif
  1694. static struct pci_driver driver = {
  1695. .name = "AZF3328",
  1696. .id_table = snd_azf3328_ids,
  1697. .probe = snd_azf3328_probe,
  1698. .remove = __devexit_p(snd_azf3328_remove),
  1699. #ifdef CONFIG_PM
  1700. .suspend = snd_azf3328_suspend,
  1701. .resume = snd_azf3328_resume,
  1702. #endif
  1703. };
  1704. static int __init
  1705. alsa_card_azf3328_init(void)
  1706. {
  1707. int err;
  1708. snd_azf3328_dbgcallenter();
  1709. err = pci_register_driver(&driver);
  1710. snd_azf3328_dbgcallleave();
  1711. return err;
  1712. }
  1713. static void __exit
  1714. alsa_card_azf3328_exit(void)
  1715. {
  1716. snd_azf3328_dbgcallenter();
  1717. pci_unregister_driver(&driver);
  1718. snd_azf3328_dbgcallleave();
  1719. }
  1720. module_init(alsa_card_azf3328_init)
  1721. module_exit(alsa_card_azf3328_exit)