main.c 119 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  4. Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  6. Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  7. Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  8. Some parts of the code in this file are derived from the ipw2200
  9. driver Copyright(c) 2003 - 2004 Intel Corporation.
  10. This program is free software; you can redistribute it and/or modify
  11. it under the terms of the GNU General Public License as published by
  12. the Free Software Foundation; either version 2 of the License, or
  13. (at your option) any later version.
  14. This program is distributed in the hope that it will be useful,
  15. but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. GNU General Public License for more details.
  18. You should have received a copy of the GNU General Public License
  19. along with this program; see the file COPYING. If not, write to
  20. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21. Boston, MA 02110-1301, USA.
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/if_arp.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/version.h>
  29. #include <linux/firmware.h>
  30. #include <linux/wireless.h>
  31. #include <linux/workqueue.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/io.h>
  34. #include <linux/dma-mapping.h>
  35. #include <asm/unaligned.h>
  36. #include "b43.h"
  37. #include "main.h"
  38. #include "debugfs.h"
  39. #include "phy.h"
  40. #include "nphy.h"
  41. #include "dma.h"
  42. #include "pio.h"
  43. #include "sysfs.h"
  44. #include "xmit.h"
  45. #include "lo.h"
  46. #include "pcmcia.h"
  47. MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  48. MODULE_AUTHOR("Martin Langer");
  49. MODULE_AUTHOR("Stefano Brivio");
  50. MODULE_AUTHOR("Michael Buesch");
  51. MODULE_LICENSE("GPL");
  52. MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
  53. static int modparam_bad_frames_preempt;
  54. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  55. MODULE_PARM_DESC(bad_frames_preempt,
  56. "enable(1) / disable(0) Bad Frames Preemption");
  57. static char modparam_fwpostfix[16];
  58. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  59. MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  60. static int modparam_hwpctl;
  61. module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  62. MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  63. static int modparam_nohwcrypt;
  64. module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  65. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  66. int b43_modparam_qos = 1;
  67. module_param_named(qos, b43_modparam_qos, int, 0444);
  68. MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
  69. static const struct ssb_device_id b43_ssb_tbl[] = {
  70. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  71. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  72. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  73. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  74. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  75. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  76. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  77. SSB_DEVTABLE_END
  78. };
  79. MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  80. /* Channel and ratetables are shared for all devices.
  81. * They can't be const, because ieee80211 puts some precalculated
  82. * data in there. This data is the same for all devices, so we don't
  83. * get concurrency issues */
  84. #define RATETAB_ENT(_rateid, _flags) \
  85. { \
  86. .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
  87. .hw_value = (_rateid), \
  88. .flags = (_flags), \
  89. }
  90. /*
  91. * NOTE: When changing this, sync with xmit.c's
  92. * b43_plcp_get_bitrate_idx_* functions!
  93. */
  94. static struct ieee80211_rate __b43_ratetable[] = {
  95. RATETAB_ENT(B43_CCK_RATE_1MB, 0),
  96. RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
  97. RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
  98. RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
  99. RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
  100. RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
  101. RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
  102. RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
  103. RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
  104. RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
  105. RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
  106. RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
  107. };
  108. #define b43_a_ratetable (__b43_ratetable + 4)
  109. #define b43_a_ratetable_size 8
  110. #define b43_b_ratetable (__b43_ratetable + 0)
  111. #define b43_b_ratetable_size 4
  112. #define b43_g_ratetable (__b43_ratetable + 0)
  113. #define b43_g_ratetable_size 12
  114. #define CHAN4G(_channel, _freq, _flags) { \
  115. .band = IEEE80211_BAND_2GHZ, \
  116. .center_freq = (_freq), \
  117. .hw_value = (_channel), \
  118. .flags = (_flags), \
  119. .max_antenna_gain = 0, \
  120. .max_power = 30, \
  121. }
  122. static struct ieee80211_channel b43_2ghz_chantable[] = {
  123. CHAN4G(1, 2412, 0),
  124. CHAN4G(2, 2417, 0),
  125. CHAN4G(3, 2422, 0),
  126. CHAN4G(4, 2427, 0),
  127. CHAN4G(5, 2432, 0),
  128. CHAN4G(6, 2437, 0),
  129. CHAN4G(7, 2442, 0),
  130. CHAN4G(8, 2447, 0),
  131. CHAN4G(9, 2452, 0),
  132. CHAN4G(10, 2457, 0),
  133. CHAN4G(11, 2462, 0),
  134. CHAN4G(12, 2467, 0),
  135. CHAN4G(13, 2472, 0),
  136. CHAN4G(14, 2484, 0),
  137. };
  138. #undef CHAN4G
  139. #define CHAN5G(_channel, _flags) { \
  140. .band = IEEE80211_BAND_5GHZ, \
  141. .center_freq = 5000 + (5 * (_channel)), \
  142. .hw_value = (_channel), \
  143. .flags = (_flags), \
  144. .max_antenna_gain = 0, \
  145. .max_power = 30, \
  146. }
  147. static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
  148. CHAN5G(32, 0), CHAN5G(34, 0),
  149. CHAN5G(36, 0), CHAN5G(38, 0),
  150. CHAN5G(40, 0), CHAN5G(42, 0),
  151. CHAN5G(44, 0), CHAN5G(46, 0),
  152. CHAN5G(48, 0), CHAN5G(50, 0),
  153. CHAN5G(52, 0), CHAN5G(54, 0),
  154. CHAN5G(56, 0), CHAN5G(58, 0),
  155. CHAN5G(60, 0), CHAN5G(62, 0),
  156. CHAN5G(64, 0), CHAN5G(66, 0),
  157. CHAN5G(68, 0), CHAN5G(70, 0),
  158. CHAN5G(72, 0), CHAN5G(74, 0),
  159. CHAN5G(76, 0), CHAN5G(78, 0),
  160. CHAN5G(80, 0), CHAN5G(82, 0),
  161. CHAN5G(84, 0), CHAN5G(86, 0),
  162. CHAN5G(88, 0), CHAN5G(90, 0),
  163. CHAN5G(92, 0), CHAN5G(94, 0),
  164. CHAN5G(96, 0), CHAN5G(98, 0),
  165. CHAN5G(100, 0), CHAN5G(102, 0),
  166. CHAN5G(104, 0), CHAN5G(106, 0),
  167. CHAN5G(108, 0), CHAN5G(110, 0),
  168. CHAN5G(112, 0), CHAN5G(114, 0),
  169. CHAN5G(116, 0), CHAN5G(118, 0),
  170. CHAN5G(120, 0), CHAN5G(122, 0),
  171. CHAN5G(124, 0), CHAN5G(126, 0),
  172. CHAN5G(128, 0), CHAN5G(130, 0),
  173. CHAN5G(132, 0), CHAN5G(134, 0),
  174. CHAN5G(136, 0), CHAN5G(138, 0),
  175. CHAN5G(140, 0), CHAN5G(142, 0),
  176. CHAN5G(144, 0), CHAN5G(145, 0),
  177. CHAN5G(146, 0), CHAN5G(147, 0),
  178. CHAN5G(148, 0), CHAN5G(149, 0),
  179. CHAN5G(150, 0), CHAN5G(151, 0),
  180. CHAN5G(152, 0), CHAN5G(153, 0),
  181. CHAN5G(154, 0), CHAN5G(155, 0),
  182. CHAN5G(156, 0), CHAN5G(157, 0),
  183. CHAN5G(158, 0), CHAN5G(159, 0),
  184. CHAN5G(160, 0), CHAN5G(161, 0),
  185. CHAN5G(162, 0), CHAN5G(163, 0),
  186. CHAN5G(164, 0), CHAN5G(165, 0),
  187. CHAN5G(166, 0), CHAN5G(168, 0),
  188. CHAN5G(170, 0), CHAN5G(172, 0),
  189. CHAN5G(174, 0), CHAN5G(176, 0),
  190. CHAN5G(178, 0), CHAN5G(180, 0),
  191. CHAN5G(182, 0), CHAN5G(184, 0),
  192. CHAN5G(186, 0), CHAN5G(188, 0),
  193. CHAN5G(190, 0), CHAN5G(192, 0),
  194. CHAN5G(194, 0), CHAN5G(196, 0),
  195. CHAN5G(198, 0), CHAN5G(200, 0),
  196. CHAN5G(202, 0), CHAN5G(204, 0),
  197. CHAN5G(206, 0), CHAN5G(208, 0),
  198. CHAN5G(210, 0), CHAN5G(212, 0),
  199. CHAN5G(214, 0), CHAN5G(216, 0),
  200. CHAN5G(218, 0), CHAN5G(220, 0),
  201. CHAN5G(222, 0), CHAN5G(224, 0),
  202. CHAN5G(226, 0), CHAN5G(228, 0),
  203. };
  204. static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
  205. CHAN5G(34, 0), CHAN5G(36, 0),
  206. CHAN5G(38, 0), CHAN5G(40, 0),
  207. CHAN5G(42, 0), CHAN5G(44, 0),
  208. CHAN5G(46, 0), CHAN5G(48, 0),
  209. CHAN5G(52, 0), CHAN5G(56, 0),
  210. CHAN5G(60, 0), CHAN5G(64, 0),
  211. CHAN5G(100, 0), CHAN5G(104, 0),
  212. CHAN5G(108, 0), CHAN5G(112, 0),
  213. CHAN5G(116, 0), CHAN5G(120, 0),
  214. CHAN5G(124, 0), CHAN5G(128, 0),
  215. CHAN5G(132, 0), CHAN5G(136, 0),
  216. CHAN5G(140, 0), CHAN5G(149, 0),
  217. CHAN5G(153, 0), CHAN5G(157, 0),
  218. CHAN5G(161, 0), CHAN5G(165, 0),
  219. CHAN5G(184, 0), CHAN5G(188, 0),
  220. CHAN5G(192, 0), CHAN5G(196, 0),
  221. CHAN5G(200, 0), CHAN5G(204, 0),
  222. CHAN5G(208, 0), CHAN5G(212, 0),
  223. CHAN5G(216, 0),
  224. };
  225. #undef CHAN5G
  226. static struct ieee80211_supported_band b43_band_5GHz_nphy = {
  227. .band = IEEE80211_BAND_5GHZ,
  228. .channels = b43_5ghz_nphy_chantable,
  229. .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
  230. .bitrates = b43_a_ratetable,
  231. .n_bitrates = b43_a_ratetable_size,
  232. };
  233. static struct ieee80211_supported_band b43_band_5GHz_aphy = {
  234. .band = IEEE80211_BAND_5GHZ,
  235. .channels = b43_5ghz_aphy_chantable,
  236. .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
  237. .bitrates = b43_a_ratetable,
  238. .n_bitrates = b43_a_ratetable_size,
  239. };
  240. static struct ieee80211_supported_band b43_band_2GHz = {
  241. .band = IEEE80211_BAND_2GHZ,
  242. .channels = b43_2ghz_chantable,
  243. .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
  244. .bitrates = b43_g_ratetable,
  245. .n_bitrates = b43_g_ratetable_size,
  246. };
  247. static void b43_wireless_core_exit(struct b43_wldev *dev);
  248. static int b43_wireless_core_init(struct b43_wldev *dev);
  249. static void b43_wireless_core_stop(struct b43_wldev *dev);
  250. static int b43_wireless_core_start(struct b43_wldev *dev);
  251. static int b43_ratelimit(struct b43_wl *wl)
  252. {
  253. if (!wl || !wl->current_dev)
  254. return 1;
  255. if (b43_status(wl->current_dev) < B43_STAT_STARTED)
  256. return 1;
  257. /* We are up and running.
  258. * Ratelimit the messages to avoid DoS over the net. */
  259. return net_ratelimit();
  260. }
  261. void b43info(struct b43_wl *wl, const char *fmt, ...)
  262. {
  263. va_list args;
  264. if (!b43_ratelimit(wl))
  265. return;
  266. va_start(args, fmt);
  267. printk(KERN_INFO "b43-%s: ",
  268. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  269. vprintk(fmt, args);
  270. va_end(args);
  271. }
  272. void b43err(struct b43_wl *wl, const char *fmt, ...)
  273. {
  274. va_list args;
  275. if (!b43_ratelimit(wl))
  276. return;
  277. va_start(args, fmt);
  278. printk(KERN_ERR "b43-%s ERROR: ",
  279. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  280. vprintk(fmt, args);
  281. va_end(args);
  282. }
  283. void b43warn(struct b43_wl *wl, const char *fmt, ...)
  284. {
  285. va_list args;
  286. if (!b43_ratelimit(wl))
  287. return;
  288. va_start(args, fmt);
  289. printk(KERN_WARNING "b43-%s warning: ",
  290. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  291. vprintk(fmt, args);
  292. va_end(args);
  293. }
  294. #if B43_DEBUG
  295. void b43dbg(struct b43_wl *wl, const char *fmt, ...)
  296. {
  297. va_list args;
  298. va_start(args, fmt);
  299. printk(KERN_DEBUG "b43-%s debug: ",
  300. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  301. vprintk(fmt, args);
  302. va_end(args);
  303. }
  304. #endif /* DEBUG */
  305. static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
  306. {
  307. u32 macctl;
  308. B43_WARN_ON(offset % 4 != 0);
  309. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  310. if (macctl & B43_MACCTL_BE)
  311. val = swab32(val);
  312. b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
  313. mmiowb();
  314. b43_write32(dev, B43_MMIO_RAM_DATA, val);
  315. }
  316. static inline void b43_shm_control_word(struct b43_wldev *dev,
  317. u16 routing, u16 offset)
  318. {
  319. u32 control;
  320. /* "offset" is the WORD offset. */
  321. control = routing;
  322. control <<= 16;
  323. control |= offset;
  324. b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
  325. }
  326. u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
  327. {
  328. struct b43_wl *wl = dev->wl;
  329. unsigned long flags;
  330. u32 ret;
  331. spin_lock_irqsave(&wl->shm_lock, flags);
  332. if (routing == B43_SHM_SHARED) {
  333. B43_WARN_ON(offset & 0x0001);
  334. if (offset & 0x0003) {
  335. /* Unaligned access */
  336. b43_shm_control_word(dev, routing, offset >> 2);
  337. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  338. ret <<= 16;
  339. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  340. ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
  341. goto out;
  342. }
  343. offset >>= 2;
  344. }
  345. b43_shm_control_word(dev, routing, offset);
  346. ret = b43_read32(dev, B43_MMIO_SHM_DATA);
  347. out:
  348. spin_unlock_irqrestore(&wl->shm_lock, flags);
  349. return ret;
  350. }
  351. u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
  352. {
  353. struct b43_wl *wl = dev->wl;
  354. unsigned long flags;
  355. u16 ret;
  356. spin_lock_irqsave(&wl->shm_lock, flags);
  357. if (routing == B43_SHM_SHARED) {
  358. B43_WARN_ON(offset & 0x0001);
  359. if (offset & 0x0003) {
  360. /* Unaligned access */
  361. b43_shm_control_word(dev, routing, offset >> 2);
  362. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  363. goto out;
  364. }
  365. offset >>= 2;
  366. }
  367. b43_shm_control_word(dev, routing, offset);
  368. ret = b43_read16(dev, B43_MMIO_SHM_DATA);
  369. out:
  370. spin_unlock_irqrestore(&wl->shm_lock, flags);
  371. return ret;
  372. }
  373. void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
  374. {
  375. struct b43_wl *wl = dev->wl;
  376. unsigned long flags;
  377. spin_lock_irqsave(&wl->shm_lock, flags);
  378. if (routing == B43_SHM_SHARED) {
  379. B43_WARN_ON(offset & 0x0001);
  380. if (offset & 0x0003) {
  381. /* Unaligned access */
  382. b43_shm_control_word(dev, routing, offset >> 2);
  383. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
  384. (value >> 16) & 0xffff);
  385. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  386. b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
  387. goto out;
  388. }
  389. offset >>= 2;
  390. }
  391. b43_shm_control_word(dev, routing, offset);
  392. b43_write32(dev, B43_MMIO_SHM_DATA, value);
  393. out:
  394. spin_unlock_irqrestore(&wl->shm_lock, flags);
  395. }
  396. void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
  397. {
  398. struct b43_wl *wl = dev->wl;
  399. unsigned long flags;
  400. spin_lock_irqsave(&wl->shm_lock, flags);
  401. if (routing == B43_SHM_SHARED) {
  402. B43_WARN_ON(offset & 0x0001);
  403. if (offset & 0x0003) {
  404. /* Unaligned access */
  405. b43_shm_control_word(dev, routing, offset >> 2);
  406. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
  407. goto out;
  408. }
  409. offset >>= 2;
  410. }
  411. b43_shm_control_word(dev, routing, offset);
  412. b43_write16(dev, B43_MMIO_SHM_DATA, value);
  413. out:
  414. spin_unlock_irqrestore(&wl->shm_lock, flags);
  415. }
  416. /* Read HostFlags */
  417. u64 b43_hf_read(struct b43_wldev * dev)
  418. {
  419. u64 ret;
  420. ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
  421. ret <<= 16;
  422. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
  423. ret <<= 16;
  424. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
  425. return ret;
  426. }
  427. /* Write HostFlags */
  428. void b43_hf_write(struct b43_wldev *dev, u64 value)
  429. {
  430. u16 lo, mi, hi;
  431. lo = (value & 0x00000000FFFFULL);
  432. mi = (value & 0x0000FFFF0000ULL) >> 16;
  433. hi = (value & 0xFFFF00000000ULL) >> 32;
  434. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
  435. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
  436. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
  437. }
  438. void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
  439. {
  440. /* We need to be careful. As we read the TSF from multiple
  441. * registers, we should take care of register overflows.
  442. * In theory, the whole tsf read process should be atomic.
  443. * We try to be atomic here, by restaring the read process,
  444. * if any of the high registers changed (overflew).
  445. */
  446. if (dev->dev->id.revision >= 3) {
  447. u32 low, high, high2;
  448. do {
  449. high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
  450. low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
  451. high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
  452. } while (unlikely(high != high2));
  453. *tsf = high;
  454. *tsf <<= 32;
  455. *tsf |= low;
  456. } else {
  457. u64 tmp;
  458. u16 v0, v1, v2, v3;
  459. u16 test1, test2, test3;
  460. do {
  461. v3 = b43_read16(dev, B43_MMIO_TSF_3);
  462. v2 = b43_read16(dev, B43_MMIO_TSF_2);
  463. v1 = b43_read16(dev, B43_MMIO_TSF_1);
  464. v0 = b43_read16(dev, B43_MMIO_TSF_0);
  465. test3 = b43_read16(dev, B43_MMIO_TSF_3);
  466. test2 = b43_read16(dev, B43_MMIO_TSF_2);
  467. test1 = b43_read16(dev, B43_MMIO_TSF_1);
  468. } while (v3 != test3 || v2 != test2 || v1 != test1);
  469. *tsf = v3;
  470. *tsf <<= 48;
  471. tmp = v2;
  472. tmp <<= 32;
  473. *tsf |= tmp;
  474. tmp = v1;
  475. tmp <<= 16;
  476. *tsf |= tmp;
  477. *tsf |= v0;
  478. }
  479. }
  480. static void b43_time_lock(struct b43_wldev *dev)
  481. {
  482. u32 macctl;
  483. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  484. macctl |= B43_MACCTL_TBTTHOLD;
  485. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  486. /* Commit the write */
  487. b43_read32(dev, B43_MMIO_MACCTL);
  488. }
  489. static void b43_time_unlock(struct b43_wldev *dev)
  490. {
  491. u32 macctl;
  492. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  493. macctl &= ~B43_MACCTL_TBTTHOLD;
  494. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  495. /* Commit the write */
  496. b43_read32(dev, B43_MMIO_MACCTL);
  497. }
  498. static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
  499. {
  500. /* Be careful with the in-progress timer.
  501. * First zero out the low register, so we have a full
  502. * register-overflow duration to complete the operation.
  503. */
  504. if (dev->dev->id.revision >= 3) {
  505. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  506. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  507. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
  508. mmiowb();
  509. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
  510. mmiowb();
  511. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
  512. } else {
  513. u16 v0 = (tsf & 0x000000000000FFFFULL);
  514. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  515. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  516. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  517. b43_write16(dev, B43_MMIO_TSF_0, 0);
  518. mmiowb();
  519. b43_write16(dev, B43_MMIO_TSF_3, v3);
  520. mmiowb();
  521. b43_write16(dev, B43_MMIO_TSF_2, v2);
  522. mmiowb();
  523. b43_write16(dev, B43_MMIO_TSF_1, v1);
  524. mmiowb();
  525. b43_write16(dev, B43_MMIO_TSF_0, v0);
  526. }
  527. }
  528. void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
  529. {
  530. b43_time_lock(dev);
  531. b43_tsf_write_locked(dev, tsf);
  532. b43_time_unlock(dev);
  533. }
  534. static
  535. void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
  536. {
  537. static const u8 zero_addr[ETH_ALEN] = { 0 };
  538. u16 data;
  539. if (!mac)
  540. mac = zero_addr;
  541. offset |= 0x0020;
  542. b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
  543. data = mac[0];
  544. data |= mac[1] << 8;
  545. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  546. data = mac[2];
  547. data |= mac[3] << 8;
  548. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  549. data = mac[4];
  550. data |= mac[5] << 8;
  551. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  552. }
  553. static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
  554. {
  555. const u8 *mac;
  556. const u8 *bssid;
  557. u8 mac_bssid[ETH_ALEN * 2];
  558. int i;
  559. u32 tmp;
  560. bssid = dev->wl->bssid;
  561. mac = dev->wl->mac_addr;
  562. b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
  563. memcpy(mac_bssid, mac, ETH_ALEN);
  564. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  565. /* Write our MAC address and BSSID to template ram */
  566. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  567. tmp = (u32) (mac_bssid[i + 0]);
  568. tmp |= (u32) (mac_bssid[i + 1]) << 8;
  569. tmp |= (u32) (mac_bssid[i + 2]) << 16;
  570. tmp |= (u32) (mac_bssid[i + 3]) << 24;
  571. b43_ram_write(dev, 0x20 + i, tmp);
  572. }
  573. }
  574. static void b43_upload_card_macaddress(struct b43_wldev *dev)
  575. {
  576. b43_write_mac_bssid_templates(dev);
  577. b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
  578. }
  579. static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
  580. {
  581. /* slot_time is in usec. */
  582. if (dev->phy.type != B43_PHYTYPE_G)
  583. return;
  584. b43_write16(dev, 0x684, 510 + slot_time);
  585. b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
  586. }
  587. static void b43_short_slot_timing_enable(struct b43_wldev *dev)
  588. {
  589. b43_set_slot_time(dev, 9);
  590. dev->short_slot = 1;
  591. }
  592. static void b43_short_slot_timing_disable(struct b43_wldev *dev)
  593. {
  594. b43_set_slot_time(dev, 20);
  595. dev->short_slot = 0;
  596. }
  597. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  598. * Returns the _previously_ enabled IRQ mask.
  599. */
  600. static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
  601. {
  602. u32 old_mask;
  603. old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  604. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
  605. return old_mask;
  606. }
  607. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  608. * Returns the _previously_ enabled IRQ mask.
  609. */
  610. static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
  611. {
  612. u32 old_mask;
  613. old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  614. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  615. return old_mask;
  616. }
  617. /* Synchronize IRQ top- and bottom-half.
  618. * IRQs must be masked before calling this.
  619. * This must not be called with the irq_lock held.
  620. */
  621. static void b43_synchronize_irq(struct b43_wldev *dev)
  622. {
  623. synchronize_irq(dev->dev->irq);
  624. tasklet_kill(&dev->isr_tasklet);
  625. }
  626. /* DummyTransmission function, as documented on
  627. * http://bcm-specs.sipsolutions.net/DummyTransmission
  628. */
  629. void b43_dummy_transmission(struct b43_wldev *dev)
  630. {
  631. struct b43_phy *phy = &dev->phy;
  632. unsigned int i, max_loop;
  633. u16 value;
  634. u32 buffer[5] = {
  635. 0x00000000,
  636. 0x00D40000,
  637. 0x00000000,
  638. 0x01000000,
  639. 0x00000000,
  640. };
  641. switch (phy->type) {
  642. case B43_PHYTYPE_A:
  643. max_loop = 0x1E;
  644. buffer[0] = 0x000201CC;
  645. break;
  646. case B43_PHYTYPE_B:
  647. case B43_PHYTYPE_G:
  648. max_loop = 0xFA;
  649. buffer[0] = 0x000B846E;
  650. break;
  651. default:
  652. B43_WARN_ON(1);
  653. return;
  654. }
  655. for (i = 0; i < 5; i++)
  656. b43_ram_write(dev, i * 4, buffer[i]);
  657. /* Commit writes */
  658. b43_read32(dev, B43_MMIO_MACCTL);
  659. b43_write16(dev, 0x0568, 0x0000);
  660. b43_write16(dev, 0x07C0, 0x0000);
  661. value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
  662. b43_write16(dev, 0x050C, value);
  663. b43_write16(dev, 0x0508, 0x0000);
  664. b43_write16(dev, 0x050A, 0x0000);
  665. b43_write16(dev, 0x054C, 0x0000);
  666. b43_write16(dev, 0x056A, 0x0014);
  667. b43_write16(dev, 0x0568, 0x0826);
  668. b43_write16(dev, 0x0500, 0x0000);
  669. b43_write16(dev, 0x0502, 0x0030);
  670. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  671. b43_radio_write16(dev, 0x0051, 0x0017);
  672. for (i = 0x00; i < max_loop; i++) {
  673. value = b43_read16(dev, 0x050E);
  674. if (value & 0x0080)
  675. break;
  676. udelay(10);
  677. }
  678. for (i = 0x00; i < 0x0A; i++) {
  679. value = b43_read16(dev, 0x050E);
  680. if (value & 0x0400)
  681. break;
  682. udelay(10);
  683. }
  684. for (i = 0x00; i < 0x0A; i++) {
  685. value = b43_read16(dev, 0x0690);
  686. if (!(value & 0x0100))
  687. break;
  688. udelay(10);
  689. }
  690. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  691. b43_radio_write16(dev, 0x0051, 0x0037);
  692. }
  693. static void key_write(struct b43_wldev *dev,
  694. u8 index, u8 algorithm, const u8 * key)
  695. {
  696. unsigned int i;
  697. u32 offset;
  698. u16 value;
  699. u16 kidx;
  700. /* Key index/algo block */
  701. kidx = b43_kidx_to_fw(dev, index);
  702. value = ((kidx << 4) | algorithm);
  703. b43_shm_write16(dev, B43_SHM_SHARED,
  704. B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
  705. /* Write the key to the Key Table Pointer offset */
  706. offset = dev->ktp + (index * B43_SEC_KEYSIZE);
  707. for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
  708. value = key[i];
  709. value |= (u16) (key[i + 1]) << 8;
  710. b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
  711. }
  712. }
  713. static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
  714. {
  715. u32 addrtmp[2] = { 0, 0, };
  716. u8 per_sta_keys_start = 8;
  717. if (b43_new_kidx_api(dev))
  718. per_sta_keys_start = 4;
  719. B43_WARN_ON(index < per_sta_keys_start);
  720. /* We have two default TX keys and possibly two default RX keys.
  721. * Physical mac 0 is mapped to physical key 4 or 8, depending
  722. * on the firmware version.
  723. * So we must adjust the index here.
  724. */
  725. index -= per_sta_keys_start;
  726. if (addr) {
  727. addrtmp[0] = addr[0];
  728. addrtmp[0] |= ((u32) (addr[1]) << 8);
  729. addrtmp[0] |= ((u32) (addr[2]) << 16);
  730. addrtmp[0] |= ((u32) (addr[3]) << 24);
  731. addrtmp[1] = addr[4];
  732. addrtmp[1] |= ((u32) (addr[5]) << 8);
  733. }
  734. if (dev->dev->id.revision >= 5) {
  735. /* Receive match transmitter address mechanism */
  736. b43_shm_write32(dev, B43_SHM_RCMTA,
  737. (index * 2) + 0, addrtmp[0]);
  738. b43_shm_write16(dev, B43_SHM_RCMTA,
  739. (index * 2) + 1, addrtmp[1]);
  740. } else {
  741. /* RXE (Receive Engine) and
  742. * PSM (Programmable State Machine) mechanism
  743. */
  744. if (index < 8) {
  745. /* TODO write to RCM 16, 19, 22 and 25 */
  746. } else {
  747. b43_shm_write32(dev, B43_SHM_SHARED,
  748. B43_SHM_SH_PSM + (index * 6) + 0,
  749. addrtmp[0]);
  750. b43_shm_write16(dev, B43_SHM_SHARED,
  751. B43_SHM_SH_PSM + (index * 6) + 4,
  752. addrtmp[1]);
  753. }
  754. }
  755. }
  756. static void do_key_write(struct b43_wldev *dev,
  757. u8 index, u8 algorithm,
  758. const u8 * key, size_t key_len, const u8 * mac_addr)
  759. {
  760. u8 buf[B43_SEC_KEYSIZE] = { 0, };
  761. u8 per_sta_keys_start = 8;
  762. if (b43_new_kidx_api(dev))
  763. per_sta_keys_start = 4;
  764. B43_WARN_ON(index >= dev->max_nr_keys);
  765. B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
  766. if (index >= per_sta_keys_start)
  767. keymac_write(dev, index, NULL); /* First zero out mac. */
  768. if (key)
  769. memcpy(buf, key, key_len);
  770. key_write(dev, index, algorithm, buf);
  771. if (index >= per_sta_keys_start)
  772. keymac_write(dev, index, mac_addr);
  773. dev->key[index].algorithm = algorithm;
  774. }
  775. static int b43_key_write(struct b43_wldev *dev,
  776. int index, u8 algorithm,
  777. const u8 * key, size_t key_len,
  778. const u8 * mac_addr,
  779. struct ieee80211_key_conf *keyconf)
  780. {
  781. int i;
  782. int sta_keys_start;
  783. if (key_len > B43_SEC_KEYSIZE)
  784. return -EINVAL;
  785. for (i = 0; i < dev->max_nr_keys; i++) {
  786. /* Check that we don't already have this key. */
  787. B43_WARN_ON(dev->key[i].keyconf == keyconf);
  788. }
  789. if (index < 0) {
  790. /* Either pairwise key or address is 00:00:00:00:00:00
  791. * for transmit-only keys. Search the index. */
  792. if (b43_new_kidx_api(dev))
  793. sta_keys_start = 4;
  794. else
  795. sta_keys_start = 8;
  796. for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
  797. if (!dev->key[i].keyconf) {
  798. /* found empty */
  799. index = i;
  800. break;
  801. }
  802. }
  803. if (index < 0) {
  804. b43err(dev->wl, "Out of hardware key memory\n");
  805. return -ENOSPC;
  806. }
  807. } else
  808. B43_WARN_ON(index > 3);
  809. do_key_write(dev, index, algorithm, key, key_len, mac_addr);
  810. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  811. /* Default RX key */
  812. B43_WARN_ON(mac_addr);
  813. do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
  814. }
  815. keyconf->hw_key_idx = index;
  816. dev->key[index].keyconf = keyconf;
  817. return 0;
  818. }
  819. static int b43_key_clear(struct b43_wldev *dev, int index)
  820. {
  821. if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
  822. return -EINVAL;
  823. do_key_write(dev, index, B43_SEC_ALGO_NONE,
  824. NULL, B43_SEC_KEYSIZE, NULL);
  825. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  826. do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
  827. NULL, B43_SEC_KEYSIZE, NULL);
  828. }
  829. dev->key[index].keyconf = NULL;
  830. return 0;
  831. }
  832. static void b43_clear_keys(struct b43_wldev *dev)
  833. {
  834. int i;
  835. for (i = 0; i < dev->max_nr_keys; i++)
  836. b43_key_clear(dev, i);
  837. }
  838. void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
  839. {
  840. u32 macctl;
  841. u16 ucstat;
  842. bool hwps;
  843. bool awake;
  844. int i;
  845. B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
  846. (ps_flags & B43_PS_DISABLED));
  847. B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
  848. if (ps_flags & B43_PS_ENABLED) {
  849. hwps = 1;
  850. } else if (ps_flags & B43_PS_DISABLED) {
  851. hwps = 0;
  852. } else {
  853. //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
  854. // and thus is not an AP and we are associated, set bit 25
  855. }
  856. if (ps_flags & B43_PS_AWAKE) {
  857. awake = 1;
  858. } else if (ps_flags & B43_PS_ASLEEP) {
  859. awake = 0;
  860. } else {
  861. //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
  862. // or we are associated, or FIXME, or the latest PS-Poll packet sent was
  863. // successful, set bit26
  864. }
  865. /* FIXME: For now we force awake-on and hwps-off */
  866. hwps = 0;
  867. awake = 1;
  868. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  869. if (hwps)
  870. macctl |= B43_MACCTL_HWPS;
  871. else
  872. macctl &= ~B43_MACCTL_HWPS;
  873. if (awake)
  874. macctl |= B43_MACCTL_AWAKE;
  875. else
  876. macctl &= ~B43_MACCTL_AWAKE;
  877. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  878. /* Commit write */
  879. b43_read32(dev, B43_MMIO_MACCTL);
  880. if (awake && dev->dev->id.revision >= 5) {
  881. /* Wait for the microcode to wake up. */
  882. for (i = 0; i < 100; i++) {
  883. ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
  884. B43_SHM_SH_UCODESTAT);
  885. if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
  886. break;
  887. udelay(10);
  888. }
  889. }
  890. }
  891. /* Turn the Analog ON/OFF */
  892. static void b43_switch_analog(struct b43_wldev *dev, int on)
  893. {
  894. switch (dev->phy.type) {
  895. case B43_PHYTYPE_A:
  896. case B43_PHYTYPE_G:
  897. b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
  898. break;
  899. case B43_PHYTYPE_N:
  900. b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
  901. on ? 0 : 0x7FFF);
  902. break;
  903. default:
  904. B43_WARN_ON(1);
  905. }
  906. }
  907. void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
  908. {
  909. u32 tmslow;
  910. u32 macctl;
  911. flags |= B43_TMSLOW_PHYCLKEN;
  912. flags |= B43_TMSLOW_PHYRESET;
  913. ssb_device_enable(dev->dev, flags);
  914. msleep(2); /* Wait for the PLL to turn on. */
  915. /* Now take the PHY out of Reset again */
  916. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  917. tmslow |= SSB_TMSLOW_FGC;
  918. tmslow &= ~B43_TMSLOW_PHYRESET;
  919. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  920. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  921. msleep(1);
  922. tmslow &= ~SSB_TMSLOW_FGC;
  923. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  924. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  925. msleep(1);
  926. /* Turn Analog ON */
  927. b43_switch_analog(dev, 1);
  928. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  929. macctl &= ~B43_MACCTL_GMODE;
  930. if (flags & B43_TMSLOW_GMODE)
  931. macctl |= B43_MACCTL_GMODE;
  932. macctl |= B43_MACCTL_IHR_ENABLED;
  933. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  934. }
  935. static void handle_irq_transmit_status(struct b43_wldev *dev)
  936. {
  937. u32 v0, v1;
  938. u16 tmp;
  939. struct b43_txstatus stat;
  940. while (1) {
  941. v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  942. if (!(v0 & 0x00000001))
  943. break;
  944. v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  945. stat.cookie = (v0 >> 16);
  946. stat.seq = (v1 & 0x0000FFFF);
  947. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  948. tmp = (v0 & 0x0000FFFF);
  949. stat.frame_count = ((tmp & 0xF000) >> 12);
  950. stat.rts_count = ((tmp & 0x0F00) >> 8);
  951. stat.supp_reason = ((tmp & 0x001C) >> 2);
  952. stat.pm_indicated = !!(tmp & 0x0080);
  953. stat.intermediate = !!(tmp & 0x0040);
  954. stat.for_ampdu = !!(tmp & 0x0020);
  955. stat.acked = !!(tmp & 0x0002);
  956. b43_handle_txstatus(dev, &stat);
  957. }
  958. }
  959. static void drain_txstatus_queue(struct b43_wldev *dev)
  960. {
  961. u32 dummy;
  962. if (dev->dev->id.revision < 5)
  963. return;
  964. /* Read all entries from the microcode TXstatus FIFO
  965. * and throw them away.
  966. */
  967. while (1) {
  968. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  969. if (!(dummy & 0x00000001))
  970. break;
  971. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  972. }
  973. }
  974. static u32 b43_jssi_read(struct b43_wldev *dev)
  975. {
  976. u32 val = 0;
  977. val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
  978. val <<= 16;
  979. val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
  980. return val;
  981. }
  982. static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
  983. {
  984. b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
  985. b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
  986. }
  987. static void b43_generate_noise_sample(struct b43_wldev *dev)
  988. {
  989. b43_jssi_write(dev, 0x7F7F7F7F);
  990. b43_write32(dev, B43_MMIO_MACCMD,
  991. b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
  992. B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
  993. }
  994. static void b43_calculate_link_quality(struct b43_wldev *dev)
  995. {
  996. /* Top half of Link Quality calculation. */
  997. if (dev->noisecalc.calculation_running)
  998. return;
  999. dev->noisecalc.channel_at_start = dev->phy.channel;
  1000. dev->noisecalc.calculation_running = 1;
  1001. dev->noisecalc.nr_samples = 0;
  1002. b43_generate_noise_sample(dev);
  1003. }
  1004. static void handle_irq_noise(struct b43_wldev *dev)
  1005. {
  1006. struct b43_phy *phy = &dev->phy;
  1007. u16 tmp;
  1008. u8 noise[4];
  1009. u8 i, j;
  1010. s32 average;
  1011. /* Bottom half of Link Quality calculation. */
  1012. B43_WARN_ON(!dev->noisecalc.calculation_running);
  1013. if (dev->noisecalc.channel_at_start != phy->channel)
  1014. goto drop_calculation;
  1015. *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
  1016. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  1017. noise[2] == 0x7F || noise[3] == 0x7F)
  1018. goto generate_new;
  1019. /* Get the noise samples. */
  1020. B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
  1021. i = dev->noisecalc.nr_samples;
  1022. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1023. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1024. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1025. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1026. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  1027. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  1028. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  1029. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  1030. dev->noisecalc.nr_samples++;
  1031. if (dev->noisecalc.nr_samples == 8) {
  1032. /* Calculate the Link Quality by the noise samples. */
  1033. average = 0;
  1034. for (i = 0; i < 8; i++) {
  1035. for (j = 0; j < 4; j++)
  1036. average += dev->noisecalc.samples[i][j];
  1037. }
  1038. average /= (8 * 4);
  1039. average *= 125;
  1040. average += 64;
  1041. average /= 128;
  1042. tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
  1043. tmp = (tmp / 128) & 0x1F;
  1044. if (tmp >= 8)
  1045. average += 2;
  1046. else
  1047. average -= 25;
  1048. if (tmp == 8)
  1049. average -= 72;
  1050. else
  1051. average -= 48;
  1052. dev->stats.link_noise = average;
  1053. drop_calculation:
  1054. dev->noisecalc.calculation_running = 0;
  1055. return;
  1056. }
  1057. generate_new:
  1058. b43_generate_noise_sample(dev);
  1059. }
  1060. static void handle_irq_tbtt_indication(struct b43_wldev *dev)
  1061. {
  1062. if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  1063. ///TODO: PS TBTT
  1064. } else {
  1065. if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
  1066. b43_power_saving_ctl_bits(dev, 0);
  1067. }
  1068. if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  1069. dev->dfq_valid = 1;
  1070. }
  1071. static void handle_irq_atim_end(struct b43_wldev *dev)
  1072. {
  1073. if (dev->dfq_valid) {
  1074. b43_write32(dev, B43_MMIO_MACCMD,
  1075. b43_read32(dev, B43_MMIO_MACCMD)
  1076. | B43_MACCMD_DFQ_VALID);
  1077. dev->dfq_valid = 0;
  1078. }
  1079. }
  1080. static void handle_irq_pmq(struct b43_wldev *dev)
  1081. {
  1082. u32 tmp;
  1083. //TODO: AP mode.
  1084. while (1) {
  1085. tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
  1086. if (!(tmp & 0x00000008))
  1087. break;
  1088. }
  1089. /* 16bit write is odd, but correct. */
  1090. b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
  1091. }
  1092. static void b43_write_template_common(struct b43_wldev *dev,
  1093. const u8 * data, u16 size,
  1094. u16 ram_offset,
  1095. u16 shm_size_offset, u8 rate)
  1096. {
  1097. u32 i, tmp;
  1098. struct b43_plcp_hdr4 plcp;
  1099. plcp.data = 0;
  1100. b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  1101. b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  1102. ram_offset += sizeof(u32);
  1103. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  1104. * So leave the first two bytes of the next write blank.
  1105. */
  1106. tmp = (u32) (data[0]) << 16;
  1107. tmp |= (u32) (data[1]) << 24;
  1108. b43_ram_write(dev, ram_offset, tmp);
  1109. ram_offset += sizeof(u32);
  1110. for (i = 2; i < size; i += sizeof(u32)) {
  1111. tmp = (u32) (data[i + 0]);
  1112. if (i + 1 < size)
  1113. tmp |= (u32) (data[i + 1]) << 8;
  1114. if (i + 2 < size)
  1115. tmp |= (u32) (data[i + 2]) << 16;
  1116. if (i + 3 < size)
  1117. tmp |= (u32) (data[i + 3]) << 24;
  1118. b43_ram_write(dev, ram_offset + i - 2, tmp);
  1119. }
  1120. b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
  1121. size + sizeof(struct b43_plcp_hdr6));
  1122. }
  1123. /* Check if the use of the antenna that ieee80211 told us to
  1124. * use is possible. This will fall back to DEFAULT.
  1125. * "antenna_nr" is the antenna identifier we got from ieee80211. */
  1126. u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
  1127. u8 antenna_nr)
  1128. {
  1129. u8 antenna_mask;
  1130. if (antenna_nr == 0) {
  1131. /* Zero means "use default antenna". That's always OK. */
  1132. return 0;
  1133. }
  1134. /* Get the mask of available antennas. */
  1135. if (dev->phy.gmode)
  1136. antenna_mask = dev->dev->bus->sprom.ant_available_bg;
  1137. else
  1138. antenna_mask = dev->dev->bus->sprom.ant_available_a;
  1139. if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
  1140. /* This antenna is not available. Fall back to default. */
  1141. return 0;
  1142. }
  1143. return antenna_nr;
  1144. }
  1145. static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
  1146. {
  1147. antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
  1148. switch (antenna) {
  1149. case 0: /* default/diversity */
  1150. return B43_ANTENNA_DEFAULT;
  1151. case 1: /* Antenna 0 */
  1152. return B43_ANTENNA0;
  1153. case 2: /* Antenna 1 */
  1154. return B43_ANTENNA1;
  1155. case 3: /* Antenna 2 */
  1156. return B43_ANTENNA2;
  1157. case 4: /* Antenna 3 */
  1158. return B43_ANTENNA3;
  1159. default:
  1160. return B43_ANTENNA_DEFAULT;
  1161. }
  1162. }
  1163. /* Convert a b43 antenna number value to the PHY TX control value. */
  1164. static u16 b43_antenna_to_phyctl(int antenna)
  1165. {
  1166. switch (antenna) {
  1167. case B43_ANTENNA0:
  1168. return B43_TXH_PHY_ANT0;
  1169. case B43_ANTENNA1:
  1170. return B43_TXH_PHY_ANT1;
  1171. case B43_ANTENNA2:
  1172. return B43_TXH_PHY_ANT2;
  1173. case B43_ANTENNA3:
  1174. return B43_TXH_PHY_ANT3;
  1175. case B43_ANTENNA_AUTO:
  1176. return B43_TXH_PHY_ANT01AUTO;
  1177. }
  1178. B43_WARN_ON(1);
  1179. return 0;
  1180. }
  1181. static void b43_write_beacon_template(struct b43_wldev *dev,
  1182. u16 ram_offset,
  1183. u16 shm_size_offset)
  1184. {
  1185. unsigned int i, len, variable_len;
  1186. const struct ieee80211_mgmt *bcn;
  1187. const u8 *ie;
  1188. bool tim_found = 0;
  1189. unsigned int rate;
  1190. u16 ctl;
  1191. int antenna;
  1192. bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
  1193. len = min((size_t) dev->wl->current_beacon->len,
  1194. 0x200 - sizeof(struct b43_plcp_hdr6));
  1195. rate = dev->wl->beacon_txctl.tx_rate->hw_value;
  1196. b43_write_template_common(dev, (const u8 *)bcn,
  1197. len, ram_offset, shm_size_offset, rate);
  1198. /* Write the PHY TX control parameters. */
  1199. antenna = b43_antenna_from_ieee80211(dev,
  1200. dev->wl->beacon_txctl.antenna_sel_tx);
  1201. antenna = b43_antenna_to_phyctl(antenna);
  1202. ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
  1203. /* We can't send beacons with short preamble. Would get PHY errors. */
  1204. ctl &= ~B43_TXH_PHY_SHORTPRMBL;
  1205. ctl &= ~B43_TXH_PHY_ANT;
  1206. ctl &= ~B43_TXH_PHY_ENC;
  1207. ctl |= antenna;
  1208. if (b43_is_cck_rate(rate))
  1209. ctl |= B43_TXH_PHY_ENC_CCK;
  1210. else
  1211. ctl |= B43_TXH_PHY_ENC_OFDM;
  1212. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  1213. /* Find the position of the TIM and the DTIM_period value
  1214. * and write them to SHM. */
  1215. ie = bcn->u.beacon.variable;
  1216. variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1217. for (i = 0; i < variable_len - 2; ) {
  1218. uint8_t ie_id, ie_len;
  1219. ie_id = ie[i];
  1220. ie_len = ie[i + 1];
  1221. if (ie_id == 5) {
  1222. u16 tim_position;
  1223. u16 dtim_period;
  1224. /* This is the TIM Information Element */
  1225. /* Check whether the ie_len is in the beacon data range. */
  1226. if (variable_len < ie_len + 2 + i)
  1227. break;
  1228. /* A valid TIM is at least 4 bytes long. */
  1229. if (ie_len < 4)
  1230. break;
  1231. tim_found = 1;
  1232. tim_position = sizeof(struct b43_plcp_hdr6);
  1233. tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1234. tim_position += i;
  1235. dtim_period = ie[i + 3];
  1236. b43_shm_write16(dev, B43_SHM_SHARED,
  1237. B43_SHM_SH_TIMBPOS, tim_position);
  1238. b43_shm_write16(dev, B43_SHM_SHARED,
  1239. B43_SHM_SH_DTIMPER, dtim_period);
  1240. break;
  1241. }
  1242. i += ie_len + 2;
  1243. }
  1244. if (!tim_found) {
  1245. b43warn(dev->wl, "Did not find a valid TIM IE in "
  1246. "the beacon template packet. AP or IBSS operation "
  1247. "may be broken.\n");
  1248. } else
  1249. b43dbg(dev->wl, "Updated beacon template\n");
  1250. }
  1251. static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
  1252. u16 shm_offset, u16 size,
  1253. struct ieee80211_rate *rate)
  1254. {
  1255. struct b43_plcp_hdr4 plcp;
  1256. u32 tmp;
  1257. __le16 dur;
  1258. plcp.data = 0;
  1259. b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
  1260. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  1261. dev->wl->vif, size,
  1262. rate);
  1263. /* Write PLCP in two parts and timing for packet transfer */
  1264. tmp = le32_to_cpu(plcp.data);
  1265. b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
  1266. b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
  1267. b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
  1268. }
  1269. /* Instead of using custom probe response template, this function
  1270. * just patches custom beacon template by:
  1271. * 1) Changing packet type
  1272. * 2) Patching duration field
  1273. * 3) Stripping TIM
  1274. */
  1275. static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
  1276. u16 *dest_size,
  1277. struct ieee80211_rate *rate)
  1278. {
  1279. const u8 *src_data;
  1280. u8 *dest_data;
  1281. u16 src_size, elem_size, src_pos, dest_pos;
  1282. __le16 dur;
  1283. struct ieee80211_hdr *hdr;
  1284. size_t ie_start;
  1285. src_size = dev->wl->current_beacon->len;
  1286. src_data = (const u8 *)dev->wl->current_beacon->data;
  1287. /* Get the start offset of the variable IEs in the packet. */
  1288. ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
  1289. B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
  1290. if (B43_WARN_ON(src_size < ie_start))
  1291. return NULL;
  1292. dest_data = kmalloc(src_size, GFP_ATOMIC);
  1293. if (unlikely(!dest_data))
  1294. return NULL;
  1295. /* Copy the static data and all Information Elements, except the TIM. */
  1296. memcpy(dest_data, src_data, ie_start);
  1297. src_pos = ie_start;
  1298. dest_pos = ie_start;
  1299. for ( ; src_pos < src_size - 2; src_pos += elem_size) {
  1300. elem_size = src_data[src_pos + 1] + 2;
  1301. if (src_data[src_pos] == 5) {
  1302. /* This is the TIM. */
  1303. continue;
  1304. }
  1305. memcpy(dest_data + dest_pos, src_data + src_pos,
  1306. elem_size);
  1307. dest_pos += elem_size;
  1308. }
  1309. *dest_size = dest_pos;
  1310. hdr = (struct ieee80211_hdr *)dest_data;
  1311. /* Set the frame control. */
  1312. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  1313. IEEE80211_STYPE_PROBE_RESP);
  1314. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  1315. dev->wl->vif, *dest_size,
  1316. rate);
  1317. hdr->duration_id = dur;
  1318. return dest_data;
  1319. }
  1320. static void b43_write_probe_resp_template(struct b43_wldev *dev,
  1321. u16 ram_offset,
  1322. u16 shm_size_offset,
  1323. struct ieee80211_rate *rate)
  1324. {
  1325. const u8 *probe_resp_data;
  1326. u16 size;
  1327. size = dev->wl->current_beacon->len;
  1328. probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
  1329. if (unlikely(!probe_resp_data))
  1330. return;
  1331. /* Looks like PLCP headers plus packet timings are stored for
  1332. * all possible basic rates
  1333. */
  1334. b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
  1335. b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
  1336. b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
  1337. b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
  1338. size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
  1339. b43_write_template_common(dev, probe_resp_data,
  1340. size, ram_offset, shm_size_offset,
  1341. rate->hw_value);
  1342. kfree(probe_resp_data);
  1343. }
  1344. static void handle_irq_beacon(struct b43_wldev *dev)
  1345. {
  1346. struct b43_wl *wl = dev->wl;
  1347. u32 cmd, beacon0_valid, beacon1_valid;
  1348. if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1349. return;
  1350. /* This is the bottom half of the asynchronous beacon update. */
  1351. /* Ignore interrupt in the future. */
  1352. dev->irq_savedstate &= ~B43_IRQ_BEACON;
  1353. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1354. beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
  1355. beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
  1356. /* Schedule interrupt manually, if busy. */
  1357. if (beacon0_valid && beacon1_valid) {
  1358. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
  1359. dev->irq_savedstate |= B43_IRQ_BEACON;
  1360. return;
  1361. }
  1362. if (!beacon0_valid) {
  1363. if (!wl->beacon0_uploaded) {
  1364. b43_write_beacon_template(dev, 0x68, 0x18);
  1365. b43_write_probe_resp_template(dev, 0x268, 0x4A,
  1366. &__b43_ratetable[3]);
  1367. wl->beacon0_uploaded = 1;
  1368. }
  1369. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1370. cmd |= B43_MACCMD_BEACON0_VALID;
  1371. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1372. } else if (!beacon1_valid) {
  1373. if (!wl->beacon1_uploaded) {
  1374. b43_write_beacon_template(dev, 0x468, 0x1A);
  1375. wl->beacon1_uploaded = 1;
  1376. }
  1377. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1378. cmd |= B43_MACCMD_BEACON1_VALID;
  1379. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1380. }
  1381. }
  1382. static void b43_beacon_update_trigger_work(struct work_struct *work)
  1383. {
  1384. struct b43_wl *wl = container_of(work, struct b43_wl,
  1385. beacon_update_trigger);
  1386. struct b43_wldev *dev;
  1387. mutex_lock(&wl->mutex);
  1388. dev = wl->current_dev;
  1389. if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
  1390. spin_lock_irq(&wl->irq_lock);
  1391. /* update beacon right away or defer to irq */
  1392. dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  1393. handle_irq_beacon(dev);
  1394. /* The handler might have updated the IRQ mask. */
  1395. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
  1396. dev->irq_savedstate);
  1397. mmiowb();
  1398. spin_unlock_irq(&wl->irq_lock);
  1399. }
  1400. mutex_unlock(&wl->mutex);
  1401. }
  1402. /* Asynchronously update the packet templates in template RAM.
  1403. * Locking: Requires wl->irq_lock to be locked. */
  1404. static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon,
  1405. const struct ieee80211_tx_control *txctl)
  1406. {
  1407. /* This is the top half of the ansynchronous beacon update.
  1408. * The bottom half is the beacon IRQ.
  1409. * Beacon update must be asynchronous to avoid sending an
  1410. * invalid beacon. This can happen for example, if the firmware
  1411. * transmits a beacon while we are updating it. */
  1412. if (wl->current_beacon)
  1413. dev_kfree_skb_any(wl->current_beacon);
  1414. wl->current_beacon = beacon;
  1415. memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl));
  1416. wl->beacon0_uploaded = 0;
  1417. wl->beacon1_uploaded = 0;
  1418. queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
  1419. }
  1420. static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
  1421. {
  1422. u32 tmp;
  1423. u16 i, len;
  1424. len = min((u16) ssid_len, (u16) 0x100);
  1425. for (i = 0; i < len; i += sizeof(u32)) {
  1426. tmp = (u32) (ssid[i + 0]);
  1427. if (i + 1 < len)
  1428. tmp |= (u32) (ssid[i + 1]) << 8;
  1429. if (i + 2 < len)
  1430. tmp |= (u32) (ssid[i + 2]) << 16;
  1431. if (i + 3 < len)
  1432. tmp |= (u32) (ssid[i + 3]) << 24;
  1433. b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
  1434. }
  1435. b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
  1436. }
  1437. static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
  1438. {
  1439. b43_time_lock(dev);
  1440. if (dev->dev->id.revision >= 3) {
  1441. b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
  1442. b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
  1443. } else {
  1444. b43_write16(dev, 0x606, (beacon_int >> 6));
  1445. b43_write16(dev, 0x610, beacon_int);
  1446. }
  1447. b43_time_unlock(dev);
  1448. b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
  1449. }
  1450. static void handle_irq_ucode_debug(struct b43_wldev *dev)
  1451. {
  1452. //TODO
  1453. }
  1454. /* Interrupt handler bottom-half */
  1455. static void b43_interrupt_tasklet(struct b43_wldev *dev)
  1456. {
  1457. u32 reason;
  1458. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1459. u32 merged_dma_reason = 0;
  1460. int i;
  1461. unsigned long flags;
  1462. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1463. B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
  1464. reason = dev->irq_reason;
  1465. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1466. dma_reason[i] = dev->dma_reason[i];
  1467. merged_dma_reason |= dma_reason[i];
  1468. }
  1469. if (unlikely(reason & B43_IRQ_MAC_TXERR))
  1470. b43err(dev->wl, "MAC transmission error\n");
  1471. if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
  1472. b43err(dev->wl, "PHY transmission error\n");
  1473. rmb();
  1474. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1475. atomic_set(&dev->phy.txerr_cnt,
  1476. B43_PHY_TX_BADNESS_LIMIT);
  1477. b43err(dev->wl, "Too many PHY TX errors, "
  1478. "restarting the controller\n");
  1479. b43_controller_restart(dev, "PHY TX errors");
  1480. }
  1481. }
  1482. if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
  1483. B43_DMAIRQ_NONFATALMASK))) {
  1484. if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
  1485. b43err(dev->wl, "Fatal DMA error: "
  1486. "0x%08X, 0x%08X, 0x%08X, "
  1487. "0x%08X, 0x%08X, 0x%08X\n",
  1488. dma_reason[0], dma_reason[1],
  1489. dma_reason[2], dma_reason[3],
  1490. dma_reason[4], dma_reason[5]);
  1491. b43_controller_restart(dev, "DMA error");
  1492. mmiowb();
  1493. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1494. return;
  1495. }
  1496. if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
  1497. b43err(dev->wl, "DMA error: "
  1498. "0x%08X, 0x%08X, 0x%08X, "
  1499. "0x%08X, 0x%08X, 0x%08X\n",
  1500. dma_reason[0], dma_reason[1],
  1501. dma_reason[2], dma_reason[3],
  1502. dma_reason[4], dma_reason[5]);
  1503. }
  1504. }
  1505. if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
  1506. handle_irq_ucode_debug(dev);
  1507. if (reason & B43_IRQ_TBTT_INDI)
  1508. handle_irq_tbtt_indication(dev);
  1509. if (reason & B43_IRQ_ATIM_END)
  1510. handle_irq_atim_end(dev);
  1511. if (reason & B43_IRQ_BEACON)
  1512. handle_irq_beacon(dev);
  1513. if (reason & B43_IRQ_PMQ)
  1514. handle_irq_pmq(dev);
  1515. if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
  1516. ;/* TODO */
  1517. if (reason & B43_IRQ_NOISESAMPLE_OK)
  1518. handle_irq_noise(dev);
  1519. /* Check the DMA reason registers for received data. */
  1520. if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
  1521. if (b43_using_pio_transfers(dev))
  1522. b43_pio_rx(dev->pio.rx_queue);
  1523. else
  1524. b43_dma_rx(dev->dma.rx_ring);
  1525. }
  1526. B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
  1527. B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
  1528. B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
  1529. B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
  1530. B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
  1531. if (reason & B43_IRQ_TX_OK)
  1532. handle_irq_transmit_status(dev);
  1533. b43_interrupt_enable(dev, dev->irq_savedstate);
  1534. mmiowb();
  1535. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1536. }
  1537. static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
  1538. {
  1539. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
  1540. b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
  1541. b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
  1542. b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
  1543. b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
  1544. b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
  1545. b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
  1546. }
  1547. /* Interrupt handler top-half */
  1548. static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
  1549. {
  1550. irqreturn_t ret = IRQ_NONE;
  1551. struct b43_wldev *dev = dev_id;
  1552. u32 reason;
  1553. if (!dev)
  1554. return IRQ_NONE;
  1555. spin_lock(&dev->wl->irq_lock);
  1556. if (b43_status(dev) < B43_STAT_STARTED)
  1557. goto out;
  1558. reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  1559. if (reason == 0xffffffff) /* shared IRQ */
  1560. goto out;
  1561. ret = IRQ_HANDLED;
  1562. reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  1563. if (!reason)
  1564. goto out;
  1565. dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
  1566. & 0x0001DC00;
  1567. dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
  1568. & 0x0000DC00;
  1569. dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
  1570. & 0x0000DC00;
  1571. dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
  1572. & 0x0001DC00;
  1573. dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
  1574. & 0x0000DC00;
  1575. dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
  1576. & 0x0000DC00;
  1577. b43_interrupt_ack(dev, reason);
  1578. /* disable all IRQs. They are enabled again in the bottom half. */
  1579. dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
  1580. /* save the reason code and call our bottom half. */
  1581. dev->irq_reason = reason;
  1582. tasklet_schedule(&dev->isr_tasklet);
  1583. out:
  1584. mmiowb();
  1585. spin_unlock(&dev->wl->irq_lock);
  1586. return ret;
  1587. }
  1588. static void do_release_fw(struct b43_firmware_file *fw)
  1589. {
  1590. release_firmware(fw->data);
  1591. fw->data = NULL;
  1592. fw->filename = NULL;
  1593. }
  1594. static void b43_release_firmware(struct b43_wldev *dev)
  1595. {
  1596. do_release_fw(&dev->fw.ucode);
  1597. do_release_fw(&dev->fw.pcm);
  1598. do_release_fw(&dev->fw.initvals);
  1599. do_release_fw(&dev->fw.initvals_band);
  1600. }
  1601. static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
  1602. {
  1603. const char *text;
  1604. text = "You must go to "
  1605. "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
  1606. "and download the latest firmware (version 4).\n";
  1607. if (error)
  1608. b43err(wl, text);
  1609. else
  1610. b43warn(wl, text);
  1611. }
  1612. static int do_request_fw(struct b43_wldev *dev,
  1613. const char *name,
  1614. struct b43_firmware_file *fw)
  1615. {
  1616. char path[sizeof(modparam_fwpostfix) + 32];
  1617. const struct firmware *blob;
  1618. struct b43_fw_header *hdr;
  1619. u32 size;
  1620. int err;
  1621. if (!name) {
  1622. /* Don't fetch anything. Free possibly cached firmware. */
  1623. do_release_fw(fw);
  1624. return 0;
  1625. }
  1626. if (fw->filename) {
  1627. if (strcmp(fw->filename, name) == 0)
  1628. return 0; /* Already have this fw. */
  1629. /* Free the cached firmware first. */
  1630. do_release_fw(fw);
  1631. }
  1632. snprintf(path, ARRAY_SIZE(path),
  1633. "b43%s/%s.fw",
  1634. modparam_fwpostfix, name);
  1635. err = request_firmware(&blob, path, dev->dev->dev);
  1636. if (err) {
  1637. b43err(dev->wl, "Firmware file \"%s\" not found "
  1638. "or load failed.\n", path);
  1639. return err;
  1640. }
  1641. if (blob->size < sizeof(struct b43_fw_header))
  1642. goto err_format;
  1643. hdr = (struct b43_fw_header *)(blob->data);
  1644. switch (hdr->type) {
  1645. case B43_FW_TYPE_UCODE:
  1646. case B43_FW_TYPE_PCM:
  1647. size = be32_to_cpu(hdr->size);
  1648. if (size != blob->size - sizeof(struct b43_fw_header))
  1649. goto err_format;
  1650. /* fallthrough */
  1651. case B43_FW_TYPE_IV:
  1652. if (hdr->ver != 1)
  1653. goto err_format;
  1654. break;
  1655. default:
  1656. goto err_format;
  1657. }
  1658. fw->data = blob;
  1659. fw->filename = name;
  1660. return 0;
  1661. err_format:
  1662. b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1663. release_firmware(blob);
  1664. return -EPROTO;
  1665. }
  1666. static int b43_request_firmware(struct b43_wldev *dev)
  1667. {
  1668. struct b43_firmware *fw = &dev->fw;
  1669. const u8 rev = dev->dev->id.revision;
  1670. const char *filename;
  1671. u32 tmshigh;
  1672. int err;
  1673. /* Get microcode */
  1674. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1675. if ((rev >= 5) && (rev <= 10))
  1676. filename = "ucode5";
  1677. else if ((rev >= 11) && (rev <= 12))
  1678. filename = "ucode11";
  1679. else if (rev >= 13)
  1680. filename = "ucode13";
  1681. else
  1682. goto err_no_ucode;
  1683. err = do_request_fw(dev, filename, &fw->ucode);
  1684. if (err)
  1685. goto err_load;
  1686. /* Get PCM code */
  1687. if ((rev >= 5) && (rev <= 10))
  1688. filename = "pcm5";
  1689. else if (rev >= 11)
  1690. filename = NULL;
  1691. else
  1692. goto err_no_pcm;
  1693. err = do_request_fw(dev, filename, &fw->pcm);
  1694. if (err)
  1695. goto err_load;
  1696. /* Get initvals */
  1697. switch (dev->phy.type) {
  1698. case B43_PHYTYPE_A:
  1699. if ((rev >= 5) && (rev <= 10)) {
  1700. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  1701. filename = "a0g1initvals5";
  1702. else
  1703. filename = "a0g0initvals5";
  1704. } else
  1705. goto err_no_initvals;
  1706. break;
  1707. case B43_PHYTYPE_G:
  1708. if ((rev >= 5) && (rev <= 10))
  1709. filename = "b0g0initvals5";
  1710. else if (rev >= 13)
  1711. filename = "lp0initvals13";
  1712. else
  1713. goto err_no_initvals;
  1714. break;
  1715. case B43_PHYTYPE_N:
  1716. if ((rev >= 11) && (rev <= 12))
  1717. filename = "n0initvals11";
  1718. else
  1719. goto err_no_initvals;
  1720. break;
  1721. default:
  1722. goto err_no_initvals;
  1723. }
  1724. err = do_request_fw(dev, filename, &fw->initvals);
  1725. if (err)
  1726. goto err_load;
  1727. /* Get bandswitch initvals */
  1728. switch (dev->phy.type) {
  1729. case B43_PHYTYPE_A:
  1730. if ((rev >= 5) && (rev <= 10)) {
  1731. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  1732. filename = "a0g1bsinitvals5";
  1733. else
  1734. filename = "a0g0bsinitvals5";
  1735. } else if (rev >= 11)
  1736. filename = NULL;
  1737. else
  1738. goto err_no_initvals;
  1739. break;
  1740. case B43_PHYTYPE_G:
  1741. if ((rev >= 5) && (rev <= 10))
  1742. filename = "b0g0bsinitvals5";
  1743. else if (rev >= 11)
  1744. filename = NULL;
  1745. else
  1746. goto err_no_initvals;
  1747. break;
  1748. case B43_PHYTYPE_N:
  1749. if ((rev >= 11) && (rev <= 12))
  1750. filename = "n0bsinitvals11";
  1751. else
  1752. goto err_no_initvals;
  1753. break;
  1754. default:
  1755. goto err_no_initvals;
  1756. }
  1757. err = do_request_fw(dev, filename, &fw->initvals_band);
  1758. if (err)
  1759. goto err_load;
  1760. return 0;
  1761. err_load:
  1762. b43_print_fw_helptext(dev->wl, 1);
  1763. goto error;
  1764. err_no_ucode:
  1765. err = -ENODEV;
  1766. b43err(dev->wl, "No microcode available for core rev %u\n", rev);
  1767. goto error;
  1768. err_no_pcm:
  1769. err = -ENODEV;
  1770. b43err(dev->wl, "No PCM available for core rev %u\n", rev);
  1771. goto error;
  1772. err_no_initvals:
  1773. err = -ENODEV;
  1774. b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
  1775. "core rev %u\n", dev->phy.type, rev);
  1776. goto error;
  1777. error:
  1778. b43_release_firmware(dev);
  1779. return err;
  1780. }
  1781. static int b43_upload_microcode(struct b43_wldev *dev)
  1782. {
  1783. const size_t hdr_len = sizeof(struct b43_fw_header);
  1784. const __be32 *data;
  1785. unsigned int i, len;
  1786. u16 fwrev, fwpatch, fwdate, fwtime;
  1787. u32 tmp, macctl;
  1788. int err = 0;
  1789. /* Jump the microcode PSM to offset 0 */
  1790. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  1791. B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
  1792. macctl |= B43_MACCTL_PSM_JMP0;
  1793. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  1794. /* Zero out all microcode PSM registers and shared memory. */
  1795. for (i = 0; i < 64; i++)
  1796. b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
  1797. for (i = 0; i < 4096; i += 2)
  1798. b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
  1799. /* Upload Microcode. */
  1800. data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
  1801. len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
  1802. b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
  1803. for (i = 0; i < len; i++) {
  1804. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  1805. udelay(10);
  1806. }
  1807. if (dev->fw.pcm.data) {
  1808. /* Upload PCM data. */
  1809. data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
  1810. len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
  1811. b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
  1812. b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
  1813. /* No need for autoinc bit in SHM_HW */
  1814. b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
  1815. for (i = 0; i < len; i++) {
  1816. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  1817. udelay(10);
  1818. }
  1819. }
  1820. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
  1821. /* Start the microcode PSM */
  1822. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  1823. macctl &= ~B43_MACCTL_PSM_JMP0;
  1824. macctl |= B43_MACCTL_PSM_RUN;
  1825. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  1826. /* Wait for the microcode to load and respond */
  1827. i = 0;
  1828. while (1) {
  1829. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  1830. if (tmp == B43_IRQ_MAC_SUSPENDED)
  1831. break;
  1832. i++;
  1833. if (i >= 20) {
  1834. b43err(dev->wl, "Microcode not responding\n");
  1835. b43_print_fw_helptext(dev->wl, 1);
  1836. err = -ENODEV;
  1837. goto error;
  1838. }
  1839. msleep_interruptible(50);
  1840. if (signal_pending(current)) {
  1841. err = -EINTR;
  1842. goto error;
  1843. }
  1844. }
  1845. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
  1846. /* Get and check the revisions. */
  1847. fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
  1848. fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
  1849. fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
  1850. fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
  1851. if (fwrev <= 0x128) {
  1852. b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
  1853. "binary drivers older than version 4.x is unsupported. "
  1854. "You must upgrade your firmware files.\n");
  1855. b43_print_fw_helptext(dev->wl, 1);
  1856. err = -EOPNOTSUPP;
  1857. goto error;
  1858. }
  1859. b43info(dev->wl, "Loading firmware version %u.%u "
  1860. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
  1861. fwrev, fwpatch,
  1862. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1863. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  1864. dev->fw.rev = fwrev;
  1865. dev->fw.patch = fwpatch;
  1866. if (b43_is_old_txhdr_format(dev)) {
  1867. b43warn(dev->wl, "You are using an old firmware image. "
  1868. "Support for old firmware will be removed in July 2008.\n");
  1869. b43_print_fw_helptext(dev->wl, 0);
  1870. }
  1871. return 0;
  1872. error:
  1873. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  1874. macctl &= ~B43_MACCTL_PSM_RUN;
  1875. macctl |= B43_MACCTL_PSM_JMP0;
  1876. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  1877. return err;
  1878. }
  1879. static int b43_write_initvals(struct b43_wldev *dev,
  1880. const struct b43_iv *ivals,
  1881. size_t count,
  1882. size_t array_size)
  1883. {
  1884. const struct b43_iv *iv;
  1885. u16 offset;
  1886. size_t i;
  1887. bool bit32;
  1888. BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
  1889. iv = ivals;
  1890. for (i = 0; i < count; i++) {
  1891. if (array_size < sizeof(iv->offset_size))
  1892. goto err_format;
  1893. array_size -= sizeof(iv->offset_size);
  1894. offset = be16_to_cpu(iv->offset_size);
  1895. bit32 = !!(offset & B43_IV_32BIT);
  1896. offset &= B43_IV_OFFSET_MASK;
  1897. if (offset >= 0x1000)
  1898. goto err_format;
  1899. if (bit32) {
  1900. u32 value;
  1901. if (array_size < sizeof(iv->data.d32))
  1902. goto err_format;
  1903. array_size -= sizeof(iv->data.d32);
  1904. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1905. b43_write32(dev, offset, value);
  1906. iv = (const struct b43_iv *)((const uint8_t *)iv +
  1907. sizeof(__be16) +
  1908. sizeof(__be32));
  1909. } else {
  1910. u16 value;
  1911. if (array_size < sizeof(iv->data.d16))
  1912. goto err_format;
  1913. array_size -= sizeof(iv->data.d16);
  1914. value = be16_to_cpu(iv->data.d16);
  1915. b43_write16(dev, offset, value);
  1916. iv = (const struct b43_iv *)((const uint8_t *)iv +
  1917. sizeof(__be16) +
  1918. sizeof(__be16));
  1919. }
  1920. }
  1921. if (array_size)
  1922. goto err_format;
  1923. return 0;
  1924. err_format:
  1925. b43err(dev->wl, "Initial Values Firmware file-format error.\n");
  1926. b43_print_fw_helptext(dev->wl, 1);
  1927. return -EPROTO;
  1928. }
  1929. static int b43_upload_initvals(struct b43_wldev *dev)
  1930. {
  1931. const size_t hdr_len = sizeof(struct b43_fw_header);
  1932. const struct b43_fw_header *hdr;
  1933. struct b43_firmware *fw = &dev->fw;
  1934. const struct b43_iv *ivals;
  1935. size_t count;
  1936. int err;
  1937. hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
  1938. ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
  1939. count = be32_to_cpu(hdr->size);
  1940. err = b43_write_initvals(dev, ivals, count,
  1941. fw->initvals.data->size - hdr_len);
  1942. if (err)
  1943. goto out;
  1944. if (fw->initvals_band.data) {
  1945. hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
  1946. ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
  1947. count = be32_to_cpu(hdr->size);
  1948. err = b43_write_initvals(dev, ivals, count,
  1949. fw->initvals_band.data->size - hdr_len);
  1950. if (err)
  1951. goto out;
  1952. }
  1953. out:
  1954. return err;
  1955. }
  1956. /* Initialize the GPIOs
  1957. * http://bcm-specs.sipsolutions.net/GPIO
  1958. */
  1959. static int b43_gpio_init(struct b43_wldev *dev)
  1960. {
  1961. struct ssb_bus *bus = dev->dev->bus;
  1962. struct ssb_device *gpiodev, *pcidev = NULL;
  1963. u32 mask, set;
  1964. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  1965. & ~B43_MACCTL_GPOUTSMSK);
  1966. b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
  1967. | 0x000F);
  1968. mask = 0x0000001F;
  1969. set = 0x0000000F;
  1970. if (dev->dev->bus->chip_id == 0x4301) {
  1971. mask |= 0x0060;
  1972. set |= 0x0060;
  1973. }
  1974. if (0 /* FIXME: conditional unknown */ ) {
  1975. b43_write16(dev, B43_MMIO_GPIO_MASK,
  1976. b43_read16(dev, B43_MMIO_GPIO_MASK)
  1977. | 0x0100);
  1978. mask |= 0x0180;
  1979. set |= 0x0180;
  1980. }
  1981. if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
  1982. b43_write16(dev, B43_MMIO_GPIO_MASK,
  1983. b43_read16(dev, B43_MMIO_GPIO_MASK)
  1984. | 0x0200);
  1985. mask |= 0x0200;
  1986. set |= 0x0200;
  1987. }
  1988. if (dev->dev->id.revision >= 2)
  1989. mask |= 0x0010; /* FIXME: This is redundant. */
  1990. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1991. pcidev = bus->pcicore.dev;
  1992. #endif
  1993. gpiodev = bus->chipco.dev ? : pcidev;
  1994. if (!gpiodev)
  1995. return 0;
  1996. ssb_write32(gpiodev, B43_GPIO_CONTROL,
  1997. (ssb_read32(gpiodev, B43_GPIO_CONTROL)
  1998. & mask) | set);
  1999. return 0;
  2000. }
  2001. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  2002. static void b43_gpio_cleanup(struct b43_wldev *dev)
  2003. {
  2004. struct ssb_bus *bus = dev->dev->bus;
  2005. struct ssb_device *gpiodev, *pcidev = NULL;
  2006. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2007. pcidev = bus->pcicore.dev;
  2008. #endif
  2009. gpiodev = bus->chipco.dev ? : pcidev;
  2010. if (!gpiodev)
  2011. return;
  2012. ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
  2013. }
  2014. /* http://bcm-specs.sipsolutions.net/EnableMac */
  2015. static void b43_mac_enable(struct b43_wldev *dev)
  2016. {
  2017. dev->mac_suspended--;
  2018. B43_WARN_ON(dev->mac_suspended < 0);
  2019. if (dev->mac_suspended == 0) {
  2020. b43_write32(dev, B43_MMIO_MACCTL,
  2021. b43_read32(dev, B43_MMIO_MACCTL)
  2022. | B43_MACCTL_ENABLED);
  2023. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
  2024. B43_IRQ_MAC_SUSPENDED);
  2025. /* Commit writes */
  2026. b43_read32(dev, B43_MMIO_MACCTL);
  2027. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2028. b43_power_saving_ctl_bits(dev, 0);
  2029. /* Re-enable IRQs. */
  2030. spin_lock_irq(&dev->wl->irq_lock);
  2031. b43_interrupt_enable(dev, dev->irq_savedstate);
  2032. spin_unlock_irq(&dev->wl->irq_lock);
  2033. }
  2034. }
  2035. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  2036. static void b43_mac_suspend(struct b43_wldev *dev)
  2037. {
  2038. int i;
  2039. u32 tmp;
  2040. might_sleep();
  2041. B43_WARN_ON(dev->mac_suspended < 0);
  2042. if (dev->mac_suspended == 0) {
  2043. /* Mask IRQs before suspending MAC. Otherwise
  2044. * the MAC stays busy and won't suspend. */
  2045. spin_lock_irq(&dev->wl->irq_lock);
  2046. tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
  2047. spin_unlock_irq(&dev->wl->irq_lock);
  2048. b43_synchronize_irq(dev);
  2049. dev->irq_savedstate = tmp;
  2050. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  2051. b43_write32(dev, B43_MMIO_MACCTL,
  2052. b43_read32(dev, B43_MMIO_MACCTL)
  2053. & ~B43_MACCTL_ENABLED);
  2054. /* force pci to flush the write */
  2055. b43_read32(dev, B43_MMIO_MACCTL);
  2056. for (i = 35; i; i--) {
  2057. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2058. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2059. goto out;
  2060. udelay(10);
  2061. }
  2062. /* Hm, it seems this will take some time. Use msleep(). */
  2063. for (i = 40; i; i--) {
  2064. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2065. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2066. goto out;
  2067. msleep(1);
  2068. }
  2069. b43err(dev->wl, "MAC suspend failed\n");
  2070. }
  2071. out:
  2072. dev->mac_suspended++;
  2073. }
  2074. static void b43_adjust_opmode(struct b43_wldev *dev)
  2075. {
  2076. struct b43_wl *wl = dev->wl;
  2077. u32 ctl;
  2078. u16 cfp_pretbtt;
  2079. ctl = b43_read32(dev, B43_MMIO_MACCTL);
  2080. /* Reset status to STA infrastructure mode. */
  2081. ctl &= ~B43_MACCTL_AP;
  2082. ctl &= ~B43_MACCTL_KEEP_CTL;
  2083. ctl &= ~B43_MACCTL_KEEP_BADPLCP;
  2084. ctl &= ~B43_MACCTL_KEEP_BAD;
  2085. ctl &= ~B43_MACCTL_PROMISC;
  2086. ctl &= ~B43_MACCTL_BEACPROMISC;
  2087. ctl |= B43_MACCTL_INFRA;
  2088. if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2089. ctl |= B43_MACCTL_AP;
  2090. else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  2091. ctl &= ~B43_MACCTL_INFRA;
  2092. if (wl->filter_flags & FIF_CONTROL)
  2093. ctl |= B43_MACCTL_KEEP_CTL;
  2094. if (wl->filter_flags & FIF_FCSFAIL)
  2095. ctl |= B43_MACCTL_KEEP_BAD;
  2096. if (wl->filter_flags & FIF_PLCPFAIL)
  2097. ctl |= B43_MACCTL_KEEP_BADPLCP;
  2098. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  2099. ctl |= B43_MACCTL_PROMISC;
  2100. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2101. ctl |= B43_MACCTL_BEACPROMISC;
  2102. /* Workaround: On old hardware the HW-MAC-address-filter
  2103. * doesn't work properly, so always run promisc in filter
  2104. * it in software. */
  2105. if (dev->dev->id.revision <= 4)
  2106. ctl |= B43_MACCTL_PROMISC;
  2107. b43_write32(dev, B43_MMIO_MACCTL, ctl);
  2108. cfp_pretbtt = 2;
  2109. if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
  2110. if (dev->dev->bus->chip_id == 0x4306 &&
  2111. dev->dev->bus->chip_rev == 3)
  2112. cfp_pretbtt = 100;
  2113. else
  2114. cfp_pretbtt = 50;
  2115. }
  2116. b43_write16(dev, 0x612, cfp_pretbtt);
  2117. }
  2118. static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
  2119. {
  2120. u16 offset;
  2121. if (is_ofdm) {
  2122. offset = 0x480;
  2123. offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  2124. } else {
  2125. offset = 0x4C0;
  2126. offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  2127. }
  2128. b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
  2129. b43_shm_read16(dev, B43_SHM_SHARED, offset));
  2130. }
  2131. static void b43_rate_memory_init(struct b43_wldev *dev)
  2132. {
  2133. switch (dev->phy.type) {
  2134. case B43_PHYTYPE_A:
  2135. case B43_PHYTYPE_G:
  2136. case B43_PHYTYPE_N:
  2137. b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
  2138. b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
  2139. b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
  2140. b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
  2141. b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
  2142. b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
  2143. b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
  2144. if (dev->phy.type == B43_PHYTYPE_A)
  2145. break;
  2146. /* fallthrough */
  2147. case B43_PHYTYPE_B:
  2148. b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
  2149. b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
  2150. b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
  2151. b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
  2152. break;
  2153. default:
  2154. B43_WARN_ON(1);
  2155. }
  2156. }
  2157. /* Set the default values for the PHY TX Control Words. */
  2158. static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
  2159. {
  2160. u16 ctl = 0;
  2161. ctl |= B43_TXH_PHY_ENC_CCK;
  2162. ctl |= B43_TXH_PHY_ANT01AUTO;
  2163. ctl |= B43_TXH_PHY_TXPWR;
  2164. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  2165. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
  2166. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
  2167. }
  2168. /* Set the TX-Antenna for management frames sent by firmware. */
  2169. static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
  2170. {
  2171. u16 ant;
  2172. u16 tmp;
  2173. ant = b43_antenna_to_phyctl(antenna);
  2174. /* For ACK/CTS */
  2175. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
  2176. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2177. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
  2178. /* For Probe Resposes */
  2179. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
  2180. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2181. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
  2182. }
  2183. /* This is the opposite of b43_chip_init() */
  2184. static void b43_chip_exit(struct b43_wldev *dev)
  2185. {
  2186. b43_radio_turn_off(dev, 1);
  2187. b43_gpio_cleanup(dev);
  2188. /* firmware is released later */
  2189. }
  2190. /* Initialize the chip
  2191. * http://bcm-specs.sipsolutions.net/ChipInit
  2192. */
  2193. static int b43_chip_init(struct b43_wldev *dev)
  2194. {
  2195. struct b43_phy *phy = &dev->phy;
  2196. int err, tmp;
  2197. u32 value32, macctl;
  2198. u16 value16;
  2199. /* Initialize the MAC control */
  2200. macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
  2201. if (dev->phy.gmode)
  2202. macctl |= B43_MACCTL_GMODE;
  2203. macctl |= B43_MACCTL_INFRA;
  2204. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2205. err = b43_request_firmware(dev);
  2206. if (err)
  2207. goto out;
  2208. err = b43_upload_microcode(dev);
  2209. if (err)
  2210. goto out; /* firmware is released later */
  2211. err = b43_gpio_init(dev);
  2212. if (err)
  2213. goto out; /* firmware is released later */
  2214. err = b43_upload_initvals(dev);
  2215. if (err)
  2216. goto err_gpio_clean;
  2217. b43_radio_turn_on(dev);
  2218. b43_write16(dev, 0x03E6, 0x0000);
  2219. err = b43_phy_init(dev);
  2220. if (err)
  2221. goto err_radio_off;
  2222. /* Select initial Interference Mitigation. */
  2223. tmp = phy->interfmode;
  2224. phy->interfmode = B43_INTERFMODE_NONE;
  2225. b43_radio_set_interference_mitigation(dev, tmp);
  2226. b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
  2227. b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
  2228. if (phy->type == B43_PHYTYPE_B) {
  2229. value16 = b43_read16(dev, 0x005E);
  2230. value16 |= 0x0004;
  2231. b43_write16(dev, 0x005E, value16);
  2232. }
  2233. b43_write32(dev, 0x0100, 0x01000000);
  2234. if (dev->dev->id.revision < 5)
  2235. b43_write32(dev, 0x010C, 0x01000000);
  2236. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  2237. & ~B43_MACCTL_INFRA);
  2238. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  2239. | B43_MACCTL_INFRA);
  2240. /* Probe Response Timeout value */
  2241. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  2242. b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
  2243. /* Initially set the wireless operation mode. */
  2244. b43_adjust_opmode(dev);
  2245. if (dev->dev->id.revision < 3) {
  2246. b43_write16(dev, 0x060E, 0x0000);
  2247. b43_write16(dev, 0x0610, 0x8000);
  2248. b43_write16(dev, 0x0604, 0x0000);
  2249. b43_write16(dev, 0x0606, 0x0200);
  2250. } else {
  2251. b43_write32(dev, 0x0188, 0x80000000);
  2252. b43_write32(dev, 0x018C, 0x02000000);
  2253. }
  2254. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
  2255. b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  2256. b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  2257. b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  2258. b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  2259. b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  2260. b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  2261. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  2262. value32 |= 0x00100000;
  2263. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  2264. b43_write16(dev, B43_MMIO_POWERUP_DELAY,
  2265. dev->dev->bus->chipco.fast_pwrup_delay);
  2266. err = 0;
  2267. b43dbg(dev->wl, "Chip initialized\n");
  2268. out:
  2269. return err;
  2270. err_radio_off:
  2271. b43_radio_turn_off(dev, 1);
  2272. err_gpio_clean:
  2273. b43_gpio_cleanup(dev);
  2274. return err;
  2275. }
  2276. static void b43_periodic_every120sec(struct b43_wldev *dev)
  2277. {
  2278. struct b43_phy *phy = &dev->phy;
  2279. if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
  2280. return;
  2281. b43_mac_suspend(dev);
  2282. b43_lo_g_measure(dev);
  2283. b43_mac_enable(dev);
  2284. if (b43_has_hardware_pctl(phy))
  2285. b43_lo_g_ctl_mark_all_unused(dev);
  2286. }
  2287. static void b43_periodic_every60sec(struct b43_wldev *dev)
  2288. {
  2289. struct b43_phy *phy = &dev->phy;
  2290. if (phy->type != B43_PHYTYPE_G)
  2291. return;
  2292. if (!b43_has_hardware_pctl(phy))
  2293. b43_lo_g_ctl_mark_all_unused(dev);
  2294. if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
  2295. b43_mac_suspend(dev);
  2296. b43_calc_nrssi_slope(dev);
  2297. if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
  2298. u8 old_chan = phy->channel;
  2299. /* VCO Calibration */
  2300. if (old_chan >= 8)
  2301. b43_radio_selectchannel(dev, 1, 0);
  2302. else
  2303. b43_radio_selectchannel(dev, 13, 0);
  2304. b43_radio_selectchannel(dev, old_chan, 0);
  2305. }
  2306. b43_mac_enable(dev);
  2307. }
  2308. }
  2309. static void b43_periodic_every30sec(struct b43_wldev *dev)
  2310. {
  2311. /* Update device statistics. */
  2312. b43_calculate_link_quality(dev);
  2313. }
  2314. static void b43_periodic_every15sec(struct b43_wldev *dev)
  2315. {
  2316. struct b43_phy *phy = &dev->phy;
  2317. if (phy->type == B43_PHYTYPE_G) {
  2318. //TODO: update_aci_moving_average
  2319. if (phy->aci_enable && phy->aci_wlan_automatic) {
  2320. b43_mac_suspend(dev);
  2321. if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
  2322. if (0 /*TODO: bunch of conditions */ ) {
  2323. b43_radio_set_interference_mitigation
  2324. (dev, B43_INTERFMODE_MANUALWLAN);
  2325. }
  2326. } else if (1 /*TODO*/) {
  2327. /*
  2328. if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
  2329. b43_radio_set_interference_mitigation(dev,
  2330. B43_INTERFMODE_NONE);
  2331. }
  2332. */
  2333. }
  2334. b43_mac_enable(dev);
  2335. } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
  2336. phy->rev == 1) {
  2337. //TODO: implement rev1 workaround
  2338. }
  2339. }
  2340. b43_phy_xmitpower(dev); //FIXME: unless scanning?
  2341. //TODO for APHY (temperature?)
  2342. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  2343. wmb();
  2344. }
  2345. static void do_periodic_work(struct b43_wldev *dev)
  2346. {
  2347. unsigned int state;
  2348. state = dev->periodic_state;
  2349. if (state % 8 == 0)
  2350. b43_periodic_every120sec(dev);
  2351. if (state % 4 == 0)
  2352. b43_periodic_every60sec(dev);
  2353. if (state % 2 == 0)
  2354. b43_periodic_every30sec(dev);
  2355. b43_periodic_every15sec(dev);
  2356. }
  2357. /* Periodic work locking policy:
  2358. * The whole periodic work handler is protected by
  2359. * wl->mutex. If another lock is needed somewhere in the
  2360. * pwork callchain, it's aquired in-place, where it's needed.
  2361. */
  2362. static void b43_periodic_work_handler(struct work_struct *work)
  2363. {
  2364. struct b43_wldev *dev = container_of(work, struct b43_wldev,
  2365. periodic_work.work);
  2366. struct b43_wl *wl = dev->wl;
  2367. unsigned long delay;
  2368. mutex_lock(&wl->mutex);
  2369. if (unlikely(b43_status(dev) != B43_STAT_STARTED))
  2370. goto out;
  2371. if (b43_debug(dev, B43_DBG_PWORK_STOP))
  2372. goto out_requeue;
  2373. do_periodic_work(dev);
  2374. dev->periodic_state++;
  2375. out_requeue:
  2376. if (b43_debug(dev, B43_DBG_PWORK_FAST))
  2377. delay = msecs_to_jiffies(50);
  2378. else
  2379. delay = round_jiffies_relative(HZ * 15);
  2380. queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
  2381. out:
  2382. mutex_unlock(&wl->mutex);
  2383. }
  2384. static void b43_periodic_tasks_setup(struct b43_wldev *dev)
  2385. {
  2386. struct delayed_work *work = &dev->periodic_work;
  2387. dev->periodic_state = 0;
  2388. INIT_DELAYED_WORK(work, b43_periodic_work_handler);
  2389. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  2390. }
  2391. /* Check if communication with the device works correctly. */
  2392. static int b43_validate_chipaccess(struct b43_wldev *dev)
  2393. {
  2394. u32 v, backup;
  2395. backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
  2396. /* Check for read/write and endianness problems. */
  2397. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
  2398. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
  2399. goto error;
  2400. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
  2401. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
  2402. goto error;
  2403. b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
  2404. if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
  2405. /* The 32bit register shadows the two 16bit registers
  2406. * with update sideeffects. Validate this. */
  2407. b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
  2408. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
  2409. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
  2410. goto error;
  2411. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
  2412. goto error;
  2413. }
  2414. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
  2415. v = b43_read32(dev, B43_MMIO_MACCTL);
  2416. v |= B43_MACCTL_GMODE;
  2417. if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
  2418. goto error;
  2419. return 0;
  2420. error:
  2421. b43err(dev->wl, "Failed to validate the chipaccess\n");
  2422. return -ENODEV;
  2423. }
  2424. static void b43_security_init(struct b43_wldev *dev)
  2425. {
  2426. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  2427. B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  2428. dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
  2429. /* KTP is a word address, but we address SHM bytewise.
  2430. * So multiply by two.
  2431. */
  2432. dev->ktp *= 2;
  2433. if (dev->dev->id.revision >= 5) {
  2434. /* Number of RCMTA address slots */
  2435. b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
  2436. }
  2437. b43_clear_keys(dev);
  2438. }
  2439. static int b43_rng_read(struct hwrng *rng, u32 * data)
  2440. {
  2441. struct b43_wl *wl = (struct b43_wl *)rng->priv;
  2442. unsigned long flags;
  2443. /* Don't take wl->mutex here, as it could deadlock with
  2444. * hwrng internal locking. It's not needed to take
  2445. * wl->mutex here, anyway. */
  2446. spin_lock_irqsave(&wl->irq_lock, flags);
  2447. *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
  2448. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2449. return (sizeof(u16));
  2450. }
  2451. static void b43_rng_exit(struct b43_wl *wl)
  2452. {
  2453. if (wl->rng_initialized)
  2454. hwrng_unregister(&wl->rng);
  2455. }
  2456. static int b43_rng_init(struct b43_wl *wl)
  2457. {
  2458. int err;
  2459. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2460. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2461. wl->rng.name = wl->rng_name;
  2462. wl->rng.data_read = b43_rng_read;
  2463. wl->rng.priv = (unsigned long)wl;
  2464. wl->rng_initialized = 1;
  2465. err = hwrng_register(&wl->rng);
  2466. if (err) {
  2467. wl->rng_initialized = 0;
  2468. b43err(wl, "Failed to register the random "
  2469. "number generator (%d)\n", err);
  2470. }
  2471. return err;
  2472. }
  2473. static int b43_op_tx(struct ieee80211_hw *hw,
  2474. struct sk_buff *skb,
  2475. struct ieee80211_tx_control *ctl)
  2476. {
  2477. struct b43_wl *wl = hw_to_b43_wl(hw);
  2478. struct b43_wldev *dev = wl->current_dev;
  2479. int err = -ENODEV;
  2480. if (unlikely(skb->len < 2 + 2 + 6)) {
  2481. /* Too short, this can't be a valid frame. */
  2482. return -EINVAL;
  2483. }
  2484. B43_WARN_ON(skb_shinfo(skb)->nr_frags);
  2485. if (unlikely(!dev))
  2486. goto out;
  2487. if (unlikely(b43_status(dev) < B43_STAT_STARTED))
  2488. goto out;
  2489. /* TX is done without a global lock. */
  2490. if (b43_using_pio_transfers(dev))
  2491. err = b43_pio_tx(dev, skb, ctl);
  2492. else
  2493. err = b43_dma_tx(dev, skb, ctl);
  2494. out:
  2495. if (unlikely(err))
  2496. return NETDEV_TX_BUSY;
  2497. return NETDEV_TX_OK;
  2498. }
  2499. /* Locking: wl->irq_lock */
  2500. static void b43_qos_params_upload(struct b43_wldev *dev,
  2501. const struct ieee80211_tx_queue_params *p,
  2502. u16 shm_offset)
  2503. {
  2504. u16 params[B43_NR_QOSPARAMS];
  2505. int cw_min, cw_max, aifs, bslots, tmp;
  2506. unsigned int i;
  2507. const u16 aCWmin = 0x0001;
  2508. const u16 aCWmax = 0x03FF;
  2509. /* Calculate the default values for the parameters, if needed. */
  2510. switch (shm_offset) {
  2511. case B43_QOS_VOICE:
  2512. aifs = (p->aifs == -1) ? 2 : p->aifs;
  2513. cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min;
  2514. cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max;
  2515. break;
  2516. case B43_QOS_VIDEO:
  2517. aifs = (p->aifs == -1) ? 2 : p->aifs;
  2518. cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min;
  2519. cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max;
  2520. break;
  2521. case B43_QOS_BESTEFFORT:
  2522. aifs = (p->aifs == -1) ? 3 : p->aifs;
  2523. cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
  2524. cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
  2525. break;
  2526. case B43_QOS_BACKGROUND:
  2527. aifs = (p->aifs == -1) ? 7 : p->aifs;
  2528. cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min;
  2529. cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max;
  2530. break;
  2531. default:
  2532. B43_WARN_ON(1);
  2533. return;
  2534. }
  2535. if (cw_min <= 0)
  2536. cw_min = aCWmin;
  2537. if (cw_max <= 0)
  2538. cw_max = aCWmin;
  2539. bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min;
  2540. memset(&params, 0, sizeof(params));
  2541. params[B43_QOSPARAM_TXOP] = p->txop * 32;
  2542. params[B43_QOSPARAM_CWMIN] = cw_min;
  2543. params[B43_QOSPARAM_CWMAX] = cw_max;
  2544. params[B43_QOSPARAM_CWCUR] = cw_min;
  2545. params[B43_QOSPARAM_AIFS] = aifs;
  2546. params[B43_QOSPARAM_BSLOTS] = bslots;
  2547. params[B43_QOSPARAM_REGGAP] = bslots + aifs;
  2548. for (i = 0; i < ARRAY_SIZE(params); i++) {
  2549. if (i == B43_QOSPARAM_STATUS) {
  2550. tmp = b43_shm_read16(dev, B43_SHM_SHARED,
  2551. shm_offset + (i * 2));
  2552. /* Mark the parameters as updated. */
  2553. tmp |= 0x100;
  2554. b43_shm_write16(dev, B43_SHM_SHARED,
  2555. shm_offset + (i * 2),
  2556. tmp);
  2557. } else {
  2558. b43_shm_write16(dev, B43_SHM_SHARED,
  2559. shm_offset + (i * 2),
  2560. params[i]);
  2561. }
  2562. }
  2563. }
  2564. /* Update the QOS parameters in hardware. */
  2565. static void b43_qos_update(struct b43_wldev *dev)
  2566. {
  2567. struct b43_wl *wl = dev->wl;
  2568. struct b43_qos_params *params;
  2569. unsigned long flags;
  2570. unsigned int i;
  2571. /* Mapping of mac80211 queues to b43 SHM offsets. */
  2572. static const u16 qos_shm_offsets[] = {
  2573. [0] = B43_QOS_VOICE,
  2574. [1] = B43_QOS_VIDEO,
  2575. [2] = B43_QOS_BESTEFFORT,
  2576. [3] = B43_QOS_BACKGROUND,
  2577. };
  2578. BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params));
  2579. b43_mac_suspend(dev);
  2580. spin_lock_irqsave(&wl->irq_lock, flags);
  2581. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  2582. params = &(wl->qos_params[i]);
  2583. if (params->need_hw_update) {
  2584. b43_qos_params_upload(dev, &(params->p),
  2585. qos_shm_offsets[i]);
  2586. params->need_hw_update = 0;
  2587. }
  2588. }
  2589. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2590. b43_mac_enable(dev);
  2591. }
  2592. static void b43_qos_clear(struct b43_wl *wl)
  2593. {
  2594. struct b43_qos_params *params;
  2595. unsigned int i;
  2596. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  2597. params = &(wl->qos_params[i]);
  2598. memset(&(params->p), 0, sizeof(params->p));
  2599. params->p.aifs = -1;
  2600. params->need_hw_update = 1;
  2601. }
  2602. }
  2603. /* Initialize the core's QOS capabilities */
  2604. static void b43_qos_init(struct b43_wldev *dev)
  2605. {
  2606. struct b43_wl *wl = dev->wl;
  2607. unsigned int i;
  2608. /* Upload the current QOS parameters. */
  2609. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++)
  2610. wl->qos_params[i].need_hw_update = 1;
  2611. b43_qos_update(dev);
  2612. /* Enable QOS support. */
  2613. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
  2614. b43_write16(dev, B43_MMIO_IFSCTL,
  2615. b43_read16(dev, B43_MMIO_IFSCTL)
  2616. | B43_MMIO_IFSCTL_USE_EDCF);
  2617. }
  2618. static void b43_qos_update_work(struct work_struct *work)
  2619. {
  2620. struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work);
  2621. struct b43_wldev *dev;
  2622. mutex_lock(&wl->mutex);
  2623. dev = wl->current_dev;
  2624. if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED)))
  2625. b43_qos_update(dev);
  2626. mutex_unlock(&wl->mutex);
  2627. }
  2628. static int b43_op_conf_tx(struct ieee80211_hw *hw,
  2629. int _queue,
  2630. const struct ieee80211_tx_queue_params *params)
  2631. {
  2632. struct b43_wl *wl = hw_to_b43_wl(hw);
  2633. unsigned long flags;
  2634. unsigned int queue = (unsigned int)_queue;
  2635. struct b43_qos_params *p;
  2636. if (queue >= ARRAY_SIZE(wl->qos_params)) {
  2637. /* Queue not available or don't support setting
  2638. * params on this queue. Return success to not
  2639. * confuse mac80211. */
  2640. return 0;
  2641. }
  2642. spin_lock_irqsave(&wl->irq_lock, flags);
  2643. p = &(wl->qos_params[queue]);
  2644. memcpy(&(p->p), params, sizeof(p->p));
  2645. p->need_hw_update = 1;
  2646. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2647. queue_work(hw->workqueue, &wl->qos_update_work);
  2648. return 0;
  2649. }
  2650. static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
  2651. struct ieee80211_tx_queue_stats *stats)
  2652. {
  2653. struct b43_wl *wl = hw_to_b43_wl(hw);
  2654. struct b43_wldev *dev = wl->current_dev;
  2655. unsigned long flags;
  2656. int err = -ENODEV;
  2657. if (!dev)
  2658. goto out;
  2659. spin_lock_irqsave(&wl->irq_lock, flags);
  2660. if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
  2661. if (b43_using_pio_transfers(dev))
  2662. b43_pio_get_tx_stats(dev, stats);
  2663. else
  2664. b43_dma_get_tx_stats(dev, stats);
  2665. err = 0;
  2666. }
  2667. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2668. out:
  2669. return err;
  2670. }
  2671. static int b43_op_get_stats(struct ieee80211_hw *hw,
  2672. struct ieee80211_low_level_stats *stats)
  2673. {
  2674. struct b43_wl *wl = hw_to_b43_wl(hw);
  2675. unsigned long flags;
  2676. spin_lock_irqsave(&wl->irq_lock, flags);
  2677. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2678. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2679. return 0;
  2680. }
  2681. static void b43_put_phy_into_reset(struct b43_wldev *dev)
  2682. {
  2683. struct ssb_device *sdev = dev->dev;
  2684. u32 tmslow;
  2685. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2686. tmslow &= ~B43_TMSLOW_GMODE;
  2687. tmslow |= B43_TMSLOW_PHYRESET;
  2688. tmslow |= SSB_TMSLOW_FGC;
  2689. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2690. msleep(1);
  2691. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2692. tmslow &= ~SSB_TMSLOW_FGC;
  2693. tmslow |= B43_TMSLOW_PHYRESET;
  2694. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2695. msleep(1);
  2696. }
  2697. static const char * band_to_string(enum ieee80211_band band)
  2698. {
  2699. switch (band) {
  2700. case IEEE80211_BAND_5GHZ:
  2701. return "5";
  2702. case IEEE80211_BAND_2GHZ:
  2703. return "2.4";
  2704. default:
  2705. break;
  2706. }
  2707. B43_WARN_ON(1);
  2708. return "";
  2709. }
  2710. /* Expects wl->mutex locked */
  2711. static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
  2712. {
  2713. struct b43_wldev *up_dev = NULL;
  2714. struct b43_wldev *down_dev;
  2715. struct b43_wldev *d;
  2716. int err;
  2717. bool gmode;
  2718. int prev_status;
  2719. /* Find a device and PHY which supports the band. */
  2720. list_for_each_entry(d, &wl->devlist, list) {
  2721. switch (chan->band) {
  2722. case IEEE80211_BAND_5GHZ:
  2723. if (d->phy.supports_5ghz) {
  2724. up_dev = d;
  2725. gmode = 0;
  2726. }
  2727. break;
  2728. case IEEE80211_BAND_2GHZ:
  2729. if (d->phy.supports_2ghz) {
  2730. up_dev = d;
  2731. gmode = 1;
  2732. }
  2733. break;
  2734. default:
  2735. B43_WARN_ON(1);
  2736. return -EINVAL;
  2737. }
  2738. if (up_dev)
  2739. break;
  2740. }
  2741. if (!up_dev) {
  2742. b43err(wl, "Could not find a device for %s-GHz band operation\n",
  2743. band_to_string(chan->band));
  2744. return -ENODEV;
  2745. }
  2746. if ((up_dev == wl->current_dev) &&
  2747. (!!wl->current_dev->phy.gmode == !!gmode)) {
  2748. /* This device is already running. */
  2749. return 0;
  2750. }
  2751. b43dbg(wl, "Switching to %s-GHz band\n",
  2752. band_to_string(chan->band));
  2753. down_dev = wl->current_dev;
  2754. prev_status = b43_status(down_dev);
  2755. /* Shutdown the currently running core. */
  2756. if (prev_status >= B43_STAT_STARTED)
  2757. b43_wireless_core_stop(down_dev);
  2758. if (prev_status >= B43_STAT_INITIALIZED)
  2759. b43_wireless_core_exit(down_dev);
  2760. if (down_dev != up_dev) {
  2761. /* We switch to a different core, so we put PHY into
  2762. * RESET on the old core. */
  2763. b43_put_phy_into_reset(down_dev);
  2764. }
  2765. /* Now start the new core. */
  2766. up_dev->phy.gmode = gmode;
  2767. if (prev_status >= B43_STAT_INITIALIZED) {
  2768. err = b43_wireless_core_init(up_dev);
  2769. if (err) {
  2770. b43err(wl, "Fatal: Could not initialize device for "
  2771. "selected %s-GHz band\n",
  2772. band_to_string(chan->band));
  2773. goto init_failure;
  2774. }
  2775. }
  2776. if (prev_status >= B43_STAT_STARTED) {
  2777. err = b43_wireless_core_start(up_dev);
  2778. if (err) {
  2779. b43err(wl, "Fatal: Coult not start device for "
  2780. "selected %s-GHz band\n",
  2781. band_to_string(chan->band));
  2782. b43_wireless_core_exit(up_dev);
  2783. goto init_failure;
  2784. }
  2785. }
  2786. B43_WARN_ON(b43_status(up_dev) != prev_status);
  2787. wl->current_dev = up_dev;
  2788. return 0;
  2789. init_failure:
  2790. /* Whoops, failed to init the new core. No core is operating now. */
  2791. wl->current_dev = NULL;
  2792. return err;
  2793. }
  2794. static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  2795. {
  2796. struct b43_wl *wl = hw_to_b43_wl(hw);
  2797. struct b43_wldev *dev;
  2798. struct b43_phy *phy;
  2799. unsigned long flags;
  2800. int antenna;
  2801. int err = 0;
  2802. u32 savedirqs;
  2803. mutex_lock(&wl->mutex);
  2804. /* Switch the band (if necessary). This might change the active core. */
  2805. err = b43_switch_band(wl, conf->channel);
  2806. if (err)
  2807. goto out_unlock_mutex;
  2808. dev = wl->current_dev;
  2809. phy = &dev->phy;
  2810. /* Disable IRQs while reconfiguring the device.
  2811. * This makes it possible to drop the spinlock throughout
  2812. * the reconfiguration process. */
  2813. spin_lock_irqsave(&wl->irq_lock, flags);
  2814. if (b43_status(dev) < B43_STAT_STARTED) {
  2815. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2816. goto out_unlock_mutex;
  2817. }
  2818. savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
  2819. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2820. b43_synchronize_irq(dev);
  2821. /* Switch to the requested channel.
  2822. * The firmware takes care of races with the TX handler. */
  2823. if (conf->channel->hw_value != phy->channel)
  2824. b43_radio_selectchannel(dev, conf->channel->hw_value, 0);
  2825. /* Enable/Disable ShortSlot timing. */
  2826. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
  2827. dev->short_slot) {
  2828. B43_WARN_ON(phy->type != B43_PHYTYPE_G);
  2829. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2830. b43_short_slot_timing_enable(dev);
  2831. else
  2832. b43_short_slot_timing_disable(dev);
  2833. }
  2834. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  2835. /* Adjust the desired TX power level. */
  2836. if (conf->power_level != 0) {
  2837. if (conf->power_level != phy->power_level) {
  2838. phy->power_level = conf->power_level;
  2839. b43_phy_xmitpower(dev);
  2840. }
  2841. }
  2842. /* Antennas for RX and management frame TX. */
  2843. antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
  2844. b43_mgmtframe_txantenna(dev, antenna);
  2845. antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
  2846. b43_set_rx_antenna(dev, antenna);
  2847. /* Update templates for AP mode. */
  2848. if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2849. b43_set_beacon_int(dev, conf->beacon_int);
  2850. if (!!conf->radio_enabled != phy->radio_on) {
  2851. if (conf->radio_enabled) {
  2852. b43_radio_turn_on(dev);
  2853. b43info(dev->wl, "Radio turned on by software\n");
  2854. if (!dev->radio_hw_enable) {
  2855. b43info(dev->wl, "The hardware RF-kill button "
  2856. "still turns the radio physically off. "
  2857. "Press the button to turn it on.\n");
  2858. }
  2859. } else {
  2860. b43_radio_turn_off(dev, 0);
  2861. b43info(dev->wl, "Radio turned off by software\n");
  2862. }
  2863. }
  2864. spin_lock_irqsave(&wl->irq_lock, flags);
  2865. b43_interrupt_enable(dev, savedirqs);
  2866. mmiowb();
  2867. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2868. out_unlock_mutex:
  2869. mutex_unlock(&wl->mutex);
  2870. return err;
  2871. }
  2872. static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2873. const u8 *local_addr, const u8 *addr,
  2874. struct ieee80211_key_conf *key)
  2875. {
  2876. struct b43_wl *wl = hw_to_b43_wl(hw);
  2877. struct b43_wldev *dev;
  2878. unsigned long flags;
  2879. u8 algorithm;
  2880. u8 index;
  2881. int err;
  2882. DECLARE_MAC_BUF(mac);
  2883. if (modparam_nohwcrypt)
  2884. return -ENOSPC; /* User disabled HW-crypto */
  2885. mutex_lock(&wl->mutex);
  2886. spin_lock_irqsave(&wl->irq_lock, flags);
  2887. dev = wl->current_dev;
  2888. err = -ENODEV;
  2889. if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
  2890. goto out_unlock;
  2891. err = -EINVAL;
  2892. switch (key->alg) {
  2893. case ALG_WEP:
  2894. if (key->keylen == 5)
  2895. algorithm = B43_SEC_ALGO_WEP40;
  2896. else
  2897. algorithm = B43_SEC_ALGO_WEP104;
  2898. break;
  2899. case ALG_TKIP:
  2900. algorithm = B43_SEC_ALGO_TKIP;
  2901. break;
  2902. case ALG_CCMP:
  2903. algorithm = B43_SEC_ALGO_AES;
  2904. break;
  2905. default:
  2906. B43_WARN_ON(1);
  2907. goto out_unlock;
  2908. }
  2909. index = (u8) (key->keyidx);
  2910. if (index > 3)
  2911. goto out_unlock;
  2912. switch (cmd) {
  2913. case SET_KEY:
  2914. if (algorithm == B43_SEC_ALGO_TKIP) {
  2915. /* FIXME: No TKIP hardware encryption for now. */
  2916. err = -EOPNOTSUPP;
  2917. goto out_unlock;
  2918. }
  2919. if (is_broadcast_ether_addr(addr)) {
  2920. /* addr is FF:FF:FF:FF:FF:FF for default keys */
  2921. err = b43_key_write(dev, index, algorithm,
  2922. key->key, key->keylen, NULL, key);
  2923. } else {
  2924. /*
  2925. * either pairwise key or address is 00:00:00:00:00:00
  2926. * for transmit-only keys
  2927. */
  2928. err = b43_key_write(dev, -1, algorithm,
  2929. key->key, key->keylen, addr, key);
  2930. }
  2931. if (err)
  2932. goto out_unlock;
  2933. if (algorithm == B43_SEC_ALGO_WEP40 ||
  2934. algorithm == B43_SEC_ALGO_WEP104) {
  2935. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
  2936. } else {
  2937. b43_hf_write(dev,
  2938. b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
  2939. }
  2940. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  2941. break;
  2942. case DISABLE_KEY: {
  2943. err = b43_key_clear(dev, key->hw_key_idx);
  2944. if (err)
  2945. goto out_unlock;
  2946. break;
  2947. }
  2948. default:
  2949. B43_WARN_ON(1);
  2950. }
  2951. out_unlock:
  2952. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2953. mutex_unlock(&wl->mutex);
  2954. if (!err) {
  2955. b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
  2956. "mac: %s\n",
  2957. cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
  2958. print_mac(mac, addr));
  2959. }
  2960. return err;
  2961. }
  2962. static void b43_op_configure_filter(struct ieee80211_hw *hw,
  2963. unsigned int changed, unsigned int *fflags,
  2964. int mc_count, struct dev_addr_list *mc_list)
  2965. {
  2966. struct b43_wl *wl = hw_to_b43_wl(hw);
  2967. struct b43_wldev *dev = wl->current_dev;
  2968. unsigned long flags;
  2969. if (!dev) {
  2970. *fflags = 0;
  2971. return;
  2972. }
  2973. spin_lock_irqsave(&wl->irq_lock, flags);
  2974. *fflags &= FIF_PROMISC_IN_BSS |
  2975. FIF_ALLMULTI |
  2976. FIF_FCSFAIL |
  2977. FIF_PLCPFAIL |
  2978. FIF_CONTROL |
  2979. FIF_OTHER_BSS |
  2980. FIF_BCN_PRBRESP_PROMISC;
  2981. changed &= FIF_PROMISC_IN_BSS |
  2982. FIF_ALLMULTI |
  2983. FIF_FCSFAIL |
  2984. FIF_PLCPFAIL |
  2985. FIF_CONTROL |
  2986. FIF_OTHER_BSS |
  2987. FIF_BCN_PRBRESP_PROMISC;
  2988. wl->filter_flags = *fflags;
  2989. if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
  2990. b43_adjust_opmode(dev);
  2991. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2992. }
  2993. static int b43_op_config_interface(struct ieee80211_hw *hw,
  2994. struct ieee80211_vif *vif,
  2995. struct ieee80211_if_conf *conf)
  2996. {
  2997. struct b43_wl *wl = hw_to_b43_wl(hw);
  2998. struct b43_wldev *dev = wl->current_dev;
  2999. unsigned long flags;
  3000. if (!dev)
  3001. return -ENODEV;
  3002. mutex_lock(&wl->mutex);
  3003. spin_lock_irqsave(&wl->irq_lock, flags);
  3004. B43_WARN_ON(wl->vif != vif);
  3005. if (conf->bssid)
  3006. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  3007. else
  3008. memset(wl->bssid, 0, ETH_ALEN);
  3009. if (b43_status(dev) >= B43_STAT_INITIALIZED) {
  3010. if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  3011. B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
  3012. b43_set_ssid(dev, conf->ssid, conf->ssid_len);
  3013. if (conf->beacon) {
  3014. b43_update_templates(wl, conf->beacon,
  3015. conf->beacon_control);
  3016. }
  3017. }
  3018. b43_write_mac_bssid_templates(dev);
  3019. }
  3020. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3021. mutex_unlock(&wl->mutex);
  3022. return 0;
  3023. }
  3024. /* Locking: wl->mutex */
  3025. static void b43_wireless_core_stop(struct b43_wldev *dev)
  3026. {
  3027. struct b43_wl *wl = dev->wl;
  3028. unsigned long flags;
  3029. if (b43_status(dev) < B43_STAT_STARTED)
  3030. return;
  3031. /* Disable and sync interrupts. We must do this before than
  3032. * setting the status to INITIALIZED, as the interrupt handler
  3033. * won't care about IRQs then. */
  3034. spin_lock_irqsave(&wl->irq_lock, flags);
  3035. dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
  3036. b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
  3037. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3038. b43_synchronize_irq(dev);
  3039. b43_set_status(dev, B43_STAT_INITIALIZED);
  3040. b43_pio_stop(dev);
  3041. mutex_unlock(&wl->mutex);
  3042. /* Must unlock as it would otherwise deadlock. No races here.
  3043. * Cancel the possibly running self-rearming periodic work. */
  3044. cancel_delayed_work_sync(&dev->periodic_work);
  3045. mutex_lock(&wl->mutex);
  3046. ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
  3047. b43_mac_suspend(dev);
  3048. free_irq(dev->dev->irq, dev);
  3049. b43dbg(wl, "Wireless interface stopped\n");
  3050. }
  3051. /* Locking: wl->mutex */
  3052. static int b43_wireless_core_start(struct b43_wldev *dev)
  3053. {
  3054. int err;
  3055. B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
  3056. drain_txstatus_queue(dev);
  3057. err = request_irq(dev->dev->irq, b43_interrupt_handler,
  3058. IRQF_SHARED, KBUILD_MODNAME, dev);
  3059. if (err) {
  3060. b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
  3061. goto out;
  3062. }
  3063. /* We are ready to run. */
  3064. b43_set_status(dev, B43_STAT_STARTED);
  3065. /* Start data flow (TX/RX). */
  3066. b43_mac_enable(dev);
  3067. b43_interrupt_enable(dev, dev->irq_savedstate);
  3068. ieee80211_start_queues(dev->wl->hw);
  3069. /* Start maintainance work */
  3070. b43_periodic_tasks_setup(dev);
  3071. b43dbg(dev->wl, "Wireless interface started\n");
  3072. out:
  3073. return err;
  3074. }
  3075. /* Get PHY and RADIO versioning numbers */
  3076. static int b43_phy_versioning(struct b43_wldev *dev)
  3077. {
  3078. struct b43_phy *phy = &dev->phy;
  3079. u32 tmp;
  3080. u8 analog_type;
  3081. u8 phy_type;
  3082. u8 phy_rev;
  3083. u16 radio_manuf;
  3084. u16 radio_ver;
  3085. u16 radio_rev;
  3086. int unsupported = 0;
  3087. /* Get PHY versioning */
  3088. tmp = b43_read16(dev, B43_MMIO_PHY_VER);
  3089. analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
  3090. phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
  3091. phy_rev = (tmp & B43_PHYVER_VERSION);
  3092. switch (phy_type) {
  3093. case B43_PHYTYPE_A:
  3094. if (phy_rev >= 4)
  3095. unsupported = 1;
  3096. break;
  3097. case B43_PHYTYPE_B:
  3098. if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
  3099. && phy_rev != 7)
  3100. unsupported = 1;
  3101. break;
  3102. case B43_PHYTYPE_G:
  3103. if (phy_rev > 9)
  3104. unsupported = 1;
  3105. break;
  3106. #ifdef CONFIG_B43_NPHY
  3107. case B43_PHYTYPE_N:
  3108. if (phy_rev > 1)
  3109. unsupported = 1;
  3110. break;
  3111. #endif
  3112. default:
  3113. unsupported = 1;
  3114. };
  3115. if (unsupported) {
  3116. b43err(dev->wl, "FOUND UNSUPPORTED PHY "
  3117. "(Analog %u, Type %u, Revision %u)\n",
  3118. analog_type, phy_type, phy_rev);
  3119. return -EOPNOTSUPP;
  3120. }
  3121. b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  3122. analog_type, phy_type, phy_rev);
  3123. /* Get RADIO versioning */
  3124. if (dev->dev->bus->chip_id == 0x4317) {
  3125. if (dev->dev->bus->chip_rev == 0)
  3126. tmp = 0x3205017F;
  3127. else if (dev->dev->bus->chip_rev == 1)
  3128. tmp = 0x4205017F;
  3129. else
  3130. tmp = 0x5205017F;
  3131. } else {
  3132. b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
  3133. tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  3134. b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
  3135. tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
  3136. }
  3137. radio_manuf = (tmp & 0x00000FFF);
  3138. radio_ver = (tmp & 0x0FFFF000) >> 12;
  3139. radio_rev = (tmp & 0xF0000000) >> 28;
  3140. if (radio_manuf != 0x17F /* Broadcom */)
  3141. unsupported = 1;
  3142. switch (phy_type) {
  3143. case B43_PHYTYPE_A:
  3144. if (radio_ver != 0x2060)
  3145. unsupported = 1;
  3146. if (radio_rev != 1)
  3147. unsupported = 1;
  3148. if (radio_manuf != 0x17F)
  3149. unsupported = 1;
  3150. break;
  3151. case B43_PHYTYPE_B:
  3152. if ((radio_ver & 0xFFF0) != 0x2050)
  3153. unsupported = 1;
  3154. break;
  3155. case B43_PHYTYPE_G:
  3156. if (radio_ver != 0x2050)
  3157. unsupported = 1;
  3158. break;
  3159. case B43_PHYTYPE_N:
  3160. if (radio_ver != 0x2055)
  3161. unsupported = 1;
  3162. break;
  3163. default:
  3164. B43_WARN_ON(1);
  3165. }
  3166. if (unsupported) {
  3167. b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
  3168. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  3169. radio_manuf, radio_ver, radio_rev);
  3170. return -EOPNOTSUPP;
  3171. }
  3172. b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
  3173. radio_manuf, radio_ver, radio_rev);
  3174. phy->radio_manuf = radio_manuf;
  3175. phy->radio_ver = radio_ver;
  3176. phy->radio_rev = radio_rev;
  3177. phy->analog = analog_type;
  3178. phy->type = phy_type;
  3179. phy->rev = phy_rev;
  3180. return 0;
  3181. }
  3182. static void setup_struct_phy_for_init(struct b43_wldev *dev,
  3183. struct b43_phy *phy)
  3184. {
  3185. struct b43_txpower_lo_control *lo;
  3186. int i;
  3187. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  3188. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  3189. phy->aci_enable = 0;
  3190. phy->aci_wlan_automatic = 0;
  3191. phy->aci_hw_rssi = 0;
  3192. phy->radio_off_context.valid = 0;
  3193. lo = phy->lo_control;
  3194. if (lo) {
  3195. memset(lo, 0, sizeof(*(phy->lo_control)));
  3196. lo->rebuild = 1;
  3197. lo->tx_bias = 0xFF;
  3198. }
  3199. phy->max_lb_gain = 0;
  3200. phy->trsw_rx_gain = 0;
  3201. phy->txpwr_offset = 0;
  3202. /* NRSSI */
  3203. phy->nrssislope = 0;
  3204. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  3205. phy->nrssi[i] = -1000;
  3206. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  3207. phy->nrssi_lt[i] = i;
  3208. phy->lofcal = 0xFFFF;
  3209. phy->initval = 0xFFFF;
  3210. phy->interfmode = B43_INTERFMODE_NONE;
  3211. phy->channel = 0xFF;
  3212. phy->hardware_power_control = !!modparam_hwpctl;
  3213. /* PHY TX errors counter. */
  3214. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  3215. /* OFDM-table address caching. */
  3216. phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
  3217. }
  3218. static void setup_struct_wldev_for_init(struct b43_wldev *dev)
  3219. {
  3220. dev->dfq_valid = 0;
  3221. /* Assume the radio is enabled. If it's not enabled, the state will
  3222. * immediately get fixed on the first periodic work run. */
  3223. dev->radio_hw_enable = 1;
  3224. /* Stats */
  3225. memset(&dev->stats, 0, sizeof(dev->stats));
  3226. setup_struct_phy_for_init(dev, &dev->phy);
  3227. /* IRQ related flags */
  3228. dev->irq_reason = 0;
  3229. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  3230. dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
  3231. dev->mac_suspended = 1;
  3232. /* Noise calculation context */
  3233. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  3234. }
  3235. static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
  3236. {
  3237. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  3238. u32 hf;
  3239. if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
  3240. return;
  3241. if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
  3242. return;
  3243. hf = b43_hf_read(dev);
  3244. if (sprom->boardflags_lo & B43_BFL_BTCMOD)
  3245. hf |= B43_HF_BTCOEXALT;
  3246. else
  3247. hf |= B43_HF_BTCOEX;
  3248. b43_hf_write(dev, hf);
  3249. //TODO
  3250. }
  3251. static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
  3252. { //TODO
  3253. }
  3254. static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
  3255. {
  3256. #ifdef CONFIG_SSB_DRIVER_PCICORE
  3257. struct ssb_bus *bus = dev->dev->bus;
  3258. u32 tmp;
  3259. if (bus->pcicore.dev &&
  3260. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  3261. bus->pcicore.dev->id.revision <= 5) {
  3262. /* IMCFGLO timeouts workaround. */
  3263. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  3264. tmp &= ~SSB_IMCFGLO_REQTO;
  3265. tmp &= ~SSB_IMCFGLO_SERTO;
  3266. switch (bus->bustype) {
  3267. case SSB_BUSTYPE_PCI:
  3268. case SSB_BUSTYPE_PCMCIA:
  3269. tmp |= 0x32;
  3270. break;
  3271. case SSB_BUSTYPE_SSB:
  3272. tmp |= 0x53;
  3273. break;
  3274. }
  3275. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  3276. }
  3277. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  3278. }
  3279. /* Write the short and long frame retry limit values. */
  3280. static void b43_set_retry_limits(struct b43_wldev *dev,
  3281. unsigned int short_retry,
  3282. unsigned int long_retry)
  3283. {
  3284. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  3285. * the chip-internal counter. */
  3286. short_retry = min(short_retry, (unsigned int)0xF);
  3287. long_retry = min(long_retry, (unsigned int)0xF);
  3288. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
  3289. short_retry);
  3290. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
  3291. long_retry);
  3292. }
  3293. static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
  3294. {
  3295. u16 pu_delay;
  3296. /* The time value is in microseconds. */
  3297. if (dev->phy.type == B43_PHYTYPE_A)
  3298. pu_delay = 3700;
  3299. else
  3300. pu_delay = 1050;
  3301. if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle)
  3302. pu_delay = 500;
  3303. if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
  3304. pu_delay = max(pu_delay, (u16)2400);
  3305. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
  3306. }
  3307. /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
  3308. static void b43_set_pretbtt(struct b43_wldev *dev)
  3309. {
  3310. u16 pretbtt;
  3311. /* The time value is in microseconds. */
  3312. if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) {
  3313. pretbtt = 2;
  3314. } else {
  3315. if (dev->phy.type == B43_PHYTYPE_A)
  3316. pretbtt = 120;
  3317. else
  3318. pretbtt = 250;
  3319. }
  3320. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
  3321. b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
  3322. }
  3323. /* Shutdown a wireless core */
  3324. /* Locking: wl->mutex */
  3325. static void b43_wireless_core_exit(struct b43_wldev *dev)
  3326. {
  3327. struct b43_phy *phy = &dev->phy;
  3328. u32 macctl;
  3329. B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
  3330. if (b43_status(dev) != B43_STAT_INITIALIZED)
  3331. return;
  3332. b43_set_status(dev, B43_STAT_UNINIT);
  3333. /* Stop the microcode PSM. */
  3334. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  3335. macctl &= ~B43_MACCTL_PSM_RUN;
  3336. macctl |= B43_MACCTL_PSM_JMP0;
  3337. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  3338. if (!dev->suspend_in_progress) {
  3339. b43_leds_exit(dev);
  3340. b43_rng_exit(dev->wl);
  3341. }
  3342. b43_dma_free(dev);
  3343. b43_pio_free(dev);
  3344. b43_chip_exit(dev);
  3345. b43_radio_turn_off(dev, 1);
  3346. b43_switch_analog(dev, 0);
  3347. if (phy->dyn_tssi_tbl)
  3348. kfree(phy->tssi2dbm);
  3349. kfree(phy->lo_control);
  3350. phy->lo_control = NULL;
  3351. if (dev->wl->current_beacon) {
  3352. dev_kfree_skb_any(dev->wl->current_beacon);
  3353. dev->wl->current_beacon = NULL;
  3354. }
  3355. ssb_device_disable(dev->dev, 0);
  3356. ssb_bus_may_powerdown(dev->dev->bus);
  3357. }
  3358. /* Initialize a wireless core */
  3359. static int b43_wireless_core_init(struct b43_wldev *dev)
  3360. {
  3361. struct b43_wl *wl = dev->wl;
  3362. struct ssb_bus *bus = dev->dev->bus;
  3363. struct ssb_sprom *sprom = &bus->sprom;
  3364. struct b43_phy *phy = &dev->phy;
  3365. int err;
  3366. u32 hf, tmp;
  3367. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  3368. err = ssb_bus_powerup(bus, 0);
  3369. if (err)
  3370. goto out;
  3371. if (!ssb_device_is_enabled(dev->dev)) {
  3372. tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
  3373. b43_wireless_core_reset(dev, tmp);
  3374. }
  3375. if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
  3376. phy->lo_control =
  3377. kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
  3378. if (!phy->lo_control) {
  3379. err = -ENOMEM;
  3380. goto err_busdown;
  3381. }
  3382. }
  3383. setup_struct_wldev_for_init(dev);
  3384. err = b43_phy_init_tssi2dbm_table(dev);
  3385. if (err)
  3386. goto err_kfree_lo_control;
  3387. /* Enable IRQ routing to this device. */
  3388. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  3389. b43_imcfglo_timeouts_workaround(dev);
  3390. b43_bluetooth_coext_disable(dev);
  3391. b43_phy_early_init(dev);
  3392. err = b43_chip_init(dev);
  3393. if (err)
  3394. goto err_kfree_tssitbl;
  3395. b43_shm_write16(dev, B43_SHM_SHARED,
  3396. B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
  3397. hf = b43_hf_read(dev);
  3398. if (phy->type == B43_PHYTYPE_G) {
  3399. hf |= B43_HF_SYMW;
  3400. if (phy->rev == 1)
  3401. hf |= B43_HF_GDCW;
  3402. if (sprom->boardflags_lo & B43_BFL_PACTRL)
  3403. hf |= B43_HF_OFDMPABOOST;
  3404. } else if (phy->type == B43_PHYTYPE_B) {
  3405. hf |= B43_HF_SYMW;
  3406. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  3407. hf &= ~B43_HF_GDCW;
  3408. }
  3409. b43_hf_write(dev, hf);
  3410. b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
  3411. B43_DEFAULT_LONG_RETRY_LIMIT);
  3412. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
  3413. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
  3414. /* Disable sending probe responses from firmware.
  3415. * Setting the MaxTime to one usec will always trigger
  3416. * a timeout, so we never send any probe resp.
  3417. * A timeout of zero is infinite. */
  3418. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
  3419. b43_rate_memory_init(dev);
  3420. b43_set_phytxctl_defaults(dev);
  3421. /* Minimum Contention Window */
  3422. if (phy->type == B43_PHYTYPE_B) {
  3423. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
  3424. } else {
  3425. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
  3426. }
  3427. /* Maximum Contention Window */
  3428. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
  3429. if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
  3430. dev->__using_pio_transfers = 1;
  3431. err = b43_pio_init(dev);
  3432. } else {
  3433. dev->__using_pio_transfers = 0;
  3434. err = b43_dma_init(dev);
  3435. }
  3436. if (err)
  3437. goto err_chip_exit;
  3438. b43_qos_init(dev);
  3439. b43_set_synth_pu_delay(dev, 1);
  3440. b43_bluetooth_coext_enable(dev);
  3441. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  3442. b43_upload_card_macaddress(dev);
  3443. b43_security_init(dev);
  3444. if (!dev->suspend_in_progress)
  3445. b43_rng_init(wl);
  3446. b43_set_status(dev, B43_STAT_INITIALIZED);
  3447. if (!dev->suspend_in_progress)
  3448. b43_leds_init(dev);
  3449. out:
  3450. return err;
  3451. err_chip_exit:
  3452. b43_chip_exit(dev);
  3453. err_kfree_tssitbl:
  3454. if (phy->dyn_tssi_tbl)
  3455. kfree(phy->tssi2dbm);
  3456. err_kfree_lo_control:
  3457. kfree(phy->lo_control);
  3458. phy->lo_control = NULL;
  3459. err_busdown:
  3460. ssb_bus_may_powerdown(bus);
  3461. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  3462. return err;
  3463. }
  3464. static int b43_op_add_interface(struct ieee80211_hw *hw,
  3465. struct ieee80211_if_init_conf *conf)
  3466. {
  3467. struct b43_wl *wl = hw_to_b43_wl(hw);
  3468. struct b43_wldev *dev;
  3469. unsigned long flags;
  3470. int err = -EOPNOTSUPP;
  3471. /* TODO: allow WDS/AP devices to coexist */
  3472. if (conf->type != IEEE80211_IF_TYPE_AP &&
  3473. conf->type != IEEE80211_IF_TYPE_STA &&
  3474. conf->type != IEEE80211_IF_TYPE_WDS &&
  3475. conf->type != IEEE80211_IF_TYPE_IBSS)
  3476. return -EOPNOTSUPP;
  3477. mutex_lock(&wl->mutex);
  3478. if (wl->operating)
  3479. goto out_mutex_unlock;
  3480. b43dbg(wl, "Adding Interface type %d\n", conf->type);
  3481. dev = wl->current_dev;
  3482. wl->operating = 1;
  3483. wl->vif = conf->vif;
  3484. wl->if_type = conf->type;
  3485. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  3486. spin_lock_irqsave(&wl->irq_lock, flags);
  3487. b43_adjust_opmode(dev);
  3488. b43_set_pretbtt(dev);
  3489. b43_set_synth_pu_delay(dev, 0);
  3490. b43_upload_card_macaddress(dev);
  3491. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3492. err = 0;
  3493. out_mutex_unlock:
  3494. mutex_unlock(&wl->mutex);
  3495. return err;
  3496. }
  3497. static void b43_op_remove_interface(struct ieee80211_hw *hw,
  3498. struct ieee80211_if_init_conf *conf)
  3499. {
  3500. struct b43_wl *wl = hw_to_b43_wl(hw);
  3501. struct b43_wldev *dev = wl->current_dev;
  3502. unsigned long flags;
  3503. b43dbg(wl, "Removing Interface type %d\n", conf->type);
  3504. mutex_lock(&wl->mutex);
  3505. B43_WARN_ON(!wl->operating);
  3506. B43_WARN_ON(wl->vif != conf->vif);
  3507. wl->vif = NULL;
  3508. wl->operating = 0;
  3509. spin_lock_irqsave(&wl->irq_lock, flags);
  3510. b43_adjust_opmode(dev);
  3511. memset(wl->mac_addr, 0, ETH_ALEN);
  3512. b43_upload_card_macaddress(dev);
  3513. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3514. mutex_unlock(&wl->mutex);
  3515. }
  3516. static int b43_op_start(struct ieee80211_hw *hw)
  3517. {
  3518. struct b43_wl *wl = hw_to_b43_wl(hw);
  3519. struct b43_wldev *dev = wl->current_dev;
  3520. int did_init = 0;
  3521. int err = 0;
  3522. bool do_rfkill_exit = 0;
  3523. /* Kill all old instance specific information to make sure
  3524. * the card won't use it in the short timeframe between start
  3525. * and mac80211 reconfiguring it. */
  3526. memset(wl->bssid, 0, ETH_ALEN);
  3527. memset(wl->mac_addr, 0, ETH_ALEN);
  3528. wl->filter_flags = 0;
  3529. wl->radiotap_enabled = 0;
  3530. b43_qos_clear(wl);
  3531. /* First register RFkill.
  3532. * LEDs that are registered later depend on it. */
  3533. b43_rfkill_init(dev);
  3534. mutex_lock(&wl->mutex);
  3535. if (b43_status(dev) < B43_STAT_INITIALIZED) {
  3536. err = b43_wireless_core_init(dev);
  3537. if (err) {
  3538. do_rfkill_exit = 1;
  3539. goto out_mutex_unlock;
  3540. }
  3541. did_init = 1;
  3542. }
  3543. if (b43_status(dev) < B43_STAT_STARTED) {
  3544. err = b43_wireless_core_start(dev);
  3545. if (err) {
  3546. if (did_init)
  3547. b43_wireless_core_exit(dev);
  3548. do_rfkill_exit = 1;
  3549. goto out_mutex_unlock;
  3550. }
  3551. }
  3552. out_mutex_unlock:
  3553. mutex_unlock(&wl->mutex);
  3554. if (do_rfkill_exit)
  3555. b43_rfkill_exit(dev);
  3556. return err;
  3557. }
  3558. static void b43_op_stop(struct ieee80211_hw *hw)
  3559. {
  3560. struct b43_wl *wl = hw_to_b43_wl(hw);
  3561. struct b43_wldev *dev = wl->current_dev;
  3562. b43_rfkill_exit(dev);
  3563. cancel_work_sync(&(wl->qos_update_work));
  3564. cancel_work_sync(&(wl->beacon_update_trigger));
  3565. mutex_lock(&wl->mutex);
  3566. if (b43_status(dev) >= B43_STAT_STARTED)
  3567. b43_wireless_core_stop(dev);
  3568. b43_wireless_core_exit(dev);
  3569. mutex_unlock(&wl->mutex);
  3570. }
  3571. static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
  3572. u32 short_retry_limit, u32 long_retry_limit)
  3573. {
  3574. struct b43_wl *wl = hw_to_b43_wl(hw);
  3575. struct b43_wldev *dev;
  3576. int err = 0;
  3577. mutex_lock(&wl->mutex);
  3578. dev = wl->current_dev;
  3579. if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
  3580. err = -ENODEV;
  3581. goto out_unlock;
  3582. }
  3583. b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
  3584. out_unlock:
  3585. mutex_unlock(&wl->mutex);
  3586. return err;
  3587. }
  3588. static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
  3589. {
  3590. struct b43_wl *wl = hw_to_b43_wl(hw);
  3591. struct sk_buff *beacon;
  3592. unsigned long flags;
  3593. struct ieee80211_tx_control txctl;
  3594. /* We could modify the existing beacon and set the aid bit in
  3595. * the TIM field, but that would probably require resizing and
  3596. * moving of data within the beacon template.
  3597. * Simply request a new beacon and let mac80211 do the hard work. */
  3598. beacon = ieee80211_beacon_get(hw, wl->vif, &txctl);
  3599. if (unlikely(!beacon))
  3600. return -ENOMEM;
  3601. spin_lock_irqsave(&wl->irq_lock, flags);
  3602. b43_update_templates(wl, beacon, &txctl);
  3603. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3604. return 0;
  3605. }
  3606. static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
  3607. struct sk_buff *beacon,
  3608. struct ieee80211_tx_control *ctl)
  3609. {
  3610. struct b43_wl *wl = hw_to_b43_wl(hw);
  3611. unsigned long flags;
  3612. spin_lock_irqsave(&wl->irq_lock, flags);
  3613. b43_update_templates(wl, beacon, ctl);
  3614. spin_unlock_irqrestore(&wl->irq_lock, flags);
  3615. return 0;
  3616. }
  3617. static void b43_op_sta_notify(struct ieee80211_hw *hw,
  3618. struct ieee80211_vif *vif,
  3619. enum sta_notify_cmd notify_cmd,
  3620. const u8 *addr)
  3621. {
  3622. struct b43_wl *wl = hw_to_b43_wl(hw);
  3623. B43_WARN_ON(!vif || wl->vif != vif);
  3624. }
  3625. static const struct ieee80211_ops b43_hw_ops = {
  3626. .tx = b43_op_tx,
  3627. .conf_tx = b43_op_conf_tx,
  3628. .add_interface = b43_op_add_interface,
  3629. .remove_interface = b43_op_remove_interface,
  3630. .config = b43_op_config,
  3631. .config_interface = b43_op_config_interface,
  3632. .configure_filter = b43_op_configure_filter,
  3633. .set_key = b43_op_set_key,
  3634. .get_stats = b43_op_get_stats,
  3635. .get_tx_stats = b43_op_get_tx_stats,
  3636. .start = b43_op_start,
  3637. .stop = b43_op_stop,
  3638. .set_retry_limit = b43_op_set_retry_limit,
  3639. .set_tim = b43_op_beacon_set_tim,
  3640. .beacon_update = b43_op_ibss_beacon_update,
  3641. .sta_notify = b43_op_sta_notify,
  3642. };
  3643. /* Hard-reset the chip. Do not call this directly.
  3644. * Use b43_controller_restart()
  3645. */
  3646. static void b43_chip_reset(struct work_struct *work)
  3647. {
  3648. struct b43_wldev *dev =
  3649. container_of(work, struct b43_wldev, restart_work);
  3650. struct b43_wl *wl = dev->wl;
  3651. int err = 0;
  3652. int prev_status;
  3653. mutex_lock(&wl->mutex);
  3654. prev_status = b43_status(dev);
  3655. /* Bring the device down... */
  3656. if (prev_status >= B43_STAT_STARTED)
  3657. b43_wireless_core_stop(dev);
  3658. if (prev_status >= B43_STAT_INITIALIZED)
  3659. b43_wireless_core_exit(dev);
  3660. /* ...and up again. */
  3661. if (prev_status >= B43_STAT_INITIALIZED) {
  3662. err = b43_wireless_core_init(dev);
  3663. if (err)
  3664. goto out;
  3665. }
  3666. if (prev_status >= B43_STAT_STARTED) {
  3667. err = b43_wireless_core_start(dev);
  3668. if (err) {
  3669. b43_wireless_core_exit(dev);
  3670. goto out;
  3671. }
  3672. }
  3673. out:
  3674. mutex_unlock(&wl->mutex);
  3675. if (err)
  3676. b43err(wl, "Controller restart FAILED\n");
  3677. else
  3678. b43info(wl, "Controller restarted\n");
  3679. }
  3680. static int b43_setup_bands(struct b43_wldev *dev,
  3681. bool have_2ghz_phy, bool have_5ghz_phy)
  3682. {
  3683. struct ieee80211_hw *hw = dev->wl->hw;
  3684. if (have_2ghz_phy)
  3685. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
  3686. if (dev->phy.type == B43_PHYTYPE_N) {
  3687. if (have_5ghz_phy)
  3688. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
  3689. } else {
  3690. if (have_5ghz_phy)
  3691. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
  3692. }
  3693. dev->phy.supports_2ghz = have_2ghz_phy;
  3694. dev->phy.supports_5ghz = have_5ghz_phy;
  3695. return 0;
  3696. }
  3697. static void b43_wireless_core_detach(struct b43_wldev *dev)
  3698. {
  3699. /* We release firmware that late to not be required to re-request
  3700. * is all the time when we reinit the core. */
  3701. b43_release_firmware(dev);
  3702. }
  3703. static int b43_wireless_core_attach(struct b43_wldev *dev)
  3704. {
  3705. struct b43_wl *wl = dev->wl;
  3706. struct ssb_bus *bus = dev->dev->bus;
  3707. struct pci_dev *pdev = bus->host_pci;
  3708. int err;
  3709. bool have_2ghz_phy = 0, have_5ghz_phy = 0;
  3710. u32 tmp;
  3711. /* Do NOT do any device initialization here.
  3712. * Do it in wireless_core_init() instead.
  3713. * This function is for gathering basic information about the HW, only.
  3714. * Also some structs may be set up here. But most likely you want to have
  3715. * that in core_init(), too.
  3716. */
  3717. err = ssb_bus_powerup(bus, 0);
  3718. if (err) {
  3719. b43err(wl, "Bus powerup failed\n");
  3720. goto out;
  3721. }
  3722. /* Get the PHY type. */
  3723. if (dev->dev->id.revision >= 5) {
  3724. u32 tmshigh;
  3725. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  3726. have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
  3727. have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
  3728. } else
  3729. B43_WARN_ON(1);
  3730. dev->phy.gmode = have_2ghz_phy;
  3731. tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
  3732. b43_wireless_core_reset(dev, tmp);
  3733. err = b43_phy_versioning(dev);
  3734. if (err)
  3735. goto err_powerdown;
  3736. /* Check if this device supports multiband. */
  3737. if (!pdev ||
  3738. (pdev->device != 0x4312 &&
  3739. pdev->device != 0x4319 && pdev->device != 0x4324)) {
  3740. /* No multiband support. */
  3741. have_2ghz_phy = 0;
  3742. have_5ghz_phy = 0;
  3743. switch (dev->phy.type) {
  3744. case B43_PHYTYPE_A:
  3745. have_5ghz_phy = 1;
  3746. break;
  3747. case B43_PHYTYPE_G:
  3748. case B43_PHYTYPE_N:
  3749. have_2ghz_phy = 1;
  3750. break;
  3751. default:
  3752. B43_WARN_ON(1);
  3753. }
  3754. }
  3755. if (dev->phy.type == B43_PHYTYPE_A) {
  3756. /* FIXME */
  3757. b43err(wl, "IEEE 802.11a devices are unsupported\n");
  3758. err = -EOPNOTSUPP;
  3759. goto err_powerdown;
  3760. }
  3761. dev->phy.gmode = have_2ghz_phy;
  3762. tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
  3763. b43_wireless_core_reset(dev, tmp);
  3764. err = b43_validate_chipaccess(dev);
  3765. if (err)
  3766. goto err_powerdown;
  3767. err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
  3768. if (err)
  3769. goto err_powerdown;
  3770. /* Now set some default "current_dev" */
  3771. if (!wl->current_dev)
  3772. wl->current_dev = dev;
  3773. INIT_WORK(&dev->restart_work, b43_chip_reset);
  3774. b43_radio_turn_off(dev, 1);
  3775. b43_switch_analog(dev, 0);
  3776. ssb_device_disable(dev->dev, 0);
  3777. ssb_bus_may_powerdown(bus);
  3778. out:
  3779. return err;
  3780. err_powerdown:
  3781. ssb_bus_may_powerdown(bus);
  3782. return err;
  3783. }
  3784. static void b43_one_core_detach(struct ssb_device *dev)
  3785. {
  3786. struct b43_wldev *wldev;
  3787. struct b43_wl *wl;
  3788. wldev = ssb_get_drvdata(dev);
  3789. wl = wldev->wl;
  3790. cancel_work_sync(&wldev->restart_work);
  3791. b43_debugfs_remove_device(wldev);
  3792. b43_wireless_core_detach(wldev);
  3793. list_del(&wldev->list);
  3794. wl->nr_devs--;
  3795. ssb_set_drvdata(dev, NULL);
  3796. kfree(wldev);
  3797. }
  3798. static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
  3799. {
  3800. struct b43_wldev *wldev;
  3801. struct pci_dev *pdev;
  3802. int err = -ENOMEM;
  3803. if (!list_empty(&wl->devlist)) {
  3804. /* We are not the first core on this chip. */
  3805. pdev = dev->bus->host_pci;
  3806. /* Only special chips support more than one wireless
  3807. * core, although some of the other chips have more than
  3808. * one wireless core as well. Check for this and
  3809. * bail out early.
  3810. */
  3811. if (!pdev ||
  3812. ((pdev->device != 0x4321) &&
  3813. (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
  3814. b43dbg(wl, "Ignoring unconnected 802.11 core\n");
  3815. return -ENODEV;
  3816. }
  3817. }
  3818. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3819. if (!wldev)
  3820. goto out;
  3821. wldev->dev = dev;
  3822. wldev->wl = wl;
  3823. b43_set_status(wldev, B43_STAT_UNINIT);
  3824. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3825. tasklet_init(&wldev->isr_tasklet,
  3826. (void (*)(unsigned long))b43_interrupt_tasklet,
  3827. (unsigned long)wldev);
  3828. INIT_LIST_HEAD(&wldev->list);
  3829. err = b43_wireless_core_attach(wldev);
  3830. if (err)
  3831. goto err_kfree_wldev;
  3832. list_add(&wldev->list, &wl->devlist);
  3833. wl->nr_devs++;
  3834. ssb_set_drvdata(dev, wldev);
  3835. b43_debugfs_add_device(wldev);
  3836. out:
  3837. return err;
  3838. err_kfree_wldev:
  3839. kfree(wldev);
  3840. return err;
  3841. }
  3842. static void b43_sprom_fixup(struct ssb_bus *bus)
  3843. {
  3844. /* boardflags workarounds */
  3845. if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
  3846. bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
  3847. bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
  3848. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3849. bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
  3850. bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
  3851. }
  3852. static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
  3853. {
  3854. struct ieee80211_hw *hw = wl->hw;
  3855. ssb_set_devtypedata(dev, NULL);
  3856. ieee80211_free_hw(hw);
  3857. }
  3858. static int b43_wireless_init(struct ssb_device *dev)
  3859. {
  3860. struct ssb_sprom *sprom = &dev->bus->sprom;
  3861. struct ieee80211_hw *hw;
  3862. struct b43_wl *wl;
  3863. int err = -ENOMEM;
  3864. b43_sprom_fixup(dev->bus);
  3865. hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
  3866. if (!hw) {
  3867. b43err(NULL, "Could not allocate ieee80211 device\n");
  3868. goto out;
  3869. }
  3870. /* fill hw info */
  3871. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3872. IEEE80211_HW_RX_INCLUDES_FCS;
  3873. hw->max_signal = 100;
  3874. hw->max_rssi = -110;
  3875. hw->max_noise = -110;
  3876. hw->queues = b43_modparam_qos ? 4 : 1;
  3877. SET_IEEE80211_DEV(hw, dev->dev);
  3878. if (is_valid_ether_addr(sprom->et1mac))
  3879. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  3880. else
  3881. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  3882. /* Get and initialize struct b43_wl */
  3883. wl = hw_to_b43_wl(hw);
  3884. memset(wl, 0, sizeof(*wl));
  3885. wl->hw = hw;
  3886. spin_lock_init(&wl->irq_lock);
  3887. spin_lock_init(&wl->leds_lock);
  3888. spin_lock_init(&wl->shm_lock);
  3889. mutex_init(&wl->mutex);
  3890. INIT_LIST_HEAD(&wl->devlist);
  3891. INIT_WORK(&wl->qos_update_work, b43_qos_update_work);
  3892. INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
  3893. ssb_set_devtypedata(dev, wl);
  3894. b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3895. err = 0;
  3896. out:
  3897. return err;
  3898. }
  3899. static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
  3900. {
  3901. struct b43_wl *wl;
  3902. int err;
  3903. int first = 0;
  3904. wl = ssb_get_devtypedata(dev);
  3905. if (!wl) {
  3906. /* Probing the first core. Must setup common struct b43_wl */
  3907. first = 1;
  3908. err = b43_wireless_init(dev);
  3909. if (err)
  3910. goto out;
  3911. wl = ssb_get_devtypedata(dev);
  3912. B43_WARN_ON(!wl);
  3913. }
  3914. err = b43_one_core_attach(dev, wl);
  3915. if (err)
  3916. goto err_wireless_exit;
  3917. if (first) {
  3918. err = ieee80211_register_hw(wl->hw);
  3919. if (err)
  3920. goto err_one_core_detach;
  3921. }
  3922. out:
  3923. return err;
  3924. err_one_core_detach:
  3925. b43_one_core_detach(dev);
  3926. err_wireless_exit:
  3927. if (first)
  3928. b43_wireless_exit(dev, wl);
  3929. return err;
  3930. }
  3931. static void b43_remove(struct ssb_device *dev)
  3932. {
  3933. struct b43_wl *wl = ssb_get_devtypedata(dev);
  3934. struct b43_wldev *wldev = ssb_get_drvdata(dev);
  3935. B43_WARN_ON(!wl);
  3936. if (wl->current_dev == wldev)
  3937. ieee80211_unregister_hw(wl->hw);
  3938. b43_one_core_detach(dev);
  3939. if (list_empty(&wl->devlist)) {
  3940. /* Last core on the chip unregistered.
  3941. * We can destroy common struct b43_wl.
  3942. */
  3943. b43_wireless_exit(dev, wl);
  3944. }
  3945. }
  3946. /* Perform a hardware reset. This can be called from any context. */
  3947. void b43_controller_restart(struct b43_wldev *dev, const char *reason)
  3948. {
  3949. /* Must avoid requeueing, if we are in shutdown. */
  3950. if (b43_status(dev) < B43_STAT_INITIALIZED)
  3951. return;
  3952. b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
  3953. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3954. }
  3955. #ifdef CONFIG_PM
  3956. static int b43_suspend(struct ssb_device *dev, pm_message_t state)
  3957. {
  3958. struct b43_wldev *wldev = ssb_get_drvdata(dev);
  3959. struct b43_wl *wl = wldev->wl;
  3960. b43dbg(wl, "Suspending...\n");
  3961. mutex_lock(&wl->mutex);
  3962. wldev->suspend_in_progress = true;
  3963. wldev->suspend_init_status = b43_status(wldev);
  3964. if (wldev->suspend_init_status >= B43_STAT_STARTED)
  3965. b43_wireless_core_stop(wldev);
  3966. if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
  3967. b43_wireless_core_exit(wldev);
  3968. mutex_unlock(&wl->mutex);
  3969. b43dbg(wl, "Device suspended.\n");
  3970. return 0;
  3971. }
  3972. static int b43_resume(struct ssb_device *dev)
  3973. {
  3974. struct b43_wldev *wldev = ssb_get_drvdata(dev);
  3975. struct b43_wl *wl = wldev->wl;
  3976. int err = 0;
  3977. b43dbg(wl, "Resuming...\n");
  3978. mutex_lock(&wl->mutex);
  3979. if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
  3980. err = b43_wireless_core_init(wldev);
  3981. if (err) {
  3982. b43err(wl, "Resume failed at core init\n");
  3983. goto out;
  3984. }
  3985. }
  3986. if (wldev->suspend_init_status >= B43_STAT_STARTED) {
  3987. err = b43_wireless_core_start(wldev);
  3988. if (err) {
  3989. b43_leds_exit(wldev);
  3990. b43_rng_exit(wldev->wl);
  3991. b43_wireless_core_exit(wldev);
  3992. b43err(wl, "Resume failed at core start\n");
  3993. goto out;
  3994. }
  3995. }
  3996. b43dbg(wl, "Device resumed.\n");
  3997. out:
  3998. wldev->suspend_in_progress = false;
  3999. mutex_unlock(&wl->mutex);
  4000. return err;
  4001. }
  4002. #else /* CONFIG_PM */
  4003. # define b43_suspend NULL
  4004. # define b43_resume NULL
  4005. #endif /* CONFIG_PM */
  4006. static struct ssb_driver b43_ssb_driver = {
  4007. .name = KBUILD_MODNAME,
  4008. .id_table = b43_ssb_tbl,
  4009. .probe = b43_probe,
  4010. .remove = b43_remove,
  4011. .suspend = b43_suspend,
  4012. .resume = b43_resume,
  4013. };
  4014. static void b43_print_driverinfo(void)
  4015. {
  4016. const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
  4017. *feat_leds = "", *feat_rfkill = "";
  4018. #ifdef CONFIG_B43_PCI_AUTOSELECT
  4019. feat_pci = "P";
  4020. #endif
  4021. #ifdef CONFIG_B43_PCMCIA
  4022. feat_pcmcia = "M";
  4023. #endif
  4024. #ifdef CONFIG_B43_NPHY
  4025. feat_nphy = "N";
  4026. #endif
  4027. #ifdef CONFIG_B43_LEDS
  4028. feat_leds = "L";
  4029. #endif
  4030. #ifdef CONFIG_B43_RFKILL
  4031. feat_rfkill = "R";
  4032. #endif
  4033. printk(KERN_INFO "Broadcom 43xx driver loaded "
  4034. "[ Features: %s%s%s%s%s, Firmware-ID: "
  4035. B43_SUPPORTED_FIRMWARE_ID " ]\n",
  4036. feat_pci, feat_pcmcia, feat_nphy,
  4037. feat_leds, feat_rfkill);
  4038. }
  4039. static int __init b43_init(void)
  4040. {
  4041. int err;
  4042. b43_debugfs_init();
  4043. err = b43_pcmcia_init();
  4044. if (err)
  4045. goto err_dfs_exit;
  4046. err = ssb_driver_register(&b43_ssb_driver);
  4047. if (err)
  4048. goto err_pcmcia_exit;
  4049. b43_print_driverinfo();
  4050. return err;
  4051. err_pcmcia_exit:
  4052. b43_pcmcia_exit();
  4053. err_dfs_exit:
  4054. b43_debugfs_exit();
  4055. return err;
  4056. }
  4057. static void __exit b43_exit(void)
  4058. {
  4059. ssb_driver_unregister(&b43_ssb_driver);
  4060. b43_pcmcia_exit();
  4061. b43_debugfs_exit();
  4062. }
  4063. module_init(b43_init)
  4064. module_exit(b43_exit)