sata_mv.c 83 KB

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  1. /*
  2. * sata_mv.c - Marvell SATA support
  3. *
  4. * Copyright 2008: Marvell Corporation, all rights reserved.
  5. * Copyright 2005: EMC Corporation, all rights reserved.
  6. * Copyright 2005 Red Hat, Inc. All rights reserved.
  7. *
  8. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; version 2 of the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. /*
  25. sata_mv TODO list:
  26. 1) Needs a full errata audit for all chipsets. I implemented most
  27. of the errata workarounds found in the Marvell vendor driver, but
  28. I distinctly remember a couple workarounds (one related to PCI-X)
  29. are still needed.
  30. 2) Improve/fix IRQ and error handling sequences.
  31. 3) ATAPI support (Marvell claims the 60xx/70xx chips can do it).
  32. 4) Think about TCQ support here, and for libata in general
  33. with controllers that suppport it via host-queuing hardware
  34. (a software-only implementation could be a nightmare).
  35. 5) Investigate problems with PCI Message Signalled Interrupts (MSI).
  36. 6) Cache frequently-accessed registers in mv_port_priv to reduce overhead.
  37. 7) Fix/reenable hot plug/unplug (should happen as a side-effect of (2) above).
  38. 8) Develop a low-power-consumption strategy, and implement it.
  39. 9) [Experiment, low priority] See if ATAPI can be supported using
  40. "unknown FIS" or "vendor-specific FIS" support, or something creative
  41. like that.
  42. 10) [Experiment, low priority] Investigate interrupt coalescing.
  43. Quite often, especially with PCI Message Signalled Interrupts (MSI),
  44. the overhead reduced by interrupt mitigation is quite often not
  45. worth the latency cost.
  46. 11) [Experiment, Marvell value added] Is it possible to use target
  47. mode to cross-connect two Linux boxes with Marvell cards? If so,
  48. creating LibATA target mode support would be very interesting.
  49. Target mode, for those without docs, is the ability to directly
  50. connect two SATA controllers.
  51. */
  52. #include <linux/kernel.h>
  53. #include <linux/module.h>
  54. #include <linux/pci.h>
  55. #include <linux/init.h>
  56. #include <linux/blkdev.h>
  57. #include <linux/delay.h>
  58. #include <linux/interrupt.h>
  59. #include <linux/dmapool.h>
  60. #include <linux/dma-mapping.h>
  61. #include <linux/device.h>
  62. #include <linux/platform_device.h>
  63. #include <linux/ata_platform.h>
  64. #include <linux/mbus.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi_cmnd.h>
  67. #include <scsi/scsi_device.h>
  68. #include <linux/libata.h>
  69. #define DRV_NAME "sata_mv"
  70. #define DRV_VERSION "1.20"
  71. enum {
  72. /* BAR's are enumerated in terms of pci_resource_start() terms */
  73. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  74. MV_IO_BAR = 2, /* offset 0x18: IO space */
  75. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  76. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  77. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  78. MV_PCI_REG_BASE = 0,
  79. MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
  80. MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
  81. MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
  82. MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
  83. MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
  84. MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
  85. MV_SATAHC0_REG_BASE = 0x20000,
  86. MV_FLASH_CTL = 0x1046c,
  87. MV_GPIO_PORT_CTL = 0x104f0,
  88. MV_RESET_CFG = 0x180d8,
  89. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  90. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  91. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  92. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  93. MV_MAX_Q_DEPTH = 32,
  94. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  95. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  96. * CRPB needs alignment on a 256B boundary. Size == 256B
  97. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  98. */
  99. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  100. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  101. MV_MAX_SG_CT = 256,
  102. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  103. MV_PORTS_PER_HC = 4,
  104. /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
  105. MV_PORT_HC_SHIFT = 2,
  106. /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
  107. MV_PORT_MASK = 3,
  108. /* Host Flags */
  109. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  110. MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
  111. /* SoC integrated controllers, no PCI interface */
  112. MV_FLAG_SOC = (1 << 28),
  113. MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  114. ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
  115. ATA_FLAG_PIO_POLLING,
  116. MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
  117. CRQB_FLAG_READ = (1 << 0),
  118. CRQB_TAG_SHIFT = 1,
  119. CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
  120. CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
  121. CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
  122. CRQB_CMD_ADDR_SHIFT = 8,
  123. CRQB_CMD_CS = (0x2 << 11),
  124. CRQB_CMD_LAST = (1 << 15),
  125. CRPB_FLAG_STATUS_SHIFT = 8,
  126. CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
  127. CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
  128. EPRD_FLAG_END_OF_TBL = (1 << 31),
  129. /* PCI interface registers */
  130. PCI_COMMAND_OFS = 0xc00,
  131. PCI_MAIN_CMD_STS_OFS = 0xd30,
  132. STOP_PCI_MASTER = (1 << 2),
  133. PCI_MASTER_EMPTY = (1 << 3),
  134. GLOB_SFT_RST = (1 << 4),
  135. MV_PCI_MODE = 0xd00,
  136. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  137. MV_PCI_DISC_TIMER = 0xd04,
  138. MV_PCI_MSI_TRIGGER = 0xc38,
  139. MV_PCI_SERR_MASK = 0xc28,
  140. MV_PCI_XBAR_TMOUT = 0x1d04,
  141. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  142. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  143. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  144. MV_PCI_ERR_COMMAND = 0x1d50,
  145. PCI_IRQ_CAUSE_OFS = 0x1d58,
  146. PCI_IRQ_MASK_OFS = 0x1d5c,
  147. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  148. PCIE_IRQ_CAUSE_OFS = 0x1900,
  149. PCIE_IRQ_MASK_OFS = 0x1910,
  150. PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
  151. HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
  152. HC_MAIN_IRQ_MASK_OFS = 0x1d64,
  153. HC_SOC_MAIN_IRQ_CAUSE_OFS = 0x20020,
  154. HC_SOC_MAIN_IRQ_MASK_OFS = 0x20024,
  155. PORT0_ERR = (1 << 0), /* shift by port # */
  156. PORT0_DONE = (1 << 1), /* shift by port # */
  157. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  158. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  159. PCI_ERR = (1 << 18),
  160. TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
  161. TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
  162. PORTS_0_3_COAL_DONE = (1 << 8),
  163. PORTS_4_7_COAL_DONE = (1 << 17),
  164. PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
  165. GPIO_INT = (1 << 22),
  166. SELF_INT = (1 << 23),
  167. TWSI_INT = (1 << 24),
  168. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  169. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  170. HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
  171. HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
  172. PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
  173. HC_MAIN_RSVD),
  174. HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  175. HC_MAIN_RSVD_5),
  176. HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
  177. /* SATAHC registers */
  178. HC_CFG_OFS = 0,
  179. HC_IRQ_CAUSE_OFS = 0x14,
  180. CRPB_DMA_DONE = (1 << 0), /* shift by port # */
  181. HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
  182. DEV_IRQ = (1 << 8), /* shift by port # */
  183. /* Shadow block registers */
  184. SHD_BLK_OFS = 0x100,
  185. SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
  186. /* SATA registers */
  187. SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
  188. SATA_ACTIVE_OFS = 0x350,
  189. SATA_FIS_IRQ_CAUSE_OFS = 0x364,
  190. LTMODE_OFS = 0x30c,
  191. LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
  192. PHY_MODE3 = 0x310,
  193. PHY_MODE4 = 0x314,
  194. PHY_MODE2 = 0x330,
  195. SATA_IFCTL_OFS = 0x344,
  196. SATA_IFSTAT_OFS = 0x34c,
  197. VENDOR_UNIQUE_FIS_OFS = 0x35c,
  198. FIS_CFG_OFS = 0x360,
  199. FIS_CFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
  200. MV5_PHY_MODE = 0x74,
  201. MV5_LT_MODE = 0x30,
  202. MV5_PHY_CTL = 0x0C,
  203. SATA_INTERFACE_CFG = 0x050,
  204. MV_M2_PREAMP_MASK = 0x7e0,
  205. /* Port registers */
  206. EDMA_CFG_OFS = 0,
  207. EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
  208. EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
  209. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  210. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  211. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  212. EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
  213. EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
  214. EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
  215. EDMA_ERR_IRQ_MASK_OFS = 0xc,
  216. EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
  217. EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
  218. EDMA_ERR_DEV = (1 << 2), /* device error */
  219. EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
  220. EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
  221. EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
  222. EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
  223. EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
  224. EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
  225. EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
  226. EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
  227. EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
  228. EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
  229. EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
  230. EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
  231. EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
  232. EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
  233. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
  234. EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
  235. EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
  236. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
  237. EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
  238. EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
  239. EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
  240. EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
  241. EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
  242. EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
  243. EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
  244. EDMA_ERR_OVERRUN_5 = (1 << 5),
  245. EDMA_ERR_UNDERRUN_5 = (1 << 6),
  246. EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
  247. EDMA_ERR_LNK_CTRL_RX_1 |
  248. EDMA_ERR_LNK_CTRL_RX_3 |
  249. EDMA_ERR_LNK_CTRL_TX |
  250. /* temporary, until we fix hotplug: */
  251. (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON),
  252. EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
  253. EDMA_ERR_PRD_PAR |
  254. EDMA_ERR_DEV_DCON |
  255. EDMA_ERR_DEV_CON |
  256. EDMA_ERR_SERR |
  257. EDMA_ERR_SELF_DIS |
  258. EDMA_ERR_CRQB_PAR |
  259. EDMA_ERR_CRPB_PAR |
  260. EDMA_ERR_INTRL_PAR |
  261. EDMA_ERR_IORDY |
  262. EDMA_ERR_LNK_CTRL_RX_2 |
  263. EDMA_ERR_LNK_DATA_RX |
  264. EDMA_ERR_LNK_DATA_TX |
  265. EDMA_ERR_TRANS_PROTO,
  266. EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
  267. EDMA_ERR_PRD_PAR |
  268. EDMA_ERR_DEV_DCON |
  269. EDMA_ERR_DEV_CON |
  270. EDMA_ERR_OVERRUN_5 |
  271. EDMA_ERR_UNDERRUN_5 |
  272. EDMA_ERR_SELF_DIS_5 |
  273. EDMA_ERR_CRQB_PAR |
  274. EDMA_ERR_CRPB_PAR |
  275. EDMA_ERR_INTRL_PAR |
  276. EDMA_ERR_IORDY,
  277. EDMA_REQ_Q_BASE_HI_OFS = 0x10,
  278. EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
  279. EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
  280. EDMA_REQ_Q_PTR_SHIFT = 5,
  281. EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
  282. EDMA_RSP_Q_IN_PTR_OFS = 0x20,
  283. EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
  284. EDMA_RSP_Q_PTR_SHIFT = 3,
  285. EDMA_CMD_OFS = 0x28, /* EDMA command register */
  286. EDMA_EN = (1 << 0), /* enable EDMA */
  287. EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
  288. ATA_RST = (1 << 2), /* reset trans/link/phy */
  289. EDMA_IORDY_TMOUT = 0x34,
  290. EDMA_ARB_CFG = 0x38,
  291. /* Host private flags (hp_flags) */
  292. MV_HP_FLAG_MSI = (1 << 0),
  293. MV_HP_ERRATA_50XXB0 = (1 << 1),
  294. MV_HP_ERRATA_50XXB2 = (1 << 2),
  295. MV_HP_ERRATA_60X1B2 = (1 << 3),
  296. MV_HP_ERRATA_60X1C0 = (1 << 4),
  297. MV_HP_ERRATA_XX42A0 = (1 << 5),
  298. MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
  299. MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
  300. MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
  301. MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
  302. /* Port private flags (pp_flags) */
  303. MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
  304. MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
  305. };
  306. #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
  307. #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
  308. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  309. #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
  310. #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
  311. #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
  312. enum {
  313. /* DMA boundary 0xffff is required by the s/g splitting
  314. * we need on /length/ in mv_fill-sg().
  315. */
  316. MV_DMA_BOUNDARY = 0xffffU,
  317. /* mask of register bits containing lower 32 bits
  318. * of EDMA request queue DMA address
  319. */
  320. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  321. /* ditto, for response queue */
  322. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  323. };
  324. enum chip_type {
  325. chip_504x,
  326. chip_508x,
  327. chip_5080,
  328. chip_604x,
  329. chip_608x,
  330. chip_6042,
  331. chip_7042,
  332. chip_soc,
  333. };
  334. /* Command ReQuest Block: 32B */
  335. struct mv_crqb {
  336. __le32 sg_addr;
  337. __le32 sg_addr_hi;
  338. __le16 ctrl_flags;
  339. __le16 ata_cmd[11];
  340. };
  341. struct mv_crqb_iie {
  342. __le32 addr;
  343. __le32 addr_hi;
  344. __le32 flags;
  345. __le32 len;
  346. __le32 ata_cmd[4];
  347. };
  348. /* Command ResPonse Block: 8B */
  349. struct mv_crpb {
  350. __le16 id;
  351. __le16 flags;
  352. __le32 tmstmp;
  353. };
  354. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  355. struct mv_sg {
  356. __le32 addr;
  357. __le32 flags_size;
  358. __le32 addr_hi;
  359. __le32 reserved;
  360. };
  361. struct mv_port_priv {
  362. struct mv_crqb *crqb;
  363. dma_addr_t crqb_dma;
  364. struct mv_crpb *crpb;
  365. dma_addr_t crpb_dma;
  366. struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
  367. dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
  368. unsigned int req_idx;
  369. unsigned int resp_idx;
  370. u32 pp_flags;
  371. };
  372. struct mv_port_signal {
  373. u32 amps;
  374. u32 pre;
  375. };
  376. struct mv_host_priv {
  377. u32 hp_flags;
  378. struct mv_port_signal signal[8];
  379. const struct mv_hw_ops *ops;
  380. int n_ports;
  381. void __iomem *base;
  382. void __iomem *main_cause_reg_addr;
  383. void __iomem *main_mask_reg_addr;
  384. u32 irq_cause_ofs;
  385. u32 irq_mask_ofs;
  386. u32 unmask_all_irqs;
  387. /*
  388. * These consistent DMA memory pools give us guaranteed
  389. * alignment for hardware-accessed data structures,
  390. * and less memory waste in accomplishing the alignment.
  391. */
  392. struct dma_pool *crqb_pool;
  393. struct dma_pool *crpb_pool;
  394. struct dma_pool *sg_tbl_pool;
  395. };
  396. struct mv_hw_ops {
  397. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  398. unsigned int port);
  399. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  400. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  401. void __iomem *mmio);
  402. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  403. unsigned int n_hc);
  404. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  405. void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
  406. };
  407. static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
  408. static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
  409. static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
  410. static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
  411. static int mv_port_start(struct ata_port *ap);
  412. static void mv_port_stop(struct ata_port *ap);
  413. static void mv_qc_prep(struct ata_queued_cmd *qc);
  414. static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
  415. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  416. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  417. unsigned long deadline);
  418. static void mv_eh_freeze(struct ata_port *ap);
  419. static void mv_eh_thaw(struct ata_port *ap);
  420. static void mv6_dev_config(struct ata_device *dev);
  421. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  422. unsigned int port);
  423. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  424. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  425. void __iomem *mmio);
  426. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  427. unsigned int n_hc);
  428. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  429. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
  430. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  431. unsigned int port);
  432. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  433. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  434. void __iomem *mmio);
  435. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  436. unsigned int n_hc);
  437. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  438. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  439. void __iomem *mmio);
  440. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  441. void __iomem *mmio);
  442. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  443. void __iomem *mmio, unsigned int n_hc);
  444. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  445. void __iomem *mmio);
  446. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
  447. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
  448. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  449. unsigned int port_no);
  450. static int mv_stop_edma(struct ata_port *ap);
  451. static int mv_stop_edma_engine(void __iomem *port_mmio);
  452. static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
  453. static void mv_pmp_select(struct ata_port *ap, int pmp);
  454. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  455. unsigned long deadline);
  456. static int mv_softreset(struct ata_link *link, unsigned int *class,
  457. unsigned long deadline);
  458. /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
  459. * because we have to allow room for worst case splitting of
  460. * PRDs for 64K boundaries in mv_fill_sg().
  461. */
  462. static struct scsi_host_template mv5_sht = {
  463. ATA_BASE_SHT(DRV_NAME),
  464. .sg_tablesize = MV_MAX_SG_CT / 2,
  465. .dma_boundary = MV_DMA_BOUNDARY,
  466. };
  467. static struct scsi_host_template mv6_sht = {
  468. ATA_NCQ_SHT(DRV_NAME),
  469. .can_queue = MV_MAX_Q_DEPTH - 1,
  470. .sg_tablesize = MV_MAX_SG_CT / 2,
  471. .dma_boundary = MV_DMA_BOUNDARY,
  472. };
  473. static struct ata_port_operations mv5_ops = {
  474. .inherits = &ata_sff_port_ops,
  475. .qc_prep = mv_qc_prep,
  476. .qc_issue = mv_qc_issue,
  477. .freeze = mv_eh_freeze,
  478. .thaw = mv_eh_thaw,
  479. .hardreset = mv_hardreset,
  480. .error_handler = ata_std_error_handler, /* avoid SFF EH */
  481. .post_internal_cmd = ATA_OP_NULL,
  482. .scr_read = mv5_scr_read,
  483. .scr_write = mv5_scr_write,
  484. .port_start = mv_port_start,
  485. .port_stop = mv_port_stop,
  486. };
  487. static struct ata_port_operations mv6_ops = {
  488. .inherits = &mv5_ops,
  489. .qc_defer = sata_pmp_qc_defer_cmd_switch,
  490. .dev_config = mv6_dev_config,
  491. .scr_read = mv_scr_read,
  492. .scr_write = mv_scr_write,
  493. .pmp_hardreset = mv_pmp_hardreset,
  494. .pmp_softreset = mv_softreset,
  495. .softreset = mv_softreset,
  496. .error_handler = sata_pmp_error_handler,
  497. };
  498. static struct ata_port_operations mv_iie_ops = {
  499. .inherits = &mv6_ops,
  500. .qc_defer = ata_std_qc_defer, /* FIS-based switching */
  501. .dev_config = ATA_OP_NULL,
  502. .qc_prep = mv_qc_prep_iie,
  503. };
  504. static const struct ata_port_info mv_port_info[] = {
  505. { /* chip_504x */
  506. .flags = MV_COMMON_FLAGS,
  507. .pio_mask = 0x1f, /* pio0-4 */
  508. .udma_mask = ATA_UDMA6,
  509. .port_ops = &mv5_ops,
  510. },
  511. { /* chip_508x */
  512. .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
  513. .pio_mask = 0x1f, /* pio0-4 */
  514. .udma_mask = ATA_UDMA6,
  515. .port_ops = &mv5_ops,
  516. },
  517. { /* chip_5080 */
  518. .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
  519. .pio_mask = 0x1f, /* pio0-4 */
  520. .udma_mask = ATA_UDMA6,
  521. .port_ops = &mv5_ops,
  522. },
  523. { /* chip_604x */
  524. .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  525. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
  526. ATA_FLAG_NCQ,
  527. .pio_mask = 0x1f, /* pio0-4 */
  528. .udma_mask = ATA_UDMA6,
  529. .port_ops = &mv6_ops,
  530. },
  531. { /* chip_608x */
  532. .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  533. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
  534. ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
  535. .pio_mask = 0x1f, /* pio0-4 */
  536. .udma_mask = ATA_UDMA6,
  537. .port_ops = &mv6_ops,
  538. },
  539. { /* chip_6042 */
  540. .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  541. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
  542. ATA_FLAG_NCQ,
  543. .pio_mask = 0x1f, /* pio0-4 */
  544. .udma_mask = ATA_UDMA6,
  545. .port_ops = &mv_iie_ops,
  546. },
  547. { /* chip_7042 */
  548. .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  549. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
  550. ATA_FLAG_NCQ,
  551. .pio_mask = 0x1f, /* pio0-4 */
  552. .udma_mask = ATA_UDMA6,
  553. .port_ops = &mv_iie_ops,
  554. },
  555. { /* chip_soc */
  556. .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  557. ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
  558. ATA_FLAG_NCQ | MV_FLAG_SOC,
  559. .pio_mask = 0x1f, /* pio0-4 */
  560. .udma_mask = ATA_UDMA6,
  561. .port_ops = &mv_iie_ops,
  562. },
  563. };
  564. static const struct pci_device_id mv_pci_tbl[] = {
  565. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  566. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  567. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  568. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  569. /* RocketRAID 1740/174x have different identifiers */
  570. { PCI_VDEVICE(TTI, 0x1740), chip_508x },
  571. { PCI_VDEVICE(TTI, 0x1742), chip_508x },
  572. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  573. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  574. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  575. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  576. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  577. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  578. /* Adaptec 1430SA */
  579. { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
  580. /* Marvell 7042 support */
  581. { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
  582. /* Highpoint RocketRAID PCIe series */
  583. { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
  584. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  585. { } /* terminate list */
  586. };
  587. static const struct mv_hw_ops mv5xxx_ops = {
  588. .phy_errata = mv5_phy_errata,
  589. .enable_leds = mv5_enable_leds,
  590. .read_preamp = mv5_read_preamp,
  591. .reset_hc = mv5_reset_hc,
  592. .reset_flash = mv5_reset_flash,
  593. .reset_bus = mv5_reset_bus,
  594. };
  595. static const struct mv_hw_ops mv6xxx_ops = {
  596. .phy_errata = mv6_phy_errata,
  597. .enable_leds = mv6_enable_leds,
  598. .read_preamp = mv6_read_preamp,
  599. .reset_hc = mv6_reset_hc,
  600. .reset_flash = mv6_reset_flash,
  601. .reset_bus = mv_reset_pci_bus,
  602. };
  603. static const struct mv_hw_ops mv_soc_ops = {
  604. .phy_errata = mv6_phy_errata,
  605. .enable_leds = mv_soc_enable_leds,
  606. .read_preamp = mv_soc_read_preamp,
  607. .reset_hc = mv_soc_reset_hc,
  608. .reset_flash = mv_soc_reset_flash,
  609. .reset_bus = mv_soc_reset_bus,
  610. };
  611. /*
  612. * Functions
  613. */
  614. static inline void writelfl(unsigned long data, void __iomem *addr)
  615. {
  616. writel(data, addr);
  617. (void) readl(addr); /* flush to avoid PCI posted write */
  618. }
  619. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  620. {
  621. return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  622. }
  623. static inline unsigned int mv_hc_from_port(unsigned int port)
  624. {
  625. return port >> MV_PORT_HC_SHIFT;
  626. }
  627. static inline unsigned int mv_hardport_from_port(unsigned int port)
  628. {
  629. return port & MV_PORT_MASK;
  630. }
  631. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  632. unsigned int port)
  633. {
  634. return mv_hc_base(base, mv_hc_from_port(port));
  635. }
  636. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  637. {
  638. return mv_hc_base_from_port(base, port) +
  639. MV_SATAHC_ARBTR_REG_SZ +
  640. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  641. }
  642. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  643. {
  644. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  645. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  646. return hc_mmio + ofs;
  647. }
  648. static inline void __iomem *mv_host_base(struct ata_host *host)
  649. {
  650. struct mv_host_priv *hpriv = host->private_data;
  651. return hpriv->base;
  652. }
  653. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  654. {
  655. return mv_port_base(mv_host_base(ap->host), ap->port_no);
  656. }
  657. static inline int mv_get_hc_count(unsigned long port_flags)
  658. {
  659. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  660. }
  661. static void mv_set_edma_ptrs(void __iomem *port_mmio,
  662. struct mv_host_priv *hpriv,
  663. struct mv_port_priv *pp)
  664. {
  665. u32 index;
  666. /*
  667. * initialize request queue
  668. */
  669. index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
  670. WARN_ON(pp->crqb_dma & 0x3ff);
  671. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
  672. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
  673. port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
  674. if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
  675. writelfl((pp->crqb_dma & 0xffffffff) | index,
  676. port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
  677. else
  678. writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
  679. /*
  680. * initialize response queue
  681. */
  682. index = (pp->resp_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_RSP_Q_PTR_SHIFT;
  683. WARN_ON(pp->crpb_dma & 0xff);
  684. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
  685. if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
  686. writelfl((pp->crpb_dma & 0xffffffff) | index,
  687. port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
  688. else
  689. writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
  690. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
  691. port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
  692. }
  693. /**
  694. * mv_start_dma - Enable eDMA engine
  695. * @base: port base address
  696. * @pp: port private data
  697. *
  698. * Verify the local cache of the eDMA state is accurate with a
  699. * WARN_ON.
  700. *
  701. * LOCKING:
  702. * Inherited from caller.
  703. */
  704. static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
  705. struct mv_port_priv *pp, u8 protocol)
  706. {
  707. int want_ncq = (protocol == ATA_PROT_NCQ);
  708. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  709. int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
  710. if (want_ncq != using_ncq)
  711. mv_stop_edma(ap);
  712. }
  713. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
  714. struct mv_host_priv *hpriv = ap->host->private_data;
  715. int hard_port = mv_hardport_from_port(ap->port_no);
  716. void __iomem *hc_mmio = mv_hc_base_from_port(
  717. mv_host_base(ap->host), hard_port);
  718. u32 hc_irq_cause, ipending;
  719. /* clear EDMA event indicators, if any */
  720. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  721. /* clear EDMA interrupt indicator, if any */
  722. hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
  723. ipending = (DEV_IRQ << hard_port) |
  724. (CRPB_DMA_DONE << hard_port);
  725. if (hc_irq_cause & ipending) {
  726. writelfl(hc_irq_cause & ~ipending,
  727. hc_mmio + HC_IRQ_CAUSE_OFS);
  728. }
  729. mv_edma_cfg(ap, want_ncq);
  730. /* clear FIS IRQ Cause */
  731. writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
  732. mv_set_edma_ptrs(port_mmio, hpriv, pp);
  733. writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
  734. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  735. }
  736. WARN_ON(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
  737. }
  738. /**
  739. * mv_stop_edma_engine - Disable eDMA engine
  740. * @port_mmio: io base address
  741. *
  742. * LOCKING:
  743. * Inherited from caller.
  744. */
  745. static int mv_stop_edma_engine(void __iomem *port_mmio)
  746. {
  747. int i;
  748. /* Disable eDMA. The disable bit auto clears. */
  749. writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
  750. /* Wait for the chip to confirm eDMA is off. */
  751. for (i = 10000; i > 0; i--) {
  752. u32 reg = readl(port_mmio + EDMA_CMD_OFS);
  753. if (!(reg & EDMA_EN))
  754. return 0;
  755. udelay(10);
  756. }
  757. return -EIO;
  758. }
  759. static int mv_stop_edma(struct ata_port *ap)
  760. {
  761. void __iomem *port_mmio = mv_ap_base(ap);
  762. struct mv_port_priv *pp = ap->private_data;
  763. if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
  764. return 0;
  765. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  766. if (mv_stop_edma_engine(port_mmio)) {
  767. ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
  768. return -EIO;
  769. }
  770. return 0;
  771. }
  772. #ifdef ATA_DEBUG
  773. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  774. {
  775. int b, w;
  776. for (b = 0; b < bytes; ) {
  777. DPRINTK("%p: ", start + b);
  778. for (w = 0; b < bytes && w < 4; w++) {
  779. printk("%08x ", readl(start + b));
  780. b += sizeof(u32);
  781. }
  782. printk("\n");
  783. }
  784. }
  785. #endif
  786. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  787. {
  788. #ifdef ATA_DEBUG
  789. int b, w;
  790. u32 dw;
  791. for (b = 0; b < bytes; ) {
  792. DPRINTK("%02x: ", b);
  793. for (w = 0; b < bytes && w < 4; w++) {
  794. (void) pci_read_config_dword(pdev, b, &dw);
  795. printk("%08x ", dw);
  796. b += sizeof(u32);
  797. }
  798. printk("\n");
  799. }
  800. #endif
  801. }
  802. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  803. struct pci_dev *pdev)
  804. {
  805. #ifdef ATA_DEBUG
  806. void __iomem *hc_base = mv_hc_base(mmio_base,
  807. port >> MV_PORT_HC_SHIFT);
  808. void __iomem *port_base;
  809. int start_port, num_ports, p, start_hc, num_hcs, hc;
  810. if (0 > port) {
  811. start_hc = start_port = 0;
  812. num_ports = 8; /* shld be benign for 4 port devs */
  813. num_hcs = 2;
  814. } else {
  815. start_hc = port >> MV_PORT_HC_SHIFT;
  816. start_port = port;
  817. num_ports = num_hcs = 1;
  818. }
  819. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  820. num_ports > 1 ? num_ports - 1 : start_port);
  821. if (NULL != pdev) {
  822. DPRINTK("PCI config space regs:\n");
  823. mv_dump_pci_cfg(pdev, 0x68);
  824. }
  825. DPRINTK("PCI regs:\n");
  826. mv_dump_mem(mmio_base+0xc00, 0x3c);
  827. mv_dump_mem(mmio_base+0xd00, 0x34);
  828. mv_dump_mem(mmio_base+0xf00, 0x4);
  829. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  830. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  831. hc_base = mv_hc_base(mmio_base, hc);
  832. DPRINTK("HC regs (HC %i):\n", hc);
  833. mv_dump_mem(hc_base, 0x1c);
  834. }
  835. for (p = start_port; p < start_port + num_ports; p++) {
  836. port_base = mv_port_base(mmio_base, p);
  837. DPRINTK("EDMA regs (port %i):\n", p);
  838. mv_dump_mem(port_base, 0x54);
  839. DPRINTK("SATA regs (port %i):\n", p);
  840. mv_dump_mem(port_base+0x300, 0x60);
  841. }
  842. #endif
  843. }
  844. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  845. {
  846. unsigned int ofs;
  847. switch (sc_reg_in) {
  848. case SCR_STATUS:
  849. case SCR_CONTROL:
  850. case SCR_ERROR:
  851. ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
  852. break;
  853. case SCR_ACTIVE:
  854. ofs = SATA_ACTIVE_OFS; /* active is not with the others */
  855. break;
  856. default:
  857. ofs = 0xffffffffU;
  858. break;
  859. }
  860. return ofs;
  861. }
  862. static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
  863. {
  864. unsigned int ofs = mv_scr_offset(sc_reg_in);
  865. if (ofs != 0xffffffffU) {
  866. *val = readl(mv_ap_base(ap) + ofs);
  867. return 0;
  868. } else
  869. return -EINVAL;
  870. }
  871. static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
  872. {
  873. unsigned int ofs = mv_scr_offset(sc_reg_in);
  874. if (ofs != 0xffffffffU) {
  875. writelfl(val, mv_ap_base(ap) + ofs);
  876. return 0;
  877. } else
  878. return -EINVAL;
  879. }
  880. static void mv6_dev_config(struct ata_device *adev)
  881. {
  882. /*
  883. * Deal with Gen-II ("mv6") hardware quirks/restrictions:
  884. *
  885. * Gen-II does not support NCQ over a port multiplier
  886. * (no FIS-based switching).
  887. *
  888. * We don't have hob_nsect when doing NCQ commands on Gen-II.
  889. * See mv_qc_prep() for more info.
  890. */
  891. if (adev->flags & ATA_DFLAG_NCQ) {
  892. if (sata_pmp_attached(adev->link->ap))
  893. adev->flags &= ~ATA_DFLAG_NCQ;
  894. else if (adev->max_sectors > ATA_MAX_SECTORS)
  895. adev->max_sectors = ATA_MAX_SECTORS;
  896. }
  897. }
  898. static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
  899. {
  900. u32 old_fcfg, new_fcfg, old_ltmode, new_ltmode;
  901. /*
  902. * Various bit settings required for operation
  903. * in FIS-based switching (fbs) mode on GenIIe:
  904. */
  905. old_fcfg = readl(port_mmio + FIS_CFG_OFS);
  906. old_ltmode = readl(port_mmio + LTMODE_OFS);
  907. if (enable_fbs) {
  908. new_fcfg = old_fcfg | FIS_CFG_SINGLE_SYNC;
  909. new_ltmode = old_ltmode | LTMODE_BIT8;
  910. } else { /* disable fbs */
  911. new_fcfg = old_fcfg & ~FIS_CFG_SINGLE_SYNC;
  912. new_ltmode = old_ltmode & ~LTMODE_BIT8;
  913. }
  914. if (new_fcfg != old_fcfg)
  915. writelfl(new_fcfg, port_mmio + FIS_CFG_OFS);
  916. if (new_ltmode != old_ltmode)
  917. writelfl(new_ltmode, port_mmio + LTMODE_OFS);
  918. }
  919. static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
  920. {
  921. u32 cfg;
  922. struct mv_port_priv *pp = ap->private_data;
  923. struct mv_host_priv *hpriv = ap->host->private_data;
  924. void __iomem *port_mmio = mv_ap_base(ap);
  925. /* set up non-NCQ EDMA configuration */
  926. cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
  927. if (IS_GEN_I(hpriv))
  928. cfg |= (1 << 8); /* enab config burst size mask */
  929. else if (IS_GEN_II(hpriv))
  930. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  931. else if (IS_GEN_IIE(hpriv)) {
  932. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  933. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  934. cfg |= (1 << 18); /* enab early completion */
  935. cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
  936. if (want_ncq && sata_pmp_attached(ap)) {
  937. cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
  938. mv_config_fbs(port_mmio, 1);
  939. } else {
  940. mv_config_fbs(port_mmio, 0);
  941. }
  942. }
  943. if (want_ncq) {
  944. cfg |= EDMA_CFG_NCQ;
  945. pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
  946. } else
  947. pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
  948. writelfl(cfg, port_mmio + EDMA_CFG_OFS);
  949. }
  950. static void mv_port_free_dma_mem(struct ata_port *ap)
  951. {
  952. struct mv_host_priv *hpriv = ap->host->private_data;
  953. struct mv_port_priv *pp = ap->private_data;
  954. int tag;
  955. if (pp->crqb) {
  956. dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
  957. pp->crqb = NULL;
  958. }
  959. if (pp->crpb) {
  960. dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
  961. pp->crpb = NULL;
  962. }
  963. /*
  964. * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
  965. * For later hardware, we have one unique sg_tbl per NCQ tag.
  966. */
  967. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  968. if (pp->sg_tbl[tag]) {
  969. if (tag == 0 || !IS_GEN_I(hpriv))
  970. dma_pool_free(hpriv->sg_tbl_pool,
  971. pp->sg_tbl[tag],
  972. pp->sg_tbl_dma[tag]);
  973. pp->sg_tbl[tag] = NULL;
  974. }
  975. }
  976. }
  977. /**
  978. * mv_port_start - Port specific init/start routine.
  979. * @ap: ATA channel to manipulate
  980. *
  981. * Allocate and point to DMA memory, init port private memory,
  982. * zero indices.
  983. *
  984. * LOCKING:
  985. * Inherited from caller.
  986. */
  987. static int mv_port_start(struct ata_port *ap)
  988. {
  989. struct device *dev = ap->host->dev;
  990. struct mv_host_priv *hpriv = ap->host->private_data;
  991. struct mv_port_priv *pp;
  992. int tag;
  993. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  994. if (!pp)
  995. return -ENOMEM;
  996. ap->private_data = pp;
  997. pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
  998. if (!pp->crqb)
  999. return -ENOMEM;
  1000. memset(pp->crqb, 0, MV_CRQB_Q_SZ);
  1001. pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
  1002. if (!pp->crpb)
  1003. goto out_port_free_dma_mem;
  1004. memset(pp->crpb, 0, MV_CRPB_Q_SZ);
  1005. /*
  1006. * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
  1007. * For later hardware, we need one unique sg_tbl per NCQ tag.
  1008. */
  1009. for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
  1010. if (tag == 0 || !IS_GEN_I(hpriv)) {
  1011. pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
  1012. GFP_KERNEL, &pp->sg_tbl_dma[tag]);
  1013. if (!pp->sg_tbl[tag])
  1014. goto out_port_free_dma_mem;
  1015. } else {
  1016. pp->sg_tbl[tag] = pp->sg_tbl[0];
  1017. pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
  1018. }
  1019. }
  1020. return 0;
  1021. out_port_free_dma_mem:
  1022. mv_port_free_dma_mem(ap);
  1023. return -ENOMEM;
  1024. }
  1025. /**
  1026. * mv_port_stop - Port specific cleanup/stop routine.
  1027. * @ap: ATA channel to manipulate
  1028. *
  1029. * Stop DMA, cleanup port memory.
  1030. *
  1031. * LOCKING:
  1032. * This routine uses the host lock to protect the DMA stop.
  1033. */
  1034. static void mv_port_stop(struct ata_port *ap)
  1035. {
  1036. mv_stop_edma(ap);
  1037. mv_port_free_dma_mem(ap);
  1038. }
  1039. /**
  1040. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  1041. * @qc: queued command whose SG list to source from
  1042. *
  1043. * Populate the SG list and mark the last entry.
  1044. *
  1045. * LOCKING:
  1046. * Inherited from caller.
  1047. */
  1048. static void mv_fill_sg(struct ata_queued_cmd *qc)
  1049. {
  1050. struct mv_port_priv *pp = qc->ap->private_data;
  1051. struct scatterlist *sg;
  1052. struct mv_sg *mv_sg, *last_sg = NULL;
  1053. unsigned int si;
  1054. mv_sg = pp->sg_tbl[qc->tag];
  1055. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1056. dma_addr_t addr = sg_dma_address(sg);
  1057. u32 sg_len = sg_dma_len(sg);
  1058. while (sg_len) {
  1059. u32 offset = addr & 0xffff;
  1060. u32 len = sg_len;
  1061. if ((offset + sg_len > 0x10000))
  1062. len = 0x10000 - offset;
  1063. mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
  1064. mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1065. mv_sg->flags_size = cpu_to_le32(len & 0xffff);
  1066. sg_len -= len;
  1067. addr += len;
  1068. last_sg = mv_sg;
  1069. mv_sg++;
  1070. }
  1071. }
  1072. if (likely(last_sg))
  1073. last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  1074. }
  1075. static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  1076. {
  1077. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  1078. (last ? CRQB_CMD_LAST : 0);
  1079. *cmdw = cpu_to_le16(tmp);
  1080. }
  1081. /**
  1082. * mv_qc_prep - Host specific command preparation.
  1083. * @qc: queued command to prepare
  1084. *
  1085. * This routine simply redirects to the general purpose routine
  1086. * if command is not DMA. Else, it handles prep of the CRQB
  1087. * (command request block), does some sanity checking, and calls
  1088. * the SG load routine.
  1089. *
  1090. * LOCKING:
  1091. * Inherited from caller.
  1092. */
  1093. static void mv_qc_prep(struct ata_queued_cmd *qc)
  1094. {
  1095. struct ata_port *ap = qc->ap;
  1096. struct mv_port_priv *pp = ap->private_data;
  1097. __le16 *cw;
  1098. struct ata_taskfile *tf;
  1099. u16 flags = 0;
  1100. unsigned in_index;
  1101. if ((qc->tf.protocol != ATA_PROT_DMA) &&
  1102. (qc->tf.protocol != ATA_PROT_NCQ))
  1103. return;
  1104. /* Fill in command request block
  1105. */
  1106. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  1107. flags |= CRQB_FLAG_READ;
  1108. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1109. flags |= qc->tag << CRQB_TAG_SHIFT;
  1110. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1111. /* get current queue index from software */
  1112. in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
  1113. pp->crqb[in_index].sg_addr =
  1114. cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1115. pp->crqb[in_index].sg_addr_hi =
  1116. cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1117. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  1118. cw = &pp->crqb[in_index].ata_cmd[0];
  1119. tf = &qc->tf;
  1120. /* Sadly, the CRQB cannot accomodate all registers--there are
  1121. * only 11 bytes...so we must pick and choose required
  1122. * registers based on the command. So, we drop feature and
  1123. * hob_feature for [RW] DMA commands, but they are needed for
  1124. * NCQ. NCQ will drop hob_nsect.
  1125. */
  1126. switch (tf->command) {
  1127. case ATA_CMD_READ:
  1128. case ATA_CMD_READ_EXT:
  1129. case ATA_CMD_WRITE:
  1130. case ATA_CMD_WRITE_EXT:
  1131. case ATA_CMD_WRITE_FUA_EXT:
  1132. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  1133. break;
  1134. case ATA_CMD_FPDMA_READ:
  1135. case ATA_CMD_FPDMA_WRITE:
  1136. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  1137. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  1138. break;
  1139. default:
  1140. /* The only other commands EDMA supports in non-queued and
  1141. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  1142. * of which are defined/used by Linux. If we get here, this
  1143. * driver needs work.
  1144. *
  1145. * FIXME: modify libata to give qc_prep a return value and
  1146. * return error here.
  1147. */
  1148. BUG_ON(tf->command);
  1149. break;
  1150. }
  1151. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  1152. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  1153. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  1154. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  1155. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  1156. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  1157. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  1158. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  1159. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  1160. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1161. return;
  1162. mv_fill_sg(qc);
  1163. }
  1164. /**
  1165. * mv_qc_prep_iie - Host specific command preparation.
  1166. * @qc: queued command to prepare
  1167. *
  1168. * This routine simply redirects to the general purpose routine
  1169. * if command is not DMA. Else, it handles prep of the CRQB
  1170. * (command request block), does some sanity checking, and calls
  1171. * the SG load routine.
  1172. *
  1173. * LOCKING:
  1174. * Inherited from caller.
  1175. */
  1176. static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
  1177. {
  1178. struct ata_port *ap = qc->ap;
  1179. struct mv_port_priv *pp = ap->private_data;
  1180. struct mv_crqb_iie *crqb;
  1181. struct ata_taskfile *tf;
  1182. unsigned in_index;
  1183. u32 flags = 0;
  1184. if ((qc->tf.protocol != ATA_PROT_DMA) &&
  1185. (qc->tf.protocol != ATA_PROT_NCQ))
  1186. return;
  1187. /* Fill in Gen IIE command request block */
  1188. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  1189. flags |= CRQB_FLAG_READ;
  1190. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  1191. flags |= qc->tag << CRQB_TAG_SHIFT;
  1192. flags |= qc->tag << CRQB_HOSTQ_SHIFT;
  1193. flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
  1194. /* get current queue index from software */
  1195. in_index = pp->req_idx & MV_MAX_Q_DEPTH_MASK;
  1196. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  1197. crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
  1198. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
  1199. crqb->flags = cpu_to_le32(flags);
  1200. tf = &qc->tf;
  1201. crqb->ata_cmd[0] = cpu_to_le32(
  1202. (tf->command << 16) |
  1203. (tf->feature << 24)
  1204. );
  1205. crqb->ata_cmd[1] = cpu_to_le32(
  1206. (tf->lbal << 0) |
  1207. (tf->lbam << 8) |
  1208. (tf->lbah << 16) |
  1209. (tf->device << 24)
  1210. );
  1211. crqb->ata_cmd[2] = cpu_to_le32(
  1212. (tf->hob_lbal << 0) |
  1213. (tf->hob_lbam << 8) |
  1214. (tf->hob_lbah << 16) |
  1215. (tf->hob_feature << 24)
  1216. );
  1217. crqb->ata_cmd[3] = cpu_to_le32(
  1218. (tf->nsect << 0) |
  1219. (tf->hob_nsect << 8)
  1220. );
  1221. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1222. return;
  1223. mv_fill_sg(qc);
  1224. }
  1225. /**
  1226. * mv_qc_issue - Initiate a command to the host
  1227. * @qc: queued command to start
  1228. *
  1229. * This routine simply redirects to the general purpose routine
  1230. * if command is not DMA. Else, it sanity checks our local
  1231. * caches of the request producer/consumer indices then enables
  1232. * DMA and bumps the request producer index.
  1233. *
  1234. * LOCKING:
  1235. * Inherited from caller.
  1236. */
  1237. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  1238. {
  1239. struct ata_port *ap = qc->ap;
  1240. void __iomem *port_mmio = mv_ap_base(ap);
  1241. struct mv_port_priv *pp = ap->private_data;
  1242. u32 in_index;
  1243. if ((qc->tf.protocol != ATA_PROT_DMA) &&
  1244. (qc->tf.protocol != ATA_PROT_NCQ)) {
  1245. /*
  1246. * We're about to send a non-EDMA capable command to the
  1247. * port. Turn off EDMA so there won't be problems accessing
  1248. * shadow block, etc registers.
  1249. */
  1250. mv_stop_edma(ap);
  1251. mv_pmp_select(ap, qc->dev->link->pmp);
  1252. return ata_sff_qc_issue(qc);
  1253. }
  1254. mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
  1255. pp->req_idx++;
  1256. in_index = (pp->req_idx & MV_MAX_Q_DEPTH_MASK) << EDMA_REQ_Q_PTR_SHIFT;
  1257. /* and write the request in pointer to kick the EDMA to life */
  1258. writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
  1259. port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
  1260. return 0;
  1261. }
  1262. /**
  1263. * mv_err_intr - Handle error interrupts on the port
  1264. * @ap: ATA channel to manipulate
  1265. * @reset_allowed: bool: 0 == don't trigger from reset here
  1266. *
  1267. * In most cases, just clear the interrupt and move on. However,
  1268. * some cases require an eDMA reset, which also performs a COMRESET.
  1269. * The SERR case requires a clear of pending errors in the SATA
  1270. * SERROR register. Finally, if the port disabled DMA,
  1271. * update our cached copy to match.
  1272. *
  1273. * LOCKING:
  1274. * Inherited from caller.
  1275. */
  1276. static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
  1277. {
  1278. void __iomem *port_mmio = mv_ap_base(ap);
  1279. u32 edma_err_cause, eh_freeze_mask, serr = 0;
  1280. struct mv_port_priv *pp = ap->private_data;
  1281. struct mv_host_priv *hpriv = ap->host->private_data;
  1282. unsigned int edma_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
  1283. unsigned int action = 0, err_mask = 0;
  1284. struct ata_eh_info *ehi = &ap->link.eh_info;
  1285. ata_ehi_clear_desc(ehi);
  1286. if (!edma_enabled) {
  1287. /* just a guess: do we need to do this? should we
  1288. * expand this, and do it in all cases?
  1289. */
  1290. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  1291. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  1292. }
  1293. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1294. ata_ehi_push_desc(ehi, "edma_err 0x%08x", edma_err_cause);
  1295. /*
  1296. * all generations share these EDMA error cause bits
  1297. */
  1298. if (edma_err_cause & EDMA_ERR_DEV)
  1299. err_mask |= AC_ERR_DEV;
  1300. if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  1301. EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
  1302. EDMA_ERR_INTRL_PAR)) {
  1303. err_mask |= AC_ERR_ATA_BUS;
  1304. action |= ATA_EH_RESET;
  1305. ata_ehi_push_desc(ehi, "parity error");
  1306. }
  1307. if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
  1308. ata_ehi_hotplugged(ehi);
  1309. ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
  1310. "dev disconnect" : "dev connect");
  1311. action |= ATA_EH_RESET;
  1312. }
  1313. if (IS_GEN_I(hpriv)) {
  1314. eh_freeze_mask = EDMA_EH_FREEZE_5;
  1315. if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
  1316. pp = ap->private_data;
  1317. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1318. ata_ehi_push_desc(ehi, "EDMA self-disable");
  1319. }
  1320. } else {
  1321. eh_freeze_mask = EDMA_EH_FREEZE;
  1322. if (edma_err_cause & EDMA_ERR_SELF_DIS) {
  1323. pp = ap->private_data;
  1324. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1325. ata_ehi_push_desc(ehi, "EDMA self-disable");
  1326. }
  1327. if (edma_err_cause & EDMA_ERR_SERR) {
  1328. sata_scr_read(&ap->link, SCR_ERROR, &serr);
  1329. sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
  1330. err_mask = AC_ERR_ATA_BUS;
  1331. action |= ATA_EH_RESET;
  1332. }
  1333. }
  1334. /* Clear EDMA now that SERR cleanup done */
  1335. writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1336. if (!err_mask) {
  1337. err_mask = AC_ERR_OTHER;
  1338. action |= ATA_EH_RESET;
  1339. }
  1340. ehi->serror |= serr;
  1341. ehi->action |= action;
  1342. if (qc)
  1343. qc->err_mask |= err_mask;
  1344. else
  1345. ehi->err_mask |= err_mask;
  1346. if (edma_err_cause & eh_freeze_mask)
  1347. ata_port_freeze(ap);
  1348. else
  1349. ata_port_abort(ap);
  1350. }
  1351. static void mv_intr_pio(struct ata_port *ap)
  1352. {
  1353. struct ata_queued_cmd *qc;
  1354. u8 ata_status;
  1355. /* ignore spurious intr if drive still BUSY */
  1356. ata_status = readb(ap->ioaddr.status_addr);
  1357. if (unlikely(ata_status & ATA_BUSY))
  1358. return;
  1359. /* get active ATA command */
  1360. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1361. if (unlikely(!qc)) /* no active tag */
  1362. return;
  1363. if (qc->tf.flags & ATA_TFLAG_POLLING) /* polling; we don't own qc */
  1364. return;
  1365. /* and finally, complete the ATA command */
  1366. qc->err_mask |= ac_err_mask(ata_status);
  1367. ata_qc_complete(qc);
  1368. }
  1369. static void mv_intr_edma(struct ata_port *ap)
  1370. {
  1371. void __iomem *port_mmio = mv_ap_base(ap);
  1372. struct mv_host_priv *hpriv = ap->host->private_data;
  1373. struct mv_port_priv *pp = ap->private_data;
  1374. struct ata_queued_cmd *qc;
  1375. u32 out_index, in_index;
  1376. bool work_done = false;
  1377. /* get h/w response queue pointer */
  1378. in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
  1379. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  1380. while (1) {
  1381. u16 status;
  1382. unsigned int tag;
  1383. /* get s/w response queue last-read pointer, and compare */
  1384. out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK;
  1385. if (in_index == out_index)
  1386. break;
  1387. /* 50xx: get active ATA command */
  1388. if (IS_GEN_I(hpriv))
  1389. tag = ap->link.active_tag;
  1390. /* Gen II/IIE: get active ATA command via tag, to enable
  1391. * support for queueing. this works transparently for
  1392. * queued and non-queued modes.
  1393. */
  1394. else
  1395. tag = le16_to_cpu(pp->crpb[out_index].id) & 0x1f;
  1396. qc = ata_qc_from_tag(ap, tag);
  1397. /* For non-NCQ mode, the lower 8 bits of status
  1398. * are from EDMA_ERR_IRQ_CAUSE_OFS,
  1399. * which should be zero if all went well.
  1400. */
  1401. status = le16_to_cpu(pp->crpb[out_index].flags);
  1402. if ((status & 0xff) && !(pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
  1403. mv_err_intr(ap, qc);
  1404. return;
  1405. }
  1406. /* and finally, complete the ATA command */
  1407. if (qc) {
  1408. qc->err_mask |=
  1409. ac_err_mask(status >> CRPB_FLAG_STATUS_SHIFT);
  1410. ata_qc_complete(qc);
  1411. }
  1412. /* advance software response queue pointer, to
  1413. * indicate (after the loop completes) to hardware
  1414. * that we have consumed a response queue entry.
  1415. */
  1416. work_done = true;
  1417. pp->resp_idx++;
  1418. }
  1419. if (work_done)
  1420. writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
  1421. (out_index << EDMA_RSP_Q_PTR_SHIFT),
  1422. port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
  1423. }
  1424. /**
  1425. * mv_host_intr - Handle all interrupts on the given host controller
  1426. * @host: host specific structure
  1427. * @relevant: port error bits relevant to this host controller
  1428. * @hc: which host controller we're to look at
  1429. *
  1430. * Read then write clear the HC interrupt status then walk each
  1431. * port connected to the HC and see if it needs servicing. Port
  1432. * success ints are reported in the HC interrupt status reg, the
  1433. * port error ints are reported in the higher level main
  1434. * interrupt status register and thus are passed in via the
  1435. * 'relevant' argument.
  1436. *
  1437. * LOCKING:
  1438. * Inherited from caller.
  1439. */
  1440. static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
  1441. {
  1442. struct mv_host_priv *hpriv = host->private_data;
  1443. void __iomem *mmio = hpriv->base;
  1444. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  1445. u32 hc_irq_cause;
  1446. int port, port0, last_port;
  1447. if (hc == 0)
  1448. port0 = 0;
  1449. else
  1450. port0 = MV_PORTS_PER_HC;
  1451. if (HAS_PCI(host))
  1452. last_port = port0 + MV_PORTS_PER_HC;
  1453. else
  1454. last_port = port0 + hpriv->n_ports;
  1455. /* we'll need the HC success int register in most cases */
  1456. hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
  1457. if (!hc_irq_cause)
  1458. return;
  1459. writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
  1460. VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
  1461. hc, relevant, hc_irq_cause);
  1462. for (port = port0; port < last_port; port++) {
  1463. struct ata_port *ap = host->ports[port];
  1464. struct mv_port_priv *pp;
  1465. int have_err_bits, hard_port, shift;
  1466. if ((!ap) || (ap->flags & ATA_FLAG_DISABLED))
  1467. continue;
  1468. pp = ap->private_data;
  1469. shift = port << 1; /* (port * 2) */
  1470. if (port >= MV_PORTS_PER_HC)
  1471. shift++; /* skip bit 8 in the HC Main IRQ reg */
  1472. have_err_bits = ((PORT0_ERR << shift) & relevant);
  1473. if (unlikely(have_err_bits)) {
  1474. struct ata_queued_cmd *qc;
  1475. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1476. if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
  1477. continue;
  1478. mv_err_intr(ap, qc);
  1479. continue;
  1480. }
  1481. hard_port = mv_hardport_from_port(port); /* range 0..3 */
  1482. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  1483. if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause)
  1484. mv_intr_edma(ap);
  1485. } else {
  1486. if ((DEV_IRQ << hard_port) & hc_irq_cause)
  1487. mv_intr_pio(ap);
  1488. }
  1489. }
  1490. VPRINTK("EXIT\n");
  1491. }
  1492. static void mv_pci_error(struct ata_host *host, void __iomem *mmio)
  1493. {
  1494. struct mv_host_priv *hpriv = host->private_data;
  1495. struct ata_port *ap;
  1496. struct ata_queued_cmd *qc;
  1497. struct ata_eh_info *ehi;
  1498. unsigned int i, err_mask, printed = 0;
  1499. u32 err_cause;
  1500. err_cause = readl(mmio + hpriv->irq_cause_ofs);
  1501. dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
  1502. err_cause);
  1503. DPRINTK("All regs @ PCI error\n");
  1504. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  1505. writelfl(0, mmio + hpriv->irq_cause_ofs);
  1506. for (i = 0; i < host->n_ports; i++) {
  1507. ap = host->ports[i];
  1508. if (!ata_link_offline(&ap->link)) {
  1509. ehi = &ap->link.eh_info;
  1510. ata_ehi_clear_desc(ehi);
  1511. if (!printed++)
  1512. ata_ehi_push_desc(ehi,
  1513. "PCI err cause 0x%08x", err_cause);
  1514. err_mask = AC_ERR_HOST_BUS;
  1515. ehi->action = ATA_EH_RESET;
  1516. qc = ata_qc_from_tag(ap, ap->link.active_tag);
  1517. if (qc)
  1518. qc->err_mask |= err_mask;
  1519. else
  1520. ehi->err_mask |= err_mask;
  1521. ata_port_freeze(ap);
  1522. }
  1523. }
  1524. }
  1525. /**
  1526. * mv_interrupt - Main interrupt event handler
  1527. * @irq: unused
  1528. * @dev_instance: private data; in this case the host structure
  1529. *
  1530. * Read the read only register to determine if any host
  1531. * controllers have pending interrupts. If so, call lower level
  1532. * routine to handle. Also check for PCI errors which are only
  1533. * reported here.
  1534. *
  1535. * LOCKING:
  1536. * This routine holds the host lock while processing pending
  1537. * interrupts.
  1538. */
  1539. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  1540. {
  1541. struct ata_host *host = dev_instance;
  1542. struct mv_host_priv *hpriv = host->private_data;
  1543. unsigned int hc, handled = 0, n_hcs;
  1544. void __iomem *mmio = hpriv->base;
  1545. u32 irq_stat, irq_mask;
  1546. /* Note to self: &host->lock == &ap->host->lock == ap->lock */
  1547. spin_lock(&host->lock);
  1548. irq_stat = readl(hpriv->main_cause_reg_addr);
  1549. irq_mask = readl(hpriv->main_mask_reg_addr);
  1550. /* check the cases where we either have nothing pending or have read
  1551. * a bogus register value which can indicate HW removal or PCI fault
  1552. */
  1553. if (!(irq_stat & irq_mask) || (0xffffffffU == irq_stat))
  1554. goto out_unlock;
  1555. n_hcs = mv_get_hc_count(host->ports[0]->flags);
  1556. if (unlikely((irq_stat & PCI_ERR) && HAS_PCI(host))) {
  1557. mv_pci_error(host, mmio);
  1558. handled = 1;
  1559. goto out_unlock; /* skip all other HC irq handling */
  1560. }
  1561. for (hc = 0; hc < n_hcs; hc++) {
  1562. u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
  1563. if (relevant) {
  1564. mv_host_intr(host, relevant, hc);
  1565. handled = 1;
  1566. }
  1567. }
  1568. out_unlock:
  1569. spin_unlock(&host->lock);
  1570. return IRQ_RETVAL(handled);
  1571. }
  1572. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  1573. {
  1574. unsigned int ofs;
  1575. switch (sc_reg_in) {
  1576. case SCR_STATUS:
  1577. case SCR_ERROR:
  1578. case SCR_CONTROL:
  1579. ofs = sc_reg_in * sizeof(u32);
  1580. break;
  1581. default:
  1582. ofs = 0xffffffffU;
  1583. break;
  1584. }
  1585. return ofs;
  1586. }
  1587. static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
  1588. {
  1589. struct mv_host_priv *hpriv = ap->host->private_data;
  1590. void __iomem *mmio = hpriv->base;
  1591. void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
  1592. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  1593. if (ofs != 0xffffffffU) {
  1594. *val = readl(addr + ofs);
  1595. return 0;
  1596. } else
  1597. return -EINVAL;
  1598. }
  1599. static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
  1600. {
  1601. struct mv_host_priv *hpriv = ap->host->private_data;
  1602. void __iomem *mmio = hpriv->base;
  1603. void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
  1604. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  1605. if (ofs != 0xffffffffU) {
  1606. writelfl(val, addr + ofs);
  1607. return 0;
  1608. } else
  1609. return -EINVAL;
  1610. }
  1611. static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
  1612. {
  1613. struct pci_dev *pdev = to_pci_dev(host->dev);
  1614. int early_5080;
  1615. early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
  1616. if (!early_5080) {
  1617. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1618. tmp |= (1 << 0);
  1619. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1620. }
  1621. mv_reset_pci_bus(host, mmio);
  1622. }
  1623. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  1624. {
  1625. writel(0x0fcfffff, mmio + MV_FLASH_CTL);
  1626. }
  1627. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  1628. void __iomem *mmio)
  1629. {
  1630. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  1631. u32 tmp;
  1632. tmp = readl(phy_mmio + MV5_PHY_MODE);
  1633. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  1634. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  1635. }
  1636. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  1637. {
  1638. u32 tmp;
  1639. writel(0, mmio + MV_GPIO_PORT_CTL);
  1640. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  1641. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1642. tmp |= ~(1 << 0);
  1643. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1644. }
  1645. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  1646. unsigned int port)
  1647. {
  1648. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  1649. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  1650. u32 tmp;
  1651. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  1652. if (fix_apm_sq) {
  1653. tmp = readl(phy_mmio + MV5_LT_MODE);
  1654. tmp |= (1 << 19);
  1655. writel(tmp, phy_mmio + MV5_LT_MODE);
  1656. tmp = readl(phy_mmio + MV5_PHY_CTL);
  1657. tmp &= ~0x3;
  1658. tmp |= 0x1;
  1659. writel(tmp, phy_mmio + MV5_PHY_CTL);
  1660. }
  1661. tmp = readl(phy_mmio + MV5_PHY_MODE);
  1662. tmp &= ~mask;
  1663. tmp |= hpriv->signal[port].pre;
  1664. tmp |= hpriv->signal[port].amps;
  1665. writel(tmp, phy_mmio + MV5_PHY_MODE);
  1666. }
  1667. #undef ZERO
  1668. #define ZERO(reg) writel(0, port_mmio + (reg))
  1669. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  1670. unsigned int port)
  1671. {
  1672. void __iomem *port_mmio = mv_port_base(mmio, port);
  1673. /*
  1674. * The datasheet warns against setting ATA_RST when EDMA is active
  1675. * (but doesn't say what the problem might be). So we first try
  1676. * to disable the EDMA engine before doing the ATA_RST operation.
  1677. */
  1678. mv_reset_channel(hpriv, mmio, port);
  1679. ZERO(0x028); /* command */
  1680. writel(0x11f, port_mmio + EDMA_CFG_OFS);
  1681. ZERO(0x004); /* timer */
  1682. ZERO(0x008); /* irq err cause */
  1683. ZERO(0x00c); /* irq err mask */
  1684. ZERO(0x010); /* rq bah */
  1685. ZERO(0x014); /* rq inp */
  1686. ZERO(0x018); /* rq outp */
  1687. ZERO(0x01c); /* respq bah */
  1688. ZERO(0x024); /* respq outp */
  1689. ZERO(0x020); /* respq inp */
  1690. ZERO(0x02c); /* test control */
  1691. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  1692. }
  1693. #undef ZERO
  1694. #define ZERO(reg) writel(0, hc_mmio + (reg))
  1695. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1696. unsigned int hc)
  1697. {
  1698. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  1699. u32 tmp;
  1700. ZERO(0x00c);
  1701. ZERO(0x010);
  1702. ZERO(0x014);
  1703. ZERO(0x018);
  1704. tmp = readl(hc_mmio + 0x20);
  1705. tmp &= 0x1c1c1c1c;
  1706. tmp |= 0x03030303;
  1707. writel(tmp, hc_mmio + 0x20);
  1708. }
  1709. #undef ZERO
  1710. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1711. unsigned int n_hc)
  1712. {
  1713. unsigned int hc, port;
  1714. for (hc = 0; hc < n_hc; hc++) {
  1715. for (port = 0; port < MV_PORTS_PER_HC; port++)
  1716. mv5_reset_hc_port(hpriv, mmio,
  1717. (hc * MV_PORTS_PER_HC) + port);
  1718. mv5_reset_one_hc(hpriv, mmio, hc);
  1719. }
  1720. return 0;
  1721. }
  1722. #undef ZERO
  1723. #define ZERO(reg) writel(0, mmio + (reg))
  1724. static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
  1725. {
  1726. struct mv_host_priv *hpriv = host->private_data;
  1727. u32 tmp;
  1728. tmp = readl(mmio + MV_PCI_MODE);
  1729. tmp &= 0xff00ffff;
  1730. writel(tmp, mmio + MV_PCI_MODE);
  1731. ZERO(MV_PCI_DISC_TIMER);
  1732. ZERO(MV_PCI_MSI_TRIGGER);
  1733. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  1734. ZERO(HC_MAIN_IRQ_MASK_OFS);
  1735. ZERO(MV_PCI_SERR_MASK);
  1736. ZERO(hpriv->irq_cause_ofs);
  1737. ZERO(hpriv->irq_mask_ofs);
  1738. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  1739. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  1740. ZERO(MV_PCI_ERR_ATTRIBUTE);
  1741. ZERO(MV_PCI_ERR_COMMAND);
  1742. }
  1743. #undef ZERO
  1744. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  1745. {
  1746. u32 tmp;
  1747. mv5_reset_flash(hpriv, mmio);
  1748. tmp = readl(mmio + MV_GPIO_PORT_CTL);
  1749. tmp &= 0x3;
  1750. tmp |= (1 << 5) | (1 << 6);
  1751. writel(tmp, mmio + MV_GPIO_PORT_CTL);
  1752. }
  1753. /**
  1754. * mv6_reset_hc - Perform the 6xxx global soft reset
  1755. * @mmio: base address of the HBA
  1756. *
  1757. * This routine only applies to 6xxx parts.
  1758. *
  1759. * LOCKING:
  1760. * Inherited from caller.
  1761. */
  1762. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1763. unsigned int n_hc)
  1764. {
  1765. void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
  1766. int i, rc = 0;
  1767. u32 t;
  1768. /* Following procedure defined in PCI "main command and status
  1769. * register" table.
  1770. */
  1771. t = readl(reg);
  1772. writel(t | STOP_PCI_MASTER, reg);
  1773. for (i = 0; i < 1000; i++) {
  1774. udelay(1);
  1775. t = readl(reg);
  1776. if (PCI_MASTER_EMPTY & t)
  1777. break;
  1778. }
  1779. if (!(PCI_MASTER_EMPTY & t)) {
  1780. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  1781. rc = 1;
  1782. goto done;
  1783. }
  1784. /* set reset */
  1785. i = 5;
  1786. do {
  1787. writel(t | GLOB_SFT_RST, reg);
  1788. t = readl(reg);
  1789. udelay(1);
  1790. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  1791. if (!(GLOB_SFT_RST & t)) {
  1792. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  1793. rc = 1;
  1794. goto done;
  1795. }
  1796. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  1797. i = 5;
  1798. do {
  1799. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  1800. t = readl(reg);
  1801. udelay(1);
  1802. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  1803. if (GLOB_SFT_RST & t) {
  1804. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  1805. rc = 1;
  1806. }
  1807. /*
  1808. * Temporary: wait 3 seconds before port-probing can happen,
  1809. * so that we don't miss finding sleepy SilXXXX port-multipliers.
  1810. * This can go away once hotplug is fully/correctly implemented.
  1811. */
  1812. if (rc == 0)
  1813. msleep(3000);
  1814. done:
  1815. return rc;
  1816. }
  1817. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  1818. void __iomem *mmio)
  1819. {
  1820. void __iomem *port_mmio;
  1821. u32 tmp;
  1822. tmp = readl(mmio + MV_RESET_CFG);
  1823. if ((tmp & (1 << 0)) == 0) {
  1824. hpriv->signal[idx].amps = 0x7 << 8;
  1825. hpriv->signal[idx].pre = 0x1 << 5;
  1826. return;
  1827. }
  1828. port_mmio = mv_port_base(mmio, idx);
  1829. tmp = readl(port_mmio + PHY_MODE2);
  1830. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  1831. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  1832. }
  1833. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  1834. {
  1835. writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
  1836. }
  1837. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  1838. unsigned int port)
  1839. {
  1840. void __iomem *port_mmio = mv_port_base(mmio, port);
  1841. u32 hp_flags = hpriv->hp_flags;
  1842. int fix_phy_mode2 =
  1843. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  1844. int fix_phy_mode4 =
  1845. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  1846. u32 m2, tmp;
  1847. if (fix_phy_mode2) {
  1848. m2 = readl(port_mmio + PHY_MODE2);
  1849. m2 &= ~(1 << 16);
  1850. m2 |= (1 << 31);
  1851. writel(m2, port_mmio + PHY_MODE2);
  1852. udelay(200);
  1853. m2 = readl(port_mmio + PHY_MODE2);
  1854. m2 &= ~((1 << 16) | (1 << 31));
  1855. writel(m2, port_mmio + PHY_MODE2);
  1856. udelay(200);
  1857. }
  1858. /* who knows what this magic does */
  1859. tmp = readl(port_mmio + PHY_MODE3);
  1860. tmp &= ~0x7F800000;
  1861. tmp |= 0x2A800000;
  1862. writel(tmp, port_mmio + PHY_MODE3);
  1863. if (fix_phy_mode4) {
  1864. u32 m4;
  1865. m4 = readl(port_mmio + PHY_MODE4);
  1866. if (hp_flags & MV_HP_ERRATA_60X1B2)
  1867. tmp = readl(port_mmio + PHY_MODE3);
  1868. /* workaround for errata FEr SATA#10 (part 1) */
  1869. m4 = (m4 & ~(1 << 1)) | (1 << 0);
  1870. writel(m4, port_mmio + PHY_MODE4);
  1871. if (hp_flags & MV_HP_ERRATA_60X1B2)
  1872. writel(tmp, port_mmio + PHY_MODE3);
  1873. }
  1874. /* Revert values of pre-emphasis and signal amps to the saved ones */
  1875. m2 = readl(port_mmio + PHY_MODE2);
  1876. m2 &= ~MV_M2_PREAMP_MASK;
  1877. m2 |= hpriv->signal[port].amps;
  1878. m2 |= hpriv->signal[port].pre;
  1879. m2 &= ~(1 << 16);
  1880. /* according to mvSata 3.6.1, some IIE values are fixed */
  1881. if (IS_GEN_IIE(hpriv)) {
  1882. m2 &= ~0xC30FF01F;
  1883. m2 |= 0x0000900F;
  1884. }
  1885. writel(m2, port_mmio + PHY_MODE2);
  1886. }
  1887. /* TODO: use the generic LED interface to configure the SATA Presence */
  1888. /* & Acitivy LEDs on the board */
  1889. static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
  1890. void __iomem *mmio)
  1891. {
  1892. return;
  1893. }
  1894. static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
  1895. void __iomem *mmio)
  1896. {
  1897. void __iomem *port_mmio;
  1898. u32 tmp;
  1899. port_mmio = mv_port_base(mmio, idx);
  1900. tmp = readl(port_mmio + PHY_MODE2);
  1901. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  1902. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  1903. }
  1904. #undef ZERO
  1905. #define ZERO(reg) writel(0, port_mmio + (reg))
  1906. static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
  1907. void __iomem *mmio, unsigned int port)
  1908. {
  1909. void __iomem *port_mmio = mv_port_base(mmio, port);
  1910. /*
  1911. * The datasheet warns against setting ATA_RST when EDMA is active
  1912. * (but doesn't say what the problem might be). So we first try
  1913. * to disable the EDMA engine before doing the ATA_RST operation.
  1914. */
  1915. mv_reset_channel(hpriv, mmio, port);
  1916. ZERO(0x028); /* command */
  1917. writel(0x101f, port_mmio + EDMA_CFG_OFS);
  1918. ZERO(0x004); /* timer */
  1919. ZERO(0x008); /* irq err cause */
  1920. ZERO(0x00c); /* irq err mask */
  1921. ZERO(0x010); /* rq bah */
  1922. ZERO(0x014); /* rq inp */
  1923. ZERO(0x018); /* rq outp */
  1924. ZERO(0x01c); /* respq bah */
  1925. ZERO(0x024); /* respq outp */
  1926. ZERO(0x020); /* respq inp */
  1927. ZERO(0x02c); /* test control */
  1928. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  1929. }
  1930. #undef ZERO
  1931. #define ZERO(reg) writel(0, hc_mmio + (reg))
  1932. static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
  1933. void __iomem *mmio)
  1934. {
  1935. void __iomem *hc_mmio = mv_hc_base(mmio, 0);
  1936. ZERO(0x00c);
  1937. ZERO(0x010);
  1938. ZERO(0x014);
  1939. }
  1940. #undef ZERO
  1941. static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
  1942. void __iomem *mmio, unsigned int n_hc)
  1943. {
  1944. unsigned int port;
  1945. for (port = 0; port < hpriv->n_ports; port++)
  1946. mv_soc_reset_hc_port(hpriv, mmio, port);
  1947. mv_soc_reset_one_hc(hpriv, mmio);
  1948. return 0;
  1949. }
  1950. static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
  1951. void __iomem *mmio)
  1952. {
  1953. return;
  1954. }
  1955. static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
  1956. {
  1957. return;
  1958. }
  1959. static void mv_setup_ifctl(void __iomem *port_mmio, int want_gen2i)
  1960. {
  1961. u32 ifctl = readl(port_mmio + SATA_INTERFACE_CFG);
  1962. ifctl = (ifctl & 0xf7f) | 0x9b1000; /* from chip spec */
  1963. if (want_gen2i)
  1964. ifctl |= (1 << 7); /* enable gen2i speed */
  1965. writelfl(ifctl, port_mmio + SATA_INTERFACE_CFG);
  1966. }
  1967. /*
  1968. * Caller must ensure that EDMA is not active,
  1969. * by first doing mv_stop_edma() where needed.
  1970. */
  1971. static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
  1972. unsigned int port_no)
  1973. {
  1974. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  1975. mv_stop_edma_engine(port_mmio);
  1976. writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
  1977. if (!IS_GEN_I(hpriv)) {
  1978. /* Enable 3.0gb/s link speed */
  1979. mv_setup_ifctl(port_mmio, 1);
  1980. }
  1981. /*
  1982. * Strobing ATA_RST here causes a hard reset of the SATA transport,
  1983. * link, and physical layers. It resets all SATA interface registers
  1984. * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
  1985. */
  1986. writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
  1987. udelay(25); /* allow reset propagation */
  1988. writelfl(0, port_mmio + EDMA_CMD_OFS);
  1989. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  1990. if (IS_GEN_I(hpriv))
  1991. mdelay(1);
  1992. }
  1993. static void mv_pmp_select(struct ata_port *ap, int pmp)
  1994. {
  1995. if (sata_pmp_supported(ap)) {
  1996. void __iomem *port_mmio = mv_ap_base(ap);
  1997. u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
  1998. int old = reg & 0xf;
  1999. if (old != pmp) {
  2000. reg = (reg & ~0xf) | pmp;
  2001. writelfl(reg, port_mmio + SATA_IFCTL_OFS);
  2002. }
  2003. }
  2004. }
  2005. static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
  2006. unsigned long deadline)
  2007. {
  2008. mv_pmp_select(link->ap, sata_srst_pmp(link));
  2009. return sata_std_hardreset(link, class, deadline);
  2010. }
  2011. static int mv_softreset(struct ata_link *link, unsigned int *class,
  2012. unsigned long deadline)
  2013. {
  2014. mv_pmp_select(link->ap, sata_srst_pmp(link));
  2015. return ata_sff_softreset(link, class, deadline);
  2016. }
  2017. static int mv_hardreset(struct ata_link *link, unsigned int *class,
  2018. unsigned long deadline)
  2019. {
  2020. struct ata_port *ap = link->ap;
  2021. struct mv_host_priv *hpriv = ap->host->private_data;
  2022. struct mv_port_priv *pp = ap->private_data;
  2023. void __iomem *mmio = hpriv->base;
  2024. int rc, attempts = 0, extra = 0;
  2025. u32 sstatus;
  2026. bool online;
  2027. mv_reset_channel(hpriv, mmio, ap->port_no);
  2028. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  2029. /* Workaround for errata FEr SATA#10 (part 2) */
  2030. do {
  2031. const unsigned long *timing =
  2032. sata_ehc_deb_timing(&link->eh_context);
  2033. rc = sata_link_hardreset(link, timing, deadline + extra,
  2034. &online, NULL);
  2035. if (rc)
  2036. return rc;
  2037. sata_scr_read(link, SCR_STATUS, &sstatus);
  2038. if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
  2039. /* Force 1.5gb/s link speed and try again */
  2040. mv_setup_ifctl(mv_ap_base(ap), 0);
  2041. if (time_after(jiffies + HZ, deadline))
  2042. extra = HZ; /* only extend it once, max */
  2043. }
  2044. } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
  2045. return rc;
  2046. }
  2047. static void mv_eh_freeze(struct ata_port *ap)
  2048. {
  2049. struct mv_host_priv *hpriv = ap->host->private_data;
  2050. unsigned int hc = (ap->port_no > 3) ? 1 : 0;
  2051. u32 tmp, mask;
  2052. unsigned int shift;
  2053. /* FIXME: handle coalescing completion events properly */
  2054. shift = ap->port_no * 2;
  2055. if (hc > 0)
  2056. shift++;
  2057. mask = 0x3 << shift;
  2058. /* disable assertion of portN err, done events */
  2059. tmp = readl(hpriv->main_mask_reg_addr);
  2060. writelfl(tmp & ~mask, hpriv->main_mask_reg_addr);
  2061. }
  2062. static void mv_eh_thaw(struct ata_port *ap)
  2063. {
  2064. struct mv_host_priv *hpriv = ap->host->private_data;
  2065. void __iomem *mmio = hpriv->base;
  2066. unsigned int hc = (ap->port_no > 3) ? 1 : 0;
  2067. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2068. void __iomem *port_mmio = mv_ap_base(ap);
  2069. u32 tmp, mask, hc_irq_cause;
  2070. unsigned int shift, hc_port_no = ap->port_no;
  2071. /* FIXME: handle coalescing completion events properly */
  2072. shift = ap->port_no * 2;
  2073. if (hc > 0) {
  2074. shift++;
  2075. hc_port_no -= 4;
  2076. }
  2077. mask = 0x3 << shift;
  2078. /* clear EDMA errors on this port */
  2079. writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  2080. /* clear pending irq events */
  2081. hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
  2082. hc_irq_cause &= ~(1 << hc_port_no); /* clear CRPB-done */
  2083. hc_irq_cause &= ~(1 << (hc_port_no + 8)); /* clear Device int */
  2084. writel(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
  2085. /* enable assertion of portN err, done events */
  2086. tmp = readl(hpriv->main_mask_reg_addr);
  2087. writelfl(tmp | mask, hpriv->main_mask_reg_addr);
  2088. }
  2089. /**
  2090. * mv_port_init - Perform some early initialization on a single port.
  2091. * @port: libata data structure storing shadow register addresses
  2092. * @port_mmio: base address of the port
  2093. *
  2094. * Initialize shadow register mmio addresses, clear outstanding
  2095. * interrupts on the port, and unmask interrupts for the future
  2096. * start of the port.
  2097. *
  2098. * LOCKING:
  2099. * Inherited from caller.
  2100. */
  2101. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  2102. {
  2103. void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
  2104. unsigned serr_ofs;
  2105. /* PIO related setup
  2106. */
  2107. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  2108. port->error_addr =
  2109. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  2110. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  2111. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  2112. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  2113. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  2114. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  2115. port->status_addr =
  2116. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  2117. /* special case: control/altstatus doesn't have ATA_REG_ address */
  2118. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
  2119. /* unused: */
  2120. port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
  2121. /* Clear any currently outstanding port interrupt conditions */
  2122. serr_ofs = mv_scr_offset(SCR_ERROR);
  2123. writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
  2124. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  2125. /* unmask all non-transient EDMA error interrupts */
  2126. writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
  2127. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  2128. readl(port_mmio + EDMA_CFG_OFS),
  2129. readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
  2130. readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
  2131. }
  2132. static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
  2133. {
  2134. struct pci_dev *pdev = to_pci_dev(host->dev);
  2135. struct mv_host_priv *hpriv = host->private_data;
  2136. u32 hp_flags = hpriv->hp_flags;
  2137. switch (board_idx) {
  2138. case chip_5080:
  2139. hpriv->ops = &mv5xxx_ops;
  2140. hp_flags |= MV_HP_GEN_I;
  2141. switch (pdev->revision) {
  2142. case 0x1:
  2143. hp_flags |= MV_HP_ERRATA_50XXB0;
  2144. break;
  2145. case 0x3:
  2146. hp_flags |= MV_HP_ERRATA_50XXB2;
  2147. break;
  2148. default:
  2149. dev_printk(KERN_WARNING, &pdev->dev,
  2150. "Applying 50XXB2 workarounds to unknown rev\n");
  2151. hp_flags |= MV_HP_ERRATA_50XXB2;
  2152. break;
  2153. }
  2154. break;
  2155. case chip_504x:
  2156. case chip_508x:
  2157. hpriv->ops = &mv5xxx_ops;
  2158. hp_flags |= MV_HP_GEN_I;
  2159. switch (pdev->revision) {
  2160. case 0x0:
  2161. hp_flags |= MV_HP_ERRATA_50XXB0;
  2162. break;
  2163. case 0x3:
  2164. hp_flags |= MV_HP_ERRATA_50XXB2;
  2165. break;
  2166. default:
  2167. dev_printk(KERN_WARNING, &pdev->dev,
  2168. "Applying B2 workarounds to unknown rev\n");
  2169. hp_flags |= MV_HP_ERRATA_50XXB2;
  2170. break;
  2171. }
  2172. break;
  2173. case chip_604x:
  2174. case chip_608x:
  2175. hpriv->ops = &mv6xxx_ops;
  2176. hp_flags |= MV_HP_GEN_II;
  2177. switch (pdev->revision) {
  2178. case 0x7:
  2179. hp_flags |= MV_HP_ERRATA_60X1B2;
  2180. break;
  2181. case 0x9:
  2182. hp_flags |= MV_HP_ERRATA_60X1C0;
  2183. break;
  2184. default:
  2185. dev_printk(KERN_WARNING, &pdev->dev,
  2186. "Applying B2 workarounds to unknown rev\n");
  2187. hp_flags |= MV_HP_ERRATA_60X1B2;
  2188. break;
  2189. }
  2190. break;
  2191. case chip_7042:
  2192. hp_flags |= MV_HP_PCIE;
  2193. if (pdev->vendor == PCI_VENDOR_ID_TTI &&
  2194. (pdev->device == 0x2300 || pdev->device == 0x2310))
  2195. {
  2196. /*
  2197. * Highpoint RocketRAID PCIe 23xx series cards:
  2198. *
  2199. * Unconfigured drives are treated as "Legacy"
  2200. * by the BIOS, and it overwrites sector 8 with
  2201. * a "Lgcy" metadata block prior to Linux boot.
  2202. *
  2203. * Configured drives (RAID or JBOD) leave sector 8
  2204. * alone, but instead overwrite a high numbered
  2205. * sector for the RAID metadata. This sector can
  2206. * be determined exactly, by truncating the physical
  2207. * drive capacity to a nice even GB value.
  2208. *
  2209. * RAID metadata is at: (dev->n_sectors & ~0xfffff)
  2210. *
  2211. * Warn the user, lest they think we're just buggy.
  2212. */
  2213. printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
  2214. " BIOS CORRUPTS DATA on all attached drives,"
  2215. " regardless of if/how they are configured."
  2216. " BEWARE!\n");
  2217. printk(KERN_WARNING DRV_NAME ": For data safety, do not"
  2218. " use sectors 8-9 on \"Legacy\" drives,"
  2219. " and avoid the final two gigabytes on"
  2220. " all RocketRAID BIOS initialized drives.\n");
  2221. }
  2222. case chip_6042:
  2223. hpriv->ops = &mv6xxx_ops;
  2224. hp_flags |= MV_HP_GEN_IIE;
  2225. switch (pdev->revision) {
  2226. case 0x0:
  2227. hp_flags |= MV_HP_ERRATA_XX42A0;
  2228. break;
  2229. case 0x1:
  2230. hp_flags |= MV_HP_ERRATA_60X1C0;
  2231. break;
  2232. default:
  2233. dev_printk(KERN_WARNING, &pdev->dev,
  2234. "Applying 60X1C0 workarounds to unknown rev\n");
  2235. hp_flags |= MV_HP_ERRATA_60X1C0;
  2236. break;
  2237. }
  2238. break;
  2239. case chip_soc:
  2240. hpriv->ops = &mv_soc_ops;
  2241. hp_flags |= MV_HP_ERRATA_60X1C0;
  2242. break;
  2243. default:
  2244. dev_printk(KERN_ERR, host->dev,
  2245. "BUG: invalid board index %u\n", board_idx);
  2246. return 1;
  2247. }
  2248. hpriv->hp_flags = hp_flags;
  2249. if (hp_flags & MV_HP_PCIE) {
  2250. hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
  2251. hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
  2252. hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
  2253. } else {
  2254. hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
  2255. hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
  2256. hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
  2257. }
  2258. return 0;
  2259. }
  2260. /**
  2261. * mv_init_host - Perform some early initialization of the host.
  2262. * @host: ATA host to initialize
  2263. * @board_idx: controller index
  2264. *
  2265. * If possible, do an early global reset of the host. Then do
  2266. * our port init and clear/unmask all/relevant host interrupts.
  2267. *
  2268. * LOCKING:
  2269. * Inherited from caller.
  2270. */
  2271. static int mv_init_host(struct ata_host *host, unsigned int board_idx)
  2272. {
  2273. int rc = 0, n_hc, port, hc;
  2274. struct mv_host_priv *hpriv = host->private_data;
  2275. void __iomem *mmio = hpriv->base;
  2276. rc = mv_chip_id(host, board_idx);
  2277. if (rc)
  2278. goto done;
  2279. if (HAS_PCI(host)) {
  2280. hpriv->main_cause_reg_addr = hpriv->base +
  2281. HC_MAIN_IRQ_CAUSE_OFS;
  2282. hpriv->main_mask_reg_addr = hpriv->base + HC_MAIN_IRQ_MASK_OFS;
  2283. } else {
  2284. hpriv->main_cause_reg_addr = hpriv->base +
  2285. HC_SOC_MAIN_IRQ_CAUSE_OFS;
  2286. hpriv->main_mask_reg_addr = hpriv->base +
  2287. HC_SOC_MAIN_IRQ_MASK_OFS;
  2288. }
  2289. /* global interrupt mask */
  2290. writel(0, hpriv->main_mask_reg_addr);
  2291. n_hc = mv_get_hc_count(host->ports[0]->flags);
  2292. for (port = 0; port < host->n_ports; port++)
  2293. hpriv->ops->read_preamp(hpriv, port, mmio);
  2294. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  2295. if (rc)
  2296. goto done;
  2297. hpriv->ops->reset_flash(hpriv, mmio);
  2298. hpriv->ops->reset_bus(host, mmio);
  2299. hpriv->ops->enable_leds(hpriv, mmio);
  2300. for (port = 0; port < host->n_ports; port++) {
  2301. struct ata_port *ap = host->ports[port];
  2302. void __iomem *port_mmio = mv_port_base(mmio, port);
  2303. mv_port_init(&ap->ioaddr, port_mmio);
  2304. #ifdef CONFIG_PCI
  2305. if (HAS_PCI(host)) {
  2306. unsigned int offset = port_mmio - mmio;
  2307. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
  2308. ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
  2309. }
  2310. #endif
  2311. }
  2312. for (hc = 0; hc < n_hc; hc++) {
  2313. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  2314. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  2315. "(before clear)=0x%08x\n", hc,
  2316. readl(hc_mmio + HC_CFG_OFS),
  2317. readl(hc_mmio + HC_IRQ_CAUSE_OFS));
  2318. /* Clear any currently outstanding hc interrupt conditions */
  2319. writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
  2320. }
  2321. if (HAS_PCI(host)) {
  2322. /* Clear any currently outstanding host interrupt conditions */
  2323. writelfl(0, mmio + hpriv->irq_cause_ofs);
  2324. /* and unmask interrupt generation for host regs */
  2325. writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
  2326. if (IS_GEN_I(hpriv))
  2327. writelfl(~HC_MAIN_MASKED_IRQS_5,
  2328. hpriv->main_mask_reg_addr);
  2329. else
  2330. writelfl(~HC_MAIN_MASKED_IRQS,
  2331. hpriv->main_mask_reg_addr);
  2332. VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
  2333. "PCI int cause/mask=0x%08x/0x%08x\n",
  2334. readl(hpriv->main_cause_reg_addr),
  2335. readl(hpriv->main_mask_reg_addr),
  2336. readl(mmio + hpriv->irq_cause_ofs),
  2337. readl(mmio + hpriv->irq_mask_ofs));
  2338. } else {
  2339. writelfl(~HC_MAIN_MASKED_IRQS_SOC,
  2340. hpriv->main_mask_reg_addr);
  2341. VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
  2342. readl(hpriv->main_cause_reg_addr),
  2343. readl(hpriv->main_mask_reg_addr));
  2344. }
  2345. done:
  2346. return rc;
  2347. }
  2348. static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
  2349. {
  2350. hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
  2351. MV_CRQB_Q_SZ, 0);
  2352. if (!hpriv->crqb_pool)
  2353. return -ENOMEM;
  2354. hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
  2355. MV_CRPB_Q_SZ, 0);
  2356. if (!hpriv->crpb_pool)
  2357. return -ENOMEM;
  2358. hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
  2359. MV_SG_TBL_SZ, 0);
  2360. if (!hpriv->sg_tbl_pool)
  2361. return -ENOMEM;
  2362. return 0;
  2363. }
  2364. static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
  2365. struct mbus_dram_target_info *dram)
  2366. {
  2367. int i;
  2368. for (i = 0; i < 4; i++) {
  2369. writel(0, hpriv->base + WINDOW_CTRL(i));
  2370. writel(0, hpriv->base + WINDOW_BASE(i));
  2371. }
  2372. for (i = 0; i < dram->num_cs; i++) {
  2373. struct mbus_dram_window *cs = dram->cs + i;
  2374. writel(((cs->size - 1) & 0xffff0000) |
  2375. (cs->mbus_attr << 8) |
  2376. (dram->mbus_dram_target_id << 4) | 1,
  2377. hpriv->base + WINDOW_CTRL(i));
  2378. writel(cs->base, hpriv->base + WINDOW_BASE(i));
  2379. }
  2380. }
  2381. /**
  2382. * mv_platform_probe - handle a positive probe of an soc Marvell
  2383. * host
  2384. * @pdev: platform device found
  2385. *
  2386. * LOCKING:
  2387. * Inherited from caller.
  2388. */
  2389. static int mv_platform_probe(struct platform_device *pdev)
  2390. {
  2391. static int printed_version;
  2392. const struct mv_sata_platform_data *mv_platform_data;
  2393. const struct ata_port_info *ppi[] =
  2394. { &mv_port_info[chip_soc], NULL };
  2395. struct ata_host *host;
  2396. struct mv_host_priv *hpriv;
  2397. struct resource *res;
  2398. int n_ports, rc;
  2399. if (!printed_version++)
  2400. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  2401. /*
  2402. * Simple resource validation ..
  2403. */
  2404. if (unlikely(pdev->num_resources != 2)) {
  2405. dev_err(&pdev->dev, "invalid number of resources\n");
  2406. return -EINVAL;
  2407. }
  2408. /*
  2409. * Get the register base first
  2410. */
  2411. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2412. if (res == NULL)
  2413. return -EINVAL;
  2414. /* allocate host */
  2415. mv_platform_data = pdev->dev.platform_data;
  2416. n_ports = mv_platform_data->n_ports;
  2417. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  2418. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  2419. if (!host || !hpriv)
  2420. return -ENOMEM;
  2421. host->private_data = hpriv;
  2422. hpriv->n_ports = n_ports;
  2423. host->iomap = NULL;
  2424. hpriv->base = devm_ioremap(&pdev->dev, res->start,
  2425. res->end - res->start + 1);
  2426. hpriv->base -= MV_SATAHC0_REG_BASE;
  2427. /*
  2428. * (Re-)program MBUS remapping windows if we are asked to.
  2429. */
  2430. if (mv_platform_data->dram != NULL)
  2431. mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
  2432. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  2433. if (rc)
  2434. return rc;
  2435. /* initialize adapter */
  2436. rc = mv_init_host(host, chip_soc);
  2437. if (rc)
  2438. return rc;
  2439. dev_printk(KERN_INFO, &pdev->dev,
  2440. "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
  2441. host->n_ports);
  2442. return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
  2443. IRQF_SHARED, &mv6_sht);
  2444. }
  2445. /*
  2446. *
  2447. * mv_platform_remove - unplug a platform interface
  2448. * @pdev: platform device
  2449. *
  2450. * A platform bus SATA device has been unplugged. Perform the needed
  2451. * cleanup. Also called on module unload for any active devices.
  2452. */
  2453. static int __devexit mv_platform_remove(struct platform_device *pdev)
  2454. {
  2455. struct device *dev = &pdev->dev;
  2456. struct ata_host *host = dev_get_drvdata(dev);
  2457. ata_host_detach(host);
  2458. return 0;
  2459. }
  2460. static struct platform_driver mv_platform_driver = {
  2461. .probe = mv_platform_probe,
  2462. .remove = __devexit_p(mv_platform_remove),
  2463. .driver = {
  2464. .name = DRV_NAME,
  2465. .owner = THIS_MODULE,
  2466. },
  2467. };
  2468. #ifdef CONFIG_PCI
  2469. static int mv_pci_init_one(struct pci_dev *pdev,
  2470. const struct pci_device_id *ent);
  2471. static struct pci_driver mv_pci_driver = {
  2472. .name = DRV_NAME,
  2473. .id_table = mv_pci_tbl,
  2474. .probe = mv_pci_init_one,
  2475. .remove = ata_pci_remove_one,
  2476. };
  2477. /*
  2478. * module options
  2479. */
  2480. static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
  2481. /* move to PCI layer or libata core? */
  2482. static int pci_go_64(struct pci_dev *pdev)
  2483. {
  2484. int rc;
  2485. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  2486. rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  2487. if (rc) {
  2488. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  2489. if (rc) {
  2490. dev_printk(KERN_ERR, &pdev->dev,
  2491. "64-bit DMA enable failed\n");
  2492. return rc;
  2493. }
  2494. }
  2495. } else {
  2496. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2497. if (rc) {
  2498. dev_printk(KERN_ERR, &pdev->dev,
  2499. "32-bit DMA enable failed\n");
  2500. return rc;
  2501. }
  2502. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  2503. if (rc) {
  2504. dev_printk(KERN_ERR, &pdev->dev,
  2505. "32-bit consistent DMA enable failed\n");
  2506. return rc;
  2507. }
  2508. }
  2509. return rc;
  2510. }
  2511. /**
  2512. * mv_print_info - Dump key info to kernel log for perusal.
  2513. * @host: ATA host to print info about
  2514. *
  2515. * FIXME: complete this.
  2516. *
  2517. * LOCKING:
  2518. * Inherited from caller.
  2519. */
  2520. static void mv_print_info(struct ata_host *host)
  2521. {
  2522. struct pci_dev *pdev = to_pci_dev(host->dev);
  2523. struct mv_host_priv *hpriv = host->private_data;
  2524. u8 scc;
  2525. const char *scc_s, *gen;
  2526. /* Use this to determine the HW stepping of the chip so we know
  2527. * what errata to workaround
  2528. */
  2529. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  2530. if (scc == 0)
  2531. scc_s = "SCSI";
  2532. else if (scc == 0x01)
  2533. scc_s = "RAID";
  2534. else
  2535. scc_s = "?";
  2536. if (IS_GEN_I(hpriv))
  2537. gen = "I";
  2538. else if (IS_GEN_II(hpriv))
  2539. gen = "II";
  2540. else if (IS_GEN_IIE(hpriv))
  2541. gen = "IIE";
  2542. else
  2543. gen = "?";
  2544. dev_printk(KERN_INFO, &pdev->dev,
  2545. "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
  2546. gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
  2547. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  2548. }
  2549. /**
  2550. * mv_pci_init_one - handle a positive probe of a PCI Marvell host
  2551. * @pdev: PCI device found
  2552. * @ent: PCI device ID entry for the matched host
  2553. *
  2554. * LOCKING:
  2555. * Inherited from caller.
  2556. */
  2557. static int mv_pci_init_one(struct pci_dev *pdev,
  2558. const struct pci_device_id *ent)
  2559. {
  2560. static int printed_version;
  2561. unsigned int board_idx = (unsigned int)ent->driver_data;
  2562. const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
  2563. struct ata_host *host;
  2564. struct mv_host_priv *hpriv;
  2565. int n_ports, rc;
  2566. if (!printed_version++)
  2567. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  2568. /* allocate host */
  2569. n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
  2570. host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
  2571. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  2572. if (!host || !hpriv)
  2573. return -ENOMEM;
  2574. host->private_data = hpriv;
  2575. hpriv->n_ports = n_ports;
  2576. /* acquire resources */
  2577. rc = pcim_enable_device(pdev);
  2578. if (rc)
  2579. return rc;
  2580. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  2581. if (rc == -EBUSY)
  2582. pcim_pin_device(pdev);
  2583. if (rc)
  2584. return rc;
  2585. host->iomap = pcim_iomap_table(pdev);
  2586. hpriv->base = host->iomap[MV_PRIMARY_BAR];
  2587. rc = pci_go_64(pdev);
  2588. if (rc)
  2589. return rc;
  2590. rc = mv_create_dma_pools(hpriv, &pdev->dev);
  2591. if (rc)
  2592. return rc;
  2593. /* initialize adapter */
  2594. rc = mv_init_host(host, board_idx);
  2595. if (rc)
  2596. return rc;
  2597. /* Enable interrupts */
  2598. if (msi && pci_enable_msi(pdev))
  2599. pci_intx(pdev, 1);
  2600. mv_dump_pci_cfg(pdev, 0x68);
  2601. mv_print_info(host);
  2602. pci_set_master(pdev);
  2603. pci_try_set_mwi(pdev);
  2604. return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
  2605. IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
  2606. }
  2607. #endif
  2608. static int mv_platform_probe(struct platform_device *pdev);
  2609. static int __devexit mv_platform_remove(struct platform_device *pdev);
  2610. static int __init mv_init(void)
  2611. {
  2612. int rc = -ENODEV;
  2613. #ifdef CONFIG_PCI
  2614. rc = pci_register_driver(&mv_pci_driver);
  2615. if (rc < 0)
  2616. return rc;
  2617. #endif
  2618. rc = platform_driver_register(&mv_platform_driver);
  2619. #ifdef CONFIG_PCI
  2620. if (rc < 0)
  2621. pci_unregister_driver(&mv_pci_driver);
  2622. #endif
  2623. return rc;
  2624. }
  2625. static void __exit mv_exit(void)
  2626. {
  2627. #ifdef CONFIG_PCI
  2628. pci_unregister_driver(&mv_pci_driver);
  2629. #endif
  2630. platform_driver_unregister(&mv_platform_driver);
  2631. }
  2632. MODULE_AUTHOR("Brett Russ");
  2633. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  2634. MODULE_LICENSE("GPL");
  2635. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  2636. MODULE_VERSION(DRV_VERSION);
  2637. MODULE_ALIAS("platform:" DRV_NAME);
  2638. #ifdef CONFIG_PCI
  2639. module_param(msi, int, 0444);
  2640. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  2641. #endif
  2642. module_init(mv_init);
  2643. module_exit(mv_exit);