smp.c 6.0 KB

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  1. /*
  2. * SMP support for pSeries machines.
  3. *
  4. * Dave Engebretsen, Peter Bergner, and
  5. * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
  6. *
  7. * Plus various changes from other IBM teams...
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #undef DEBUG
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/delay.h>
  21. #include <linux/init.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/cache.h>
  24. #include <linux/err.h>
  25. #include <linux/sysdev.h>
  26. #include <linux/cpu.h>
  27. #include <asm/ptrace.h>
  28. #include <asm/atomic.h>
  29. #include <asm/irq.h>
  30. #include <asm/page.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/io.h>
  33. #include <asm/prom.h>
  34. #include <asm/smp.h>
  35. #include <asm/paca.h>
  36. #include <asm/time.h>
  37. #include <asm/machdep.h>
  38. #include "xics.h"
  39. #include <asm/cputable.h>
  40. #include <asm/firmware.h>
  41. #include <asm/system.h>
  42. #include <asm/rtas.h>
  43. #include <asm/pSeries_reconfig.h>
  44. #include <asm/mpic.h>
  45. #include <asm/vdso_datapage.h>
  46. #include <asm/cputhreads.h>
  47. #include "plpar_wrappers.h"
  48. #include "pseries.h"
  49. #ifdef DEBUG
  50. #include <asm/udbg.h>
  51. #define DBG(fmt...) udbg_printf(fmt)
  52. #else
  53. #define DBG(fmt...)
  54. #endif
  55. /*
  56. * The primary thread of each non-boot processor is recorded here before
  57. * smp init.
  58. */
  59. static cpumask_t of_spin_map;
  60. extern void generic_secondary_smp_init(unsigned long);
  61. /**
  62. * smp_startup_cpu() - start the given cpu
  63. *
  64. * At boot time, there is nothing to do for primary threads which were
  65. * started from Open Firmware. For anything else, call RTAS with the
  66. * appropriate start location.
  67. *
  68. * Returns:
  69. * 0 - failure
  70. * 1 - success
  71. */
  72. static inline int __devinit smp_startup_cpu(unsigned int lcpu)
  73. {
  74. int status;
  75. unsigned long start_here = __pa((u32)*((unsigned long *)
  76. generic_secondary_smp_init));
  77. unsigned int pcpu;
  78. int start_cpu;
  79. if (cpu_isset(lcpu, of_spin_map))
  80. /* Already started by OF and sitting in spin loop */
  81. return 1;
  82. pcpu = get_hard_smp_processor_id(lcpu);
  83. /* Fixup atomic count: it exited inside IRQ handler. */
  84. task_thread_info(paca[lcpu].__current)->preempt_count = 0;
  85. /*
  86. * If the RTAS start-cpu token does not exist then presume the
  87. * cpu is already spinning.
  88. */
  89. start_cpu = rtas_token("start-cpu");
  90. if (start_cpu == RTAS_UNKNOWN_SERVICE)
  91. return 1;
  92. status = rtas_call(start_cpu, 3, 1, NULL, pcpu, start_here, pcpu);
  93. if (status != 0) {
  94. printk(KERN_ERR "start-cpu failed: %i\n", status);
  95. return 0;
  96. }
  97. return 1;
  98. }
  99. #ifdef CONFIG_XICS
  100. static inline void smp_xics_do_message(int cpu, int msg)
  101. {
  102. set_bit(msg, &xics_ipi_message[cpu].value);
  103. mb();
  104. xics_cause_IPI(cpu);
  105. }
  106. static void smp_xics_message_pass(int target, int msg)
  107. {
  108. unsigned int i;
  109. if (target < NR_CPUS) {
  110. smp_xics_do_message(target, msg);
  111. } else {
  112. for_each_online_cpu(i) {
  113. if (target == MSG_ALL_BUT_SELF
  114. && i == smp_processor_id())
  115. continue;
  116. smp_xics_do_message(i, msg);
  117. }
  118. }
  119. }
  120. static int __init smp_xics_probe(void)
  121. {
  122. xics_request_IPIs();
  123. return cpus_weight(cpu_possible_map);
  124. }
  125. static void __devinit smp_xics_setup_cpu(int cpu)
  126. {
  127. if (cpu != boot_cpuid)
  128. xics_setup_cpu();
  129. if (firmware_has_feature(FW_FEATURE_SPLPAR))
  130. vpa_init(cpu);
  131. cpu_clear(cpu, of_spin_map);
  132. }
  133. #endif /* CONFIG_XICS */
  134. static DEFINE_SPINLOCK(timebase_lock);
  135. static unsigned long timebase = 0;
  136. static void __devinit pSeries_give_timebase(void)
  137. {
  138. spin_lock(&timebase_lock);
  139. rtas_call(rtas_token("freeze-time-base"), 0, 1, NULL);
  140. timebase = get_tb();
  141. spin_unlock(&timebase_lock);
  142. while (timebase)
  143. barrier();
  144. rtas_call(rtas_token("thaw-time-base"), 0, 1, NULL);
  145. }
  146. static void __devinit pSeries_take_timebase(void)
  147. {
  148. while (!timebase)
  149. barrier();
  150. spin_lock(&timebase_lock);
  151. set_tb(timebase >> 32, timebase & 0xffffffff);
  152. timebase = 0;
  153. spin_unlock(&timebase_lock);
  154. }
  155. static void __devinit smp_pSeries_kick_cpu(int nr)
  156. {
  157. BUG_ON(nr < 0 || nr >= NR_CPUS);
  158. if (!smp_startup_cpu(nr))
  159. return;
  160. /*
  161. * The processor is currently spinning, waiting for the
  162. * cpu_start field to become non-zero After we set cpu_start,
  163. * the processor will continue on to secondary_start
  164. */
  165. paca[nr].cpu_start = 1;
  166. }
  167. static int smp_pSeries_cpu_bootable(unsigned int nr)
  168. {
  169. /* Special case - we inhibit secondary thread startup
  170. * during boot if the user requests it. Odd-numbered
  171. * cpus are assumed to be secondary threads.
  172. */
  173. if (system_state < SYSTEM_RUNNING &&
  174. cpu_has_feature(CPU_FTR_SMT) &&
  175. !smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
  176. return 0;
  177. return 1;
  178. }
  179. #ifdef CONFIG_MPIC
  180. static struct smp_ops_t pSeries_mpic_smp_ops = {
  181. .message_pass = smp_mpic_message_pass,
  182. .probe = smp_mpic_probe,
  183. .kick_cpu = smp_pSeries_kick_cpu,
  184. .setup_cpu = smp_mpic_setup_cpu,
  185. };
  186. #endif
  187. #ifdef CONFIG_XICS
  188. static struct smp_ops_t pSeries_xics_smp_ops = {
  189. .message_pass = smp_xics_message_pass,
  190. .probe = smp_xics_probe,
  191. .kick_cpu = smp_pSeries_kick_cpu,
  192. .setup_cpu = smp_xics_setup_cpu,
  193. .cpu_bootable = smp_pSeries_cpu_bootable,
  194. };
  195. #endif
  196. /* This is called very early */
  197. static void __init smp_init_pseries(void)
  198. {
  199. int i;
  200. DBG(" -> smp_init_pSeries()\n");
  201. /* Mark threads which are still spinning in hold loops. */
  202. if (cpu_has_feature(CPU_FTR_SMT)) {
  203. for_each_present_cpu(i) {
  204. if (i % 2 == 0)
  205. /*
  206. * Even-numbered logical cpus correspond to
  207. * primary threads.
  208. */
  209. cpu_set(i, of_spin_map);
  210. }
  211. } else {
  212. of_spin_map = cpu_present_map;
  213. }
  214. cpu_clear(boot_cpuid, of_spin_map);
  215. /* Non-lpar has additional take/give timebase */
  216. if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
  217. smp_ops->give_timebase = pSeries_give_timebase;
  218. smp_ops->take_timebase = pSeries_take_timebase;
  219. }
  220. DBG(" <- smp_init_pSeries()\n");
  221. }
  222. #ifdef CONFIG_MPIC
  223. void __init smp_init_pseries_mpic(void)
  224. {
  225. smp_ops = &pSeries_mpic_smp_ops;
  226. smp_init_pseries();
  227. }
  228. #endif
  229. void __init smp_init_pseries_xics(void)
  230. {
  231. smp_ops = &pSeries_xics_smp_ops;
  232. smp_init_pseries();
  233. }