sequoia.dts 8.5 KB

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  1. /*
  2. * Device Tree Source for AMCC Sequoia
  3. *
  4. * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com>
  5. * Copyright (c) 2006, 2007 IBM Corp.
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. *
  13. */
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,sequoia";
  18. compatible = "amcc,sequoia";
  19. dcr-parent = <&/cpus/cpu@0>;
  20. aliases {
  21. ethernet0 = &EMAC0;
  22. ethernet1 = &EMAC1;
  23. serial0 = &UART0;
  24. serial1 = &UART1;
  25. serial2 = &UART2;
  26. serial3 = &UART3;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. cpu@0 {
  32. device_type = "cpu";
  33. model = "PowerPC,440EPx";
  34. reg = <0>;
  35. clock-frequency = <0>; /* Filled in by zImage */
  36. timebase-frequency = <0>; /* Filled in by zImage */
  37. i-cache-line-size = <20>;
  38. d-cache-line-size = <20>;
  39. i-cache-size = <8000>;
  40. d-cache-size = <8000>;
  41. dcr-controller;
  42. dcr-access-method = "native";
  43. };
  44. };
  45. memory {
  46. device_type = "memory";
  47. reg = <0 0 0>; /* Filled in by zImage */
  48. };
  49. UIC0: interrupt-controller0 {
  50. compatible = "ibm,uic-440epx","ibm,uic";
  51. interrupt-controller;
  52. cell-index = <0>;
  53. dcr-reg = <0c0 009>;
  54. #address-cells = <0>;
  55. #size-cells = <0>;
  56. #interrupt-cells = <2>;
  57. };
  58. UIC1: interrupt-controller1 {
  59. compatible = "ibm,uic-440epx","ibm,uic";
  60. interrupt-controller;
  61. cell-index = <1>;
  62. dcr-reg = <0d0 009>;
  63. #address-cells = <0>;
  64. #size-cells = <0>;
  65. #interrupt-cells = <2>;
  66. interrupts = <1e 4 1f 4>; /* cascade */
  67. interrupt-parent = <&UIC0>;
  68. };
  69. UIC2: interrupt-controller2 {
  70. compatible = "ibm,uic-440epx","ibm,uic";
  71. interrupt-controller;
  72. cell-index = <2>;
  73. dcr-reg = <0e0 009>;
  74. #address-cells = <0>;
  75. #size-cells = <0>;
  76. #interrupt-cells = <2>;
  77. interrupts = <1c 4 1d 4>; /* cascade */
  78. interrupt-parent = <&UIC0>;
  79. };
  80. SDR0: sdr {
  81. compatible = "ibm,sdr-440epx", "ibm,sdr-440ep";
  82. dcr-reg = <00e 002>;
  83. };
  84. CPR0: cpr {
  85. compatible = "ibm,cpr-440epx", "ibm,cpr-440ep";
  86. dcr-reg = <00c 002>;
  87. };
  88. plb {
  89. compatible = "ibm,plb-440epx", "ibm,plb4";
  90. #address-cells = <2>;
  91. #size-cells = <1>;
  92. ranges;
  93. clock-frequency = <0>; /* Filled in by zImage */
  94. SDRAM0: sdram {
  95. compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
  96. dcr-reg = <010 2>;
  97. };
  98. DMA0: dma {
  99. compatible = "ibm,dma-440epx", "ibm,dma-4xx";
  100. dcr-reg = <100 027>;
  101. };
  102. MAL0: mcmal {
  103. compatible = "ibm,mcmal-440epx", "ibm,mcmal2";
  104. dcr-reg = <180 62>;
  105. num-tx-chans = <2>;
  106. num-rx-chans = <2>;
  107. interrupt-parent = <&MAL0>;
  108. interrupts = <0 1 2 3 4>;
  109. #interrupt-cells = <1>;
  110. #address-cells = <0>;
  111. #size-cells = <0>;
  112. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  113. /*RXEOB*/ 1 &UIC0 b 4
  114. /*SERR*/ 2 &UIC1 0 4
  115. /*TXDE*/ 3 &UIC1 1 4
  116. /*RXDE*/ 4 &UIC1 2 4>;
  117. interrupt-map-mask = <ffffffff>;
  118. };
  119. USB1: usb@e0000400 {
  120. compatible = "ohci-be";
  121. reg = <0 e0000400 60>;
  122. interrupt-parent = <&UIC0>;
  123. interrupts = <15 8>;
  124. };
  125. USB0: ehci@e0000300 {
  126. compatible = "ibm,usb-ehci-440epx", "usb-ehci";
  127. interrupt-parent = <&UIC0>;
  128. interrupts = <1a 4>;
  129. reg = <0 e0000300 90 0 e0000390 70>;
  130. big-endian;
  131. };
  132. POB0: opb {
  133. compatible = "ibm,opb-440epx", "ibm,opb";
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. ranges = <00000000 1 00000000 80000000
  137. 80000000 1 80000000 80000000>;
  138. interrupt-parent = <&UIC1>;
  139. interrupts = <7 4>;
  140. clock-frequency = <0>; /* Filled in by zImage */
  141. EBC0: ebc {
  142. compatible = "ibm,ebc-440epx", "ibm,ebc";
  143. dcr-reg = <012 2>;
  144. #address-cells = <2>;
  145. #size-cells = <1>;
  146. clock-frequency = <0>; /* Filled in by zImage */
  147. interrupts = <5 1>;
  148. interrupt-parent = <&UIC1>;
  149. nor_flash@0,0 {
  150. compatible = "amd,s29gl256n", "cfi-flash";
  151. bank-width = <2>;
  152. reg = <0 000000 4000000>;
  153. #address-cells = <1>;
  154. #size-cells = <1>;
  155. partition@0 {
  156. label = "Kernel";
  157. reg = <0 180000>;
  158. };
  159. partition@180000 {
  160. label = "ramdisk";
  161. reg = <180000 200000>;
  162. };
  163. partition@380000 {
  164. label = "file system";
  165. reg = <380000 3aa0000>;
  166. };
  167. partition@3e20000 {
  168. label = "kozio";
  169. reg = <3e20000 140000>;
  170. };
  171. partition@3f60000 {
  172. label = "env";
  173. reg = <3f60000 40000>;
  174. };
  175. partition@3fa0000 {
  176. label = "u-boot";
  177. reg = <3fa0000 60000>;
  178. };
  179. };
  180. };
  181. UART0: serial@ef600300 {
  182. device_type = "serial";
  183. compatible = "ns16550";
  184. reg = <ef600300 8>;
  185. virtual-reg = <ef600300>;
  186. clock-frequency = <0>; /* Filled in by zImage */
  187. current-speed = <1c200>;
  188. interrupt-parent = <&UIC0>;
  189. interrupts = <0 4>;
  190. };
  191. UART1: serial@ef600400 {
  192. device_type = "serial";
  193. compatible = "ns16550";
  194. reg = <ef600400 8>;
  195. virtual-reg = <ef600400>;
  196. clock-frequency = <0>;
  197. current-speed = <0>;
  198. interrupt-parent = <&UIC0>;
  199. interrupts = <1 4>;
  200. };
  201. UART2: serial@ef600500 {
  202. device_type = "serial";
  203. compatible = "ns16550";
  204. reg = <ef600500 8>;
  205. virtual-reg = <ef600500>;
  206. clock-frequency = <0>;
  207. current-speed = <0>;
  208. interrupt-parent = <&UIC1>;
  209. interrupts = <3 4>;
  210. };
  211. UART3: serial@ef600600 {
  212. device_type = "serial";
  213. compatible = "ns16550";
  214. reg = <ef600600 8>;
  215. virtual-reg = <ef600600>;
  216. clock-frequency = <0>;
  217. current-speed = <0>;
  218. interrupt-parent = <&UIC1>;
  219. interrupts = <4 4>;
  220. };
  221. IIC0: i2c@ef600700 {
  222. compatible = "ibm,iic-440epx", "ibm,iic";
  223. reg = <ef600700 14>;
  224. interrupt-parent = <&UIC0>;
  225. interrupts = <2 4>;
  226. };
  227. IIC1: i2c@ef600800 {
  228. compatible = "ibm,iic-440epx", "ibm,iic";
  229. reg = <ef600800 14>;
  230. interrupt-parent = <&UIC0>;
  231. interrupts = <7 4>;
  232. };
  233. ZMII0: emac-zmii@ef600d00 {
  234. compatible = "ibm,zmii-440epx", "ibm,zmii";
  235. reg = <ef600d00 c>;
  236. };
  237. RGMII0: emac-rgmii@ef601000 {
  238. compatible = "ibm,rgmii-440epx", "ibm,rgmii";
  239. reg = <ef601000 8>;
  240. has-mdio;
  241. };
  242. EMAC0: ethernet@ef600e00 {
  243. device_type = "network";
  244. compatible = "ibm,emac-440epx", "ibm,emac4";
  245. interrupt-parent = <&EMAC0>;
  246. interrupts = <0 1>;
  247. #interrupt-cells = <1>;
  248. #address-cells = <0>;
  249. #size-cells = <0>;
  250. interrupt-map = </*Status*/ 0 &UIC0 18 4
  251. /*Wake*/ 1 &UIC1 1d 4>;
  252. reg = <ef600e00 70>;
  253. local-mac-address = [000000000000];
  254. mal-device = <&MAL0>;
  255. mal-tx-channel = <0>;
  256. mal-rx-channel = <0>;
  257. cell-index = <0>;
  258. max-frame-size = <2328>;
  259. rx-fifo-size = <1000>;
  260. tx-fifo-size = <800>;
  261. phy-mode = "rgmii";
  262. phy-map = <00000000>;
  263. zmii-device = <&ZMII0>;
  264. zmii-channel = <0>;
  265. rgmii-device = <&RGMII0>;
  266. rgmii-channel = <0>;
  267. has-inverted-stacr-oc;
  268. has-new-stacr-staopc;
  269. };
  270. EMAC1: ethernet@ef600f00 {
  271. device_type = "network";
  272. compatible = "ibm,emac-440epx", "ibm,emac4";
  273. interrupt-parent = <&EMAC1>;
  274. interrupts = <0 1>;
  275. #interrupt-cells = <1>;
  276. #address-cells = <0>;
  277. #size-cells = <0>;
  278. interrupt-map = </*Status*/ 0 &UIC0 19 4
  279. /*Wake*/ 1 &UIC1 1f 4>;
  280. reg = <ef600f00 70>;
  281. local-mac-address = [000000000000];
  282. mal-device = <&MAL0>;
  283. mal-tx-channel = <1>;
  284. mal-rx-channel = <1>;
  285. cell-index = <1>;
  286. max-frame-size = <2328>;
  287. rx-fifo-size = <1000>;
  288. tx-fifo-size = <800>;
  289. phy-mode = "rgmii";
  290. phy-map = <00000000>;
  291. zmii-device = <&ZMII0>;
  292. zmii-channel = <1>;
  293. rgmii-device = <&RGMII0>;
  294. rgmii-channel = <1>;
  295. has-inverted-stacr-oc;
  296. has-new-stacr-staopc;
  297. };
  298. };
  299. PCI0: pci@1ec000000 {
  300. device_type = "pci";
  301. #interrupt-cells = <1>;
  302. #size-cells = <2>;
  303. #address-cells = <3>;
  304. compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
  305. primary;
  306. reg = <1 eec00000 8 /* Config space access */
  307. 1 eed00000 4 /* IACK */
  308. 1 eed00000 4 /* Special cycle */
  309. 1 ef400000 40>; /* Internal registers */
  310. /* Outbound ranges, one memory and one IO,
  311. * later cannot be changed. Chip supports a second
  312. * IO range but we don't use it for now
  313. */
  314. ranges = <02000000 0 80000000 1 80000000 0 10000000
  315. 01000000 0 00000000 1 e8000000 0 00100000>;
  316. /* Inbound 2GB range starting at 0 */
  317. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  318. /* All PCI interrupts are routed to IRQ 67 */
  319. interrupt-map-mask = <0000 0 0 0>;
  320. interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
  321. };
  322. };
  323. chosen {
  324. linux,stdout-path = "/plb/opb/serial@ef600300";
  325. bootargs = "console=ttyS0,115200";
  326. };
  327. };