mpc8377_mds.dts 7.5 KB

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  1. /*
  2. * MPC8377E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8377emds";
  14. compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8377@0 {
  28. device_type = "cpu";
  29. reg = <0x0>;
  30. d-cache-line-size = <32>;
  31. i-cache-line-size = <32>;
  32. d-cache-size = <32768>;
  33. i-cache-size = <32768>;
  34. timebase-frequency = <0>;
  35. bus-frequency = <0>;
  36. clock-frequency = <0>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x20000000>; // 512MB at 0
  42. };
  43. localbus@e0005000 {
  44. #address-cells = <2>;
  45. #size-cells = <1>;
  46. compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
  47. reg = <0xe0005000 0x1000>;
  48. interrupts = <77 0x8>;
  49. interrupt-parent = <&ipic>;
  50. // booting from NOR flash
  51. ranges = <0 0x0 0xfe000000 0x02000000
  52. 1 0x0 0xf8000000 0x00008000
  53. 3 0x0 0xe0600000 0x00008000>;
  54. flash@0,0 {
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. compatible = "cfi-flash";
  58. reg = <0 0x0 0x2000000>;
  59. bank-width = <2>;
  60. device-width = <1>;
  61. u-boot@0 {
  62. reg = <0x0 0x100000>;
  63. read-only;
  64. };
  65. fs@100000 {
  66. reg = <0x100000 0x800000>;
  67. };
  68. kernel@1d00000 {
  69. reg = <0x1d00000 0x200000>;
  70. };
  71. dtb@1f00000 {
  72. reg = <0x1f00000 0x100000>;
  73. };
  74. };
  75. bcsr@1,0 {
  76. reg = <1 0x0 0x8000>;
  77. compatible = "fsl,mpc837xmds-bcsr";
  78. };
  79. nand@3,0 {
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. compatible = "fsl,mpc8377-fcm-nand",
  83. "fsl,elbc-fcm-nand";
  84. reg = <3 0x0 0x8000>;
  85. u-boot@0 {
  86. reg = <0x0 0x100000>;
  87. read-only;
  88. };
  89. kernel@100000 {
  90. reg = <0x100000 0x300000>;
  91. };
  92. fs@400000 {
  93. reg = <0x400000 0x1c00000>;
  94. };
  95. };
  96. };
  97. soc@e0000000 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. device_type = "soc";
  101. ranges = <0x0 0xe0000000 0x00100000>;
  102. reg = <0xe0000000 0x00000200>;
  103. bus-frequency = <0>;
  104. wdt@200 {
  105. compatible = "mpc83xx_wdt";
  106. reg = <0x200 0x100>;
  107. };
  108. i2c@3000 {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. cell-index = <0>;
  112. compatible = "fsl-i2c";
  113. reg = <0x3000 0x100>;
  114. interrupts = <14 0x8>;
  115. interrupt-parent = <&ipic>;
  116. dfsrr;
  117. };
  118. i2c@3100 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. cell-index = <1>;
  122. compatible = "fsl-i2c";
  123. reg = <0x3100 0x100>;
  124. interrupts = <15 0x8>;
  125. interrupt-parent = <&ipic>;
  126. dfsrr;
  127. };
  128. spi@7000 {
  129. cell-index = <0>;
  130. compatible = "fsl,spi";
  131. reg = <0x7000 0x1000>;
  132. interrupts = <16 0x8>;
  133. interrupt-parent = <&ipic>;
  134. mode = "cpu";
  135. };
  136. usb@23000 {
  137. compatible = "fsl-usb2-dr";
  138. reg = <0x23000 0x1000>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. interrupt-parent = <&ipic>;
  142. interrupts = <38 0x8>;
  143. dr_mode = "host";
  144. phy_type = "ulpi";
  145. };
  146. mdio@24520 {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. compatible = "fsl,gianfar-mdio";
  150. reg = <0x24520 0x20>;
  151. phy2: ethernet-phy@2 {
  152. interrupt-parent = <&ipic>;
  153. interrupts = <17 0x8>;
  154. reg = <0x2>;
  155. device_type = "ethernet-phy";
  156. };
  157. phy3: ethernet-phy@3 {
  158. interrupt-parent = <&ipic>;
  159. interrupts = <18 0x8>;
  160. reg = <0x3>;
  161. device_type = "ethernet-phy";
  162. };
  163. };
  164. enet0: ethernet@24000 {
  165. cell-index = <0>;
  166. device_type = "network";
  167. model = "eTSEC";
  168. compatible = "gianfar";
  169. reg = <0x24000 0x1000>;
  170. local-mac-address = [ 00 00 00 00 00 00 ];
  171. interrupts = <32 0x8 33 0x8 34 0x8>;
  172. phy-connection-type = "mii";
  173. interrupt-parent = <&ipic>;
  174. phy-handle = <&phy2>;
  175. };
  176. enet1: ethernet@25000 {
  177. cell-index = <1>;
  178. device_type = "network";
  179. model = "eTSEC";
  180. compatible = "gianfar";
  181. reg = <0x25000 0x1000>;
  182. local-mac-address = [ 00 00 00 00 00 00 ];
  183. interrupts = <35 0x8 36 0x8 37 0x8>;
  184. phy-connection-type = "mii";
  185. interrupt-parent = <&ipic>;
  186. phy-handle = <&phy3>;
  187. };
  188. serial0: serial@4500 {
  189. cell-index = <0>;
  190. device_type = "serial";
  191. compatible = "ns16550";
  192. reg = <0x4500 0x100>;
  193. clock-frequency = <0>;
  194. interrupts = <9 0x8>;
  195. interrupt-parent = <&ipic>;
  196. };
  197. serial1: serial@4600 {
  198. cell-index = <1>;
  199. device_type = "serial";
  200. compatible = "ns16550";
  201. reg = <0x4600 0x100>;
  202. clock-frequency = <0>;
  203. interrupts = <10 0x8>;
  204. interrupt-parent = <&ipic>;
  205. };
  206. crypto@30000 {
  207. model = "SEC3";
  208. compatible = "talitos";
  209. reg = <0x30000 0x10000>;
  210. interrupts = <11 0x8>;
  211. interrupt-parent = <&ipic>;
  212. /* Rev. 3.0 geometry */
  213. num-channels = <4>;
  214. channel-fifo-len = <24>;
  215. exec-units-mask = <0x000001fe>;
  216. descriptor-types-mask = <0x03ab0ebf>;
  217. };
  218. sdhc@2e000 {
  219. model = "eSDHC";
  220. compatible = "fsl,esdhc";
  221. reg = <0x2e000 0x1000>;
  222. interrupts = <42 0x8>;
  223. interrupt-parent = <&ipic>;
  224. };
  225. sata@18000 {
  226. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  227. reg = <0x18000 0x1000>;
  228. interrupts = <44 0x8>;
  229. interrupt-parent = <&ipic>;
  230. };
  231. sata@19000 {
  232. compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
  233. reg = <0x19000 0x1000>;
  234. interrupts = <45 0x8>;
  235. interrupt-parent = <&ipic>;
  236. };
  237. /* IPIC
  238. * interrupts cell = <intr #, sense>
  239. * sense values match linux IORESOURCE_IRQ_* defines:
  240. * sense == 8: Level, low assertion
  241. * sense == 2: Edge, high-to-low change
  242. */
  243. ipic: pic@700 {
  244. compatible = "fsl,ipic";
  245. interrupt-controller;
  246. #address-cells = <0>;
  247. #interrupt-cells = <2>;
  248. reg = <0x700 0x100>;
  249. };
  250. };
  251. pci0: pci@e0008500 {
  252. cell-index = <0>;
  253. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  254. interrupt-map = <
  255. /* IDSEL 0x11 */
  256. 0x8800 0x0 0x0 0x1 &ipic 20 0x8
  257. 0x8800 0x0 0x0 0x2 &ipic 21 0x8
  258. 0x8800 0x0 0x0 0x3 &ipic 22 0x8
  259. 0x8800 0x0 0x0 0x4 &ipic 23 0x8
  260. /* IDSEL 0x12 */
  261. 0x9000 0x0 0x0 0x1 &ipic 22 0x8
  262. 0x9000 0x0 0x0 0x2 &ipic 23 0x8
  263. 0x9000 0x0 0x0 0x3 &ipic 20 0x8
  264. 0x9000 0x0 0x0 0x4 &ipic 21 0x8
  265. /* IDSEL 0x13 */
  266. 0x9800 0x0 0x0 0x1 &ipic 23 0x8
  267. 0x9800 0x0 0x0 0x2 &ipic 20 0x8
  268. 0x9800 0x0 0x0 0x3 &ipic 21 0x8
  269. 0x9800 0x0 0x0 0x4 &ipic 22 0x8
  270. /* IDSEL 0x15 */
  271. 0xa800 0x0 0x0 0x1 &ipic 20 0x8
  272. 0xa800 0x0 0x0 0x2 &ipic 21 0x8
  273. 0xa800 0x0 0x0 0x3 &ipic 22 0x8
  274. 0xa800 0x0 0x0 0x4 &ipic 23 0x8
  275. /* IDSEL 0x16 */
  276. 0xb000 0x0 0x0 0x1 &ipic 23 0x8
  277. 0xb000 0x0 0x0 0x2 &ipic 20 0x8
  278. 0xb000 0x0 0x0 0x3 &ipic 21 0x8
  279. 0xb000 0x0 0x0 0x4 &ipic 22 0x8
  280. /* IDSEL 0x17 */
  281. 0xb800 0x0 0x0 0x1 &ipic 22 0x8
  282. 0xb800 0x0 0x0 0x2 &ipic 23 0x8
  283. 0xb800 0x0 0x0 0x3 &ipic 20 0x8
  284. 0xb800 0x0 0x0 0x4 &ipic 21 0x8
  285. /* IDSEL 0x18 */
  286. 0xc000 0x0 0x0 0x1 &ipic 21 0x8
  287. 0xc000 0x0 0x0 0x2 &ipic 22 0x8
  288. 0xc000 0x0 0x0 0x3 &ipic 23 0x8
  289. 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
  290. interrupt-parent = <&ipic>;
  291. interrupts = <66 0x8>;
  292. bus-range = <0x0 0x0>;
  293. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  294. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  295. 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
  296. clock-frequency = <0>;
  297. #interrupt-cells = <1>;
  298. #size-cells = <2>;
  299. #address-cells = <3>;
  300. reg = <0xe0008500 0x100>;
  301. compatible = "fsl,mpc8349-pci";
  302. device_type = "pci";
  303. };
  304. };