mpc8349emitxgp.dts 4.3 KB

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  1. /*
  2. * MPC8349E-mITX-GP Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITXGP";
  14. compatible = "MPC8349EMITXGP", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8349@0 {
  27. device_type = "cpu";
  28. reg = <0x0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>;
  41. };
  42. soc8349@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. ranges = <0x0 0xe0000000 0x00100000>;
  47. reg = <0xe0000000 0x00000200>;
  48. bus-frequency = <0>; // from bootloader
  49. wdt@200 {
  50. device_type = "watchdog";
  51. compatible = "mpc83xx_wdt";
  52. reg = <0x200 0x100>;
  53. };
  54. i2c@3000 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. cell-index = <0>;
  58. compatible = "fsl-i2c";
  59. reg = <0x3000 0x100>;
  60. interrupts = <14 0x8>;
  61. interrupt-parent = <&ipic>;
  62. dfsrr;
  63. };
  64. i2c@3100 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. cell-index = <1>;
  68. compatible = "fsl-i2c";
  69. reg = <0x3100 0x100>;
  70. interrupts = <15 0x8>;
  71. interrupt-parent = <&ipic>;
  72. dfsrr;
  73. };
  74. spi@7000 {
  75. cell-index = <0>;
  76. compatible = "fsl,spi";
  77. reg = <0x7000 0x1000>;
  78. interrupts = <16 0x8>;
  79. interrupt-parent = <&ipic>;
  80. mode = "cpu";
  81. };
  82. usb@23000 {
  83. compatible = "fsl-usb2-dr";
  84. reg = <0x23000 0x1000>;
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. interrupt-parent = <&ipic>;
  88. interrupts = <38 0x8>;
  89. dr_mode = "otg";
  90. phy_type = "ulpi";
  91. };
  92. mdio@24520 {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. compatible = "fsl,gianfar-mdio";
  96. reg = <0x24520 0x20>;
  97. /* Vitesse 8201 */
  98. phy1c: ethernet-phy@1c {
  99. interrupt-parent = <&ipic>;
  100. interrupts = <18 0x8>;
  101. reg = <0x1c>;
  102. device_type = "ethernet-phy";
  103. };
  104. };
  105. enet0: ethernet@24000 {
  106. cell-index = <0>;
  107. device_type = "network";
  108. model = "TSEC";
  109. compatible = "gianfar";
  110. reg = <0x24000 0x1000>;
  111. local-mac-address = [ 00 00 00 00 00 00 ];
  112. interrupts = <32 0x8 33 0x8 34 0x8>;
  113. interrupt-parent = <&ipic>;
  114. phy-handle = <&phy1c>;
  115. linux,network-index = <0>;
  116. };
  117. serial0: serial@4500 {
  118. cell-index = <0>;
  119. device_type = "serial";
  120. compatible = "ns16550";
  121. reg = <0x4500 0x100>;
  122. clock-frequency = <0>; // from bootloader
  123. interrupts = <9 0x8>;
  124. interrupt-parent = <&ipic>;
  125. };
  126. serial1: serial@4600 {
  127. cell-index = <1>;
  128. device_type = "serial";
  129. compatible = "ns16550";
  130. reg = <0x4600 0x100>;
  131. clock-frequency = <0>; // from bootloader
  132. interrupts = <10 0x8>;
  133. interrupt-parent = <&ipic>;
  134. };
  135. crypto@30000 {
  136. device_type = "crypto";
  137. model = "SEC2";
  138. compatible = "talitos";
  139. reg = <0x30000 0x10000>;
  140. interrupts = <11 0x8>;
  141. interrupt-parent = <&ipic>;
  142. num-channels = <4>;
  143. channel-fifo-len = <24>;
  144. exec-units-mask = <0x0000007e>;
  145. descriptor-types-mask = <0x01010ebf>;
  146. };
  147. ipic: pic@700 {
  148. interrupt-controller;
  149. #address-cells = <0>;
  150. #interrupt-cells = <2>;
  151. reg = <0x700 0x100>;
  152. device_type = "ipic";
  153. };
  154. };
  155. pci0: pci@e0008600 {
  156. cell-index = <2>;
  157. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  158. interrupt-map = <
  159. /* IDSEL 0x0F - PCI Slot */
  160. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  161. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  162. >;
  163. interrupt-parent = <&ipic>;
  164. interrupts = <67 0x8>;
  165. bus-range = <0x1 0x1>;
  166. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  167. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  168. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  169. clock-frequency = <66666666>;
  170. #interrupt-cells = <1>;
  171. #size-cells = <2>;
  172. #address-cells = <3>;
  173. reg = <0xe0008600 0x100>;
  174. compatible = "fsl,mpc8349-pci";
  175. device_type = "pci";
  176. };
  177. };