mpc8313erdb.dts 6.2 KB

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  1. /*
  2. * MPC8313E RDB Device Tree Source
  3. *
  4. * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8313ERDB";
  14. compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8313@0 {
  28. device_type = "cpu";
  29. reg = <0x0>;
  30. d-cache-line-size = <32>;
  31. i-cache-line-size = <32>;
  32. d-cache-size = <16384>;
  33. i-cache-size = <16384>;
  34. timebase-frequency = <0>; // from bootloader
  35. bus-frequency = <0>; // from bootloader
  36. clock-frequency = <0>; // from bootloader
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x08000000>; // 128MB at 0
  42. };
  43. localbus@e0005000 {
  44. #address-cells = <2>;
  45. #size-cells = <1>;
  46. compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
  47. reg = <0xe0005000 0x1000>;
  48. interrupts = <77 0x8>;
  49. interrupt-parent = <&ipic>;
  50. // CS0 and CS1 are swapped when
  51. // booting from nand, but the
  52. // addresses are the same.
  53. ranges = <0x0 0x0 0xfe000000 0x00800000
  54. 0x1 0x0 0xe2800000 0x00008000
  55. 0x2 0x0 0xf0000000 0x00020000
  56. 0x3 0x0 0xfa000000 0x00008000>;
  57. flash@0,0 {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. compatible = "cfi-flash";
  61. reg = <0x0 0x0 0x800000>;
  62. bank-width = <2>;
  63. device-width = <1>;
  64. };
  65. nand@1,0 {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "fsl,mpc8313-fcm-nand",
  69. "fsl,elbc-fcm-nand";
  70. reg = <0x1 0x0 0x2000>;
  71. u-boot@0 {
  72. reg = <0x0 0x100000>;
  73. read-only;
  74. };
  75. kernel@100000 {
  76. reg = <0x100000 0x300000>;
  77. };
  78. fs@400000 {
  79. reg = <0x400000 0x1c00000>;
  80. };
  81. };
  82. };
  83. soc8313@e0000000 {
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. device_type = "soc";
  87. compatible = "simple-bus";
  88. ranges = <0x0 0xe0000000 0x00100000>;
  89. reg = <0xe0000000 0x00000200>;
  90. bus-frequency = <0>;
  91. wdt@200 {
  92. device_type = "watchdog";
  93. compatible = "mpc83xx_wdt";
  94. reg = <0x200 0x100>;
  95. };
  96. i2c@3000 {
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. cell-index = <0>;
  100. compatible = "fsl-i2c";
  101. reg = <0x3000 0x100>;
  102. interrupts = <14 0x8>;
  103. interrupt-parent = <&ipic>;
  104. dfsrr;
  105. rtc@68 {
  106. compatible = "dallas,ds1339";
  107. reg = <0x68>;
  108. };
  109. };
  110. i2c@3100 {
  111. #address-cells = <1>;
  112. #size-cells = <0>;
  113. cell-index = <1>;
  114. compatible = "fsl-i2c";
  115. reg = <0x3100 0x100>;
  116. interrupts = <15 0x8>;
  117. interrupt-parent = <&ipic>;
  118. dfsrr;
  119. };
  120. spi@7000 {
  121. cell-index = <0>;
  122. compatible = "fsl,spi";
  123. reg = <0x7000 0x1000>;
  124. interrupts = <16 0x8>;
  125. interrupt-parent = <&ipic>;
  126. mode = "cpu";
  127. };
  128. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  129. usb@23000 {
  130. compatible = "fsl-usb2-dr";
  131. reg = <0x23000 0x1000>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. interrupt-parent = <&ipic>;
  135. interrupts = <38 0x8>;
  136. phy_type = "utmi_wide";
  137. };
  138. mdio@24520 {
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. compatible = "fsl,gianfar-mdio";
  142. reg = <0x24520 0x20>;
  143. phy1: ethernet-phy@1 {
  144. interrupt-parent = <&ipic>;
  145. interrupts = <19 0x8>;
  146. reg = <0x1>;
  147. device_type = "ethernet-phy";
  148. };
  149. phy4: ethernet-phy@4 {
  150. interrupt-parent = <&ipic>;
  151. interrupts = <20 0x8>;
  152. reg = <0x4>;
  153. device_type = "ethernet-phy";
  154. };
  155. };
  156. enet0: ethernet@24000 {
  157. cell-index = <0>;
  158. device_type = "network";
  159. model = "eTSEC";
  160. compatible = "gianfar";
  161. reg = <0x24000 0x1000>;
  162. local-mac-address = [ 00 00 00 00 00 00 ];
  163. interrupts = <37 0x8 36 0x8 35 0x8>;
  164. interrupt-parent = <&ipic>;
  165. phy-handle = < &phy1 >;
  166. };
  167. enet1: ethernet@25000 {
  168. cell-index = <1>;
  169. device_type = "network";
  170. model = "eTSEC";
  171. compatible = "gianfar";
  172. reg = <0x25000 0x1000>;
  173. local-mac-address = [ 00 00 00 00 00 00 ];
  174. interrupts = <34 0x8 33 0x8 32 0x8>;
  175. interrupt-parent = <&ipic>;
  176. phy-handle = < &phy4 >;
  177. };
  178. serial0: serial@4500 {
  179. cell-index = <0>;
  180. device_type = "serial";
  181. compatible = "ns16550";
  182. reg = <0x4500 0x100>;
  183. clock-frequency = <0>;
  184. interrupts = <9 0x8>;
  185. interrupt-parent = <&ipic>;
  186. };
  187. serial1: serial@4600 {
  188. cell-index = <1>;
  189. device_type = "serial";
  190. compatible = "ns16550";
  191. reg = <0x4600 0x100>;
  192. clock-frequency = <0>;
  193. interrupts = <10 0x8>;
  194. interrupt-parent = <&ipic>;
  195. };
  196. crypto@30000 {
  197. device_type = "crypto";
  198. model = "SEC2";
  199. compatible = "talitos";
  200. reg = <0x30000 0x7000>;
  201. interrupts = <11 0x8>;
  202. interrupt-parent = <&ipic>;
  203. /* Rev. 2.2 */
  204. num-channels = <1>;
  205. channel-fifo-len = <24>;
  206. exec-units-mask = <0x0000004c>;
  207. descriptor-types-mask = <0x0122003f>;
  208. };
  209. /* IPIC
  210. * interrupts cell = <intr #, sense>
  211. * sense values match linux IORESOURCE_IRQ_* defines:
  212. * sense == 8: Level, low assertion
  213. * sense == 2: Edge, high-to-low change
  214. */
  215. ipic: pic@700 {
  216. interrupt-controller;
  217. #address-cells = <0>;
  218. #interrupt-cells = <2>;
  219. reg = <0x700 0x100>;
  220. device_type = "ipic";
  221. };
  222. };
  223. pci0: pci@e0008500 {
  224. cell-index = <1>;
  225. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  226. interrupt-map = <
  227. /* IDSEL 0x0E -mini PCI */
  228. 0x7000 0x0 0x0 0x1 &ipic 18 0x8
  229. 0x7000 0x0 0x0 0x2 &ipic 18 0x8
  230. 0x7000 0x0 0x0 0x3 &ipic 18 0x8
  231. 0x7000 0x0 0x0 0x4 &ipic 18 0x8
  232. /* IDSEL 0x0F - PCI slot */
  233. 0x7800 0x0 0x0 0x1 &ipic 17 0x8
  234. 0x7800 0x0 0x0 0x2 &ipic 18 0x8
  235. 0x7800 0x0 0x0 0x3 &ipic 17 0x8
  236. 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
  237. interrupt-parent = <&ipic>;
  238. interrupts = <66 0x8>;
  239. bus-range = <0x0 0x0>;
  240. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  241. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  242. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  243. clock-frequency = <66666666>;
  244. #interrupt-cells = <1>;
  245. #size-cells = <2>;
  246. #address-cells = <3>;
  247. reg = <0xe0008500 0x100>;
  248. compatible = "fsl,mpc8349-pci";
  249. device_type = "pci";
  250. };
  251. };