gdth.c 177 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: gdth_bufflen
  87. * buffer: gdth_sglist
  88. * dma_handle: unused
  89. * buffers_residual: gdth_sg_count
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include <linux/scatterlist.h>
  127. #include "scsi.h"
  128. #include <scsi/scsi_host.h>
  129. #include "gdth.h"
  130. static void gdth_delay(int milliseconds);
  131. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  132. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  133. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  134. int gdth_from_wait, int* pIndex);
  135. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  136. Scsi_Cmnd *scp);
  137. static int gdth_async_event(gdth_ha_str *ha);
  138. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  139. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  140. static void gdth_next(gdth_ha_str *ha);
  141. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  142. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  143. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  144. ushort idx, gdth_evt_data *evt);
  145. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  146. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  147. gdth_evt_str *estr);
  148. static void gdth_clear_events(void);
  149. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  150. char *buffer, ushort count);
  151. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  152. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  153. static void gdth_enable_int(gdth_ha_str *ha);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  169. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  170. struct gdth_cmndinfo *cmndinfo);
  171. static void gdth_scsi_done(struct scsi_cmnd *scp);
  172. #ifdef DEBUG_GDTH
  173. static unchar DebugState = DEBUG_GDTH;
  174. #ifdef __SERIAL__
  175. #define MAX_SERBUF 160
  176. static void ser_init(void);
  177. static void ser_puts(char *str);
  178. static void ser_putc(char c);
  179. static int ser_printk(const char *fmt, ...);
  180. static char strbuf[MAX_SERBUF+1];
  181. #ifdef __COM2__
  182. #define COM_BASE 0x2f8
  183. #else
  184. #define COM_BASE 0x3f8
  185. #endif
  186. static void ser_init()
  187. {
  188. unsigned port=COM_BASE;
  189. outb(0x80,port+3);
  190. outb(0,port+1);
  191. /* 19200 Baud, if 9600: outb(12,port) */
  192. outb(6, port);
  193. outb(3,port+3);
  194. outb(0,port+1);
  195. /*
  196. ser_putc('I');
  197. ser_putc(' ');
  198. */
  199. }
  200. static void ser_puts(char *str)
  201. {
  202. char *ptr;
  203. ser_init();
  204. for (ptr=str;*ptr;++ptr)
  205. ser_putc(*ptr);
  206. }
  207. static void ser_putc(char c)
  208. {
  209. unsigned port=COM_BASE;
  210. while ((inb(port+5) & 0x20)==0);
  211. outb(c,port);
  212. if (c==0x0a)
  213. {
  214. while ((inb(port+5) & 0x20)==0);
  215. outb(0x0d,port);
  216. }
  217. }
  218. static int ser_printk(const char *fmt, ...)
  219. {
  220. va_list args;
  221. int i;
  222. va_start(args,fmt);
  223. i = vsprintf(strbuf,fmt,args);
  224. ser_puts(strbuf);
  225. va_end(args);
  226. return i;
  227. }
  228. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  229. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  230. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  231. #else /* !__SERIAL__ */
  232. #define TRACE(a) {if (DebugState==1) {printk a;}}
  233. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  234. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  235. #endif
  236. #else /* !DEBUG */
  237. #define TRACE(a)
  238. #define TRACE2(a)
  239. #define TRACE3(a)
  240. #endif
  241. #ifdef GDTH_STATISTICS
  242. static ulong32 max_rq=0, max_index=0, max_sg=0;
  243. #ifdef INT_COAL
  244. static ulong32 max_int_coal=0;
  245. #endif
  246. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  247. static struct timer_list gdth_timer;
  248. #endif
  249. #define PTR2USHORT(a) (ushort)(ulong)(a)
  250. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  251. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  252. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  253. #ifdef CONFIG_ISA
  254. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  255. #endif
  256. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  257. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  258. #endif
  259. static unchar gdth_polling; /* polling if TRUE */
  260. static int gdth_ctr_count = 0; /* controller count */
  261. static LIST_HEAD(gdth_instances); /* controller list */
  262. static unchar gdth_write_through = FALSE; /* write through */
  263. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  264. static int elastidx;
  265. static int eoldidx;
  266. static int major;
  267. #define DIN 1 /* IN data direction */
  268. #define DOU 2 /* OUT data direction */
  269. #define DNO DIN /* no data transfer */
  270. #define DUN DIN /* unknown data direction */
  271. static unchar gdth_direction_tab[0x100] = {
  272. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  273. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  274. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  275. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  276. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  277. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  283. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  288. };
  289. /* LILO and modprobe/insmod parameters */
  290. /* IRQ list for GDT3000/3020 EISA controllers */
  291. static int irq[MAXHA] __initdata =
  292. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  293. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  294. /* disable driver flag */
  295. static int disable __initdata = 0;
  296. /* reserve flag */
  297. static int reserve_mode = 1;
  298. /* reserve list */
  299. static int reserve_list[MAX_RES_ARGS] =
  300. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  301. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  303. /* scan order for PCI controllers */
  304. static int reverse_scan = 0;
  305. /* virtual channel for the host drives */
  306. static int hdr_channel = 0;
  307. /* max. IDs per channel */
  308. static int max_ids = MAXID;
  309. /* rescan all IDs */
  310. static int rescan = 0;
  311. /* shared access */
  312. static int shared_access = 1;
  313. /* enable support for EISA and ISA controllers */
  314. static int probe_eisa_isa = 0;
  315. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  316. static int force_dma32 = 0;
  317. /* parameters for modprobe/insmod */
  318. module_param_array(irq, int, NULL, 0);
  319. module_param(disable, int, 0);
  320. module_param(reserve_mode, int, 0);
  321. module_param_array(reserve_list, int, NULL, 0);
  322. module_param(reverse_scan, int, 0);
  323. module_param(hdr_channel, int, 0);
  324. module_param(max_ids, int, 0);
  325. module_param(rescan, int, 0);
  326. module_param(shared_access, int, 0);
  327. module_param(probe_eisa_isa, int, 0);
  328. module_param(force_dma32, int, 0);
  329. MODULE_AUTHOR("Achim Leubner");
  330. MODULE_LICENSE("GPL");
  331. /* ioctl interface */
  332. static const struct file_operations gdth_fops = {
  333. .ioctl = gdth_ioctl,
  334. .open = gdth_open,
  335. .release = gdth_close,
  336. };
  337. /*
  338. * gdth scsi_command access wrappers.
  339. * below 6 functions are used throughout the driver to access scsi_command's
  340. * io parameters. The reason we do not use the regular accessors from
  341. * scsi_cmnd.h is because of gdth_execute(). Since it is unrecommended for
  342. * llds to directly set scsi_cmnd's IO members. This driver will use SCp
  343. * members for IO parameters, and will copy scsi_cmnd's members to Scp
  344. * members in queuecommand. For internal commands through gdth_execute()
  345. * SCp's members will be set directly.
  346. */
  347. static inline unsigned gdth_bufflen(struct scsi_cmnd *cmd)
  348. {
  349. return (unsigned)cmd->SCp.this_residual;
  350. }
  351. static inline void gdth_set_bufflen(struct scsi_cmnd *cmd, unsigned bufflen)
  352. {
  353. cmd->SCp.this_residual = bufflen;
  354. }
  355. static inline unsigned gdth_sg_count(struct scsi_cmnd *cmd)
  356. {
  357. return (unsigned)cmd->SCp.buffers_residual;
  358. }
  359. static inline void gdth_set_sg_count(struct scsi_cmnd *cmd, unsigned sg_count)
  360. {
  361. cmd->SCp.buffers_residual = sg_count;
  362. }
  363. static inline struct scatterlist *gdth_sglist(struct scsi_cmnd *cmd)
  364. {
  365. return cmd->SCp.buffer;
  366. }
  367. static inline void gdth_set_sglist(struct scsi_cmnd *cmd,
  368. struct scatterlist *sglist)
  369. {
  370. cmd->SCp.buffer = sglist;
  371. }
  372. #include "gdth_proc.h"
  373. #include "gdth_proc.c"
  374. static gdth_ha_str *gdth_find_ha(int hanum)
  375. {
  376. gdth_ha_str *ha;
  377. list_for_each_entry(ha, &gdth_instances, list)
  378. if (hanum == ha->hanum)
  379. return ha;
  380. return NULL;
  381. }
  382. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  383. {
  384. struct gdth_cmndinfo *priv = NULL;
  385. ulong flags;
  386. int i;
  387. spin_lock_irqsave(&ha->smp_lock, flags);
  388. for (i=0; i<GDTH_MAXCMDS; ++i) {
  389. if (ha->cmndinfo[i].index == 0) {
  390. priv = &ha->cmndinfo[i];
  391. memset(priv, 0, sizeof(*priv));
  392. priv->index = i+1;
  393. break;
  394. }
  395. }
  396. spin_unlock_irqrestore(&ha->smp_lock, flags);
  397. return priv;
  398. }
  399. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  400. {
  401. BUG_ON(!priv);
  402. priv->index = 0;
  403. }
  404. static void gdth_delay(int milliseconds)
  405. {
  406. if (milliseconds == 0) {
  407. udelay(1);
  408. } else {
  409. mdelay(milliseconds);
  410. }
  411. }
  412. static void gdth_scsi_done(struct scsi_cmnd *scp)
  413. {
  414. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  415. int internal_command = cmndinfo->internal_command;
  416. TRACE2(("gdth_scsi_done()\n"));
  417. gdth_put_cmndinfo(cmndinfo);
  418. scp->host_scribble = NULL;
  419. if (internal_command)
  420. complete((struct completion *)scp->request);
  421. else
  422. scp->scsi_done(scp);
  423. }
  424. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  425. int timeout, u32 *info)
  426. {
  427. gdth_ha_str *ha = shost_priv(sdev->host);
  428. Scsi_Cmnd *scp;
  429. struct gdth_cmndinfo cmndinfo;
  430. DECLARE_COMPLETION_ONSTACK(wait);
  431. int rval;
  432. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  433. if (!scp)
  434. return -ENOMEM;
  435. scp->device = sdev;
  436. memset(&cmndinfo, 0, sizeof(cmndinfo));
  437. /* use request field to save the ptr. to completion struct. */
  438. scp->request = (struct request *)&wait;
  439. scp->timeout_per_command = timeout*HZ;
  440. scp->cmd_len = 12;
  441. memcpy(scp->cmnd, cmnd, 12);
  442. cmndinfo.priority = IOCTL_PRI;
  443. cmndinfo.internal_cmd_str = gdtcmd;
  444. cmndinfo.internal_command = 1;
  445. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  446. __gdth_queuecommand(ha, scp, &cmndinfo);
  447. wait_for_completion(&wait);
  448. rval = cmndinfo.status;
  449. if (info)
  450. *info = cmndinfo.info;
  451. kfree(scp);
  452. return rval;
  453. }
  454. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  455. int timeout, u32 *info)
  456. {
  457. struct scsi_device *sdev = scsi_get_host_dev(shost);
  458. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  459. scsi_free_host_dev(sdev);
  460. return rval;
  461. }
  462. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  463. {
  464. *cyls = size /HEADS/SECS;
  465. if (*cyls <= MAXCYLS) {
  466. *heads = HEADS;
  467. *secs = SECS;
  468. } else { /* too high for 64*32 */
  469. *cyls = size /MEDHEADS/MEDSECS;
  470. if (*cyls <= MAXCYLS) {
  471. *heads = MEDHEADS;
  472. *secs = MEDSECS;
  473. } else { /* too high for 127*63 */
  474. *cyls = size /BIGHEADS/BIGSECS;
  475. *heads = BIGHEADS;
  476. *secs = BIGSECS;
  477. }
  478. }
  479. }
  480. /* controller search and initialization functions */
  481. #ifdef CONFIG_EISA
  482. static int __init gdth_search_eisa(ushort eisa_adr)
  483. {
  484. ulong32 id;
  485. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  486. id = inl(eisa_adr+ID0REG);
  487. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  488. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  489. return 0; /* not EISA configured */
  490. return 1;
  491. }
  492. if (id == GDT3_ID) /* GDT3000 */
  493. return 1;
  494. return 0;
  495. }
  496. #endif /* CONFIG_EISA */
  497. #ifdef CONFIG_ISA
  498. static int __init gdth_search_isa(ulong32 bios_adr)
  499. {
  500. void __iomem *addr;
  501. ulong32 id;
  502. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  503. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  504. id = readl(addr);
  505. iounmap(addr);
  506. if (id == GDT2_ID) /* GDT2000 */
  507. return 1;
  508. }
  509. return 0;
  510. }
  511. #endif /* CONFIG_ISA */
  512. #ifdef CONFIG_PCI
  513. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  514. ushort vendor, ushort dev);
  515. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  516. {
  517. ushort device, cnt;
  518. TRACE(("gdth_search_pci()\n"));
  519. cnt = 0;
  520. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  521. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  522. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  523. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  524. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  525. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  526. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  527. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  528. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  529. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  530. PCI_DEVICE_ID_INTEL_SRC);
  531. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  532. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  533. return cnt;
  534. }
  535. /* Vortex only makes RAID controllers.
  536. * We do not really want to specify all 550 ids here, so wildcard match.
  537. */
  538. static struct pci_device_id gdthtable[] __maybe_unused = {
  539. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  540. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  541. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  542. {0}
  543. };
  544. MODULE_DEVICE_TABLE(pci,gdthtable);
  545. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  546. ushort vendor, ushort device)
  547. {
  548. ulong base0, base1, base2;
  549. struct pci_dev *pdev;
  550. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  551. *cnt, vendor, device));
  552. pdev = NULL;
  553. while ((pdev = pci_get_device(vendor, device, pdev))
  554. != NULL) {
  555. if (pci_enable_device(pdev))
  556. continue;
  557. if (*cnt >= MAXHA) {
  558. pci_dev_put(pdev);
  559. return;
  560. }
  561. /* GDT PCI controller found, resources are already in pdev */
  562. pcistr[*cnt].pdev = pdev;
  563. pcistr[*cnt].irq = pdev->irq;
  564. base0 = pci_resource_flags(pdev, 0);
  565. base1 = pci_resource_flags(pdev, 1);
  566. base2 = pci_resource_flags(pdev, 2);
  567. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  568. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  569. if (!(base0 & IORESOURCE_MEM))
  570. continue;
  571. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  572. } else { /* GDT6110, GDT6120, .. */
  573. if (!(base0 & IORESOURCE_MEM) ||
  574. !(base2 & IORESOURCE_MEM) ||
  575. !(base1 & IORESOURCE_IO))
  576. continue;
  577. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  578. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  579. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  580. }
  581. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  582. pcistr[*cnt].pdev->bus->number,
  583. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  584. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  585. (*cnt)++;
  586. }
  587. }
  588. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  589. {
  590. gdth_pci_str temp;
  591. int i, changed;
  592. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  593. if (cnt == 0)
  594. return;
  595. do {
  596. changed = FALSE;
  597. for (i = 0; i < cnt-1; ++i) {
  598. if (!reverse_scan) {
  599. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  600. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  601. PCI_SLOT(pcistr[i].pdev->devfn) >
  602. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  603. temp = pcistr[i];
  604. pcistr[i] = pcistr[i+1];
  605. pcistr[i+1] = temp;
  606. changed = TRUE;
  607. }
  608. } else {
  609. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  610. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  611. PCI_SLOT(pcistr[i].pdev->devfn) <
  612. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  613. temp = pcistr[i];
  614. pcistr[i] = pcistr[i+1];
  615. pcistr[i+1] = temp;
  616. changed = TRUE;
  617. }
  618. }
  619. }
  620. } while (changed);
  621. }
  622. #endif /* CONFIG_PCI */
  623. #ifdef CONFIG_EISA
  624. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  625. {
  626. ulong32 retries,id;
  627. unchar prot_ver,eisacf,i,irq_found;
  628. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  629. /* disable board interrupts, deinitialize services */
  630. outb(0xff,eisa_adr+EDOORREG);
  631. outb(0x00,eisa_adr+EDENABREG);
  632. outb(0x00,eisa_adr+EINTENABREG);
  633. outb(0xff,eisa_adr+LDOORREG);
  634. retries = INIT_RETRIES;
  635. gdth_delay(20);
  636. while (inb(eisa_adr+EDOORREG) != 0xff) {
  637. if (--retries == 0) {
  638. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  639. return 0;
  640. }
  641. gdth_delay(1);
  642. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  643. }
  644. prot_ver = inb(eisa_adr+MAILBOXREG);
  645. outb(0xff,eisa_adr+EDOORREG);
  646. if (prot_ver != PROTOCOL_VERSION) {
  647. printk("GDT-EISA: Illegal protocol version\n");
  648. return 0;
  649. }
  650. ha->bmic = eisa_adr;
  651. ha->brd_phys = (ulong32)eisa_adr >> 12;
  652. outl(0,eisa_adr+MAILBOXREG);
  653. outl(0,eisa_adr+MAILBOXREG+4);
  654. outl(0,eisa_adr+MAILBOXREG+8);
  655. outl(0,eisa_adr+MAILBOXREG+12);
  656. /* detect IRQ */
  657. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  658. ha->oem_id = OEM_ID_ICP;
  659. ha->type = GDT_EISA;
  660. ha->stype = id;
  661. outl(1,eisa_adr+MAILBOXREG+8);
  662. outb(0xfe,eisa_adr+LDOORREG);
  663. retries = INIT_RETRIES;
  664. gdth_delay(20);
  665. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  666. if (--retries == 0) {
  667. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  668. return 0;
  669. }
  670. gdth_delay(1);
  671. }
  672. ha->irq = inb(eisa_adr+MAILBOXREG);
  673. outb(0xff,eisa_adr+EDOORREG);
  674. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  675. /* check the result */
  676. if (ha->irq == 0) {
  677. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  678. for (i = 0, irq_found = FALSE;
  679. i < MAXHA && irq[i] != 0xff; ++i) {
  680. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  681. irq_found = TRUE;
  682. break;
  683. }
  684. }
  685. if (irq_found) {
  686. ha->irq = irq[i];
  687. irq[i] = 0;
  688. printk("GDT-EISA: Can not detect controller IRQ,\n");
  689. printk("Use IRQ setting from command line (IRQ = %d)\n",
  690. ha->irq);
  691. } else {
  692. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  693. printk("the controller BIOS or use command line parameters\n");
  694. return 0;
  695. }
  696. }
  697. } else {
  698. eisacf = inb(eisa_adr+EISAREG) & 7;
  699. if (eisacf > 4) /* level triggered */
  700. eisacf -= 4;
  701. ha->irq = gdth_irq_tab[eisacf];
  702. ha->oem_id = OEM_ID_ICP;
  703. ha->type = GDT_EISA;
  704. ha->stype = id;
  705. }
  706. ha->dma64_support = 0;
  707. return 1;
  708. }
  709. #endif /* CONFIG_EISA */
  710. #ifdef CONFIG_ISA
  711. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  712. {
  713. register gdt2_dpram_str __iomem *dp2_ptr;
  714. int i;
  715. unchar irq_drq,prot_ver;
  716. ulong32 retries;
  717. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  718. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  719. if (ha->brd == NULL) {
  720. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  721. return 0;
  722. }
  723. dp2_ptr = ha->brd;
  724. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  725. /* reset interface area */
  726. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  727. if (readl(&dp2_ptr->u) != 0) {
  728. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  729. iounmap(ha->brd);
  730. return 0;
  731. }
  732. /* disable board interrupts, read DRQ and IRQ */
  733. writeb(0xff, &dp2_ptr->io.irqdel);
  734. writeb(0x00, &dp2_ptr->io.irqen);
  735. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  736. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  737. irq_drq = readb(&dp2_ptr->io.rq);
  738. for (i=0; i<3; ++i) {
  739. if ((irq_drq & 1)==0)
  740. break;
  741. irq_drq >>= 1;
  742. }
  743. ha->drq = gdth_drq_tab[i];
  744. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  745. for (i=1; i<5; ++i) {
  746. if ((irq_drq & 1)==0)
  747. break;
  748. irq_drq >>= 1;
  749. }
  750. ha->irq = gdth_irq_tab[i];
  751. /* deinitialize services */
  752. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  753. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  754. writeb(0, &dp2_ptr->io.event);
  755. retries = INIT_RETRIES;
  756. gdth_delay(20);
  757. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  758. if (--retries == 0) {
  759. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  760. iounmap(ha->brd);
  761. return 0;
  762. }
  763. gdth_delay(1);
  764. }
  765. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  766. writeb(0, &dp2_ptr->u.ic.Status);
  767. writeb(0xff, &dp2_ptr->io.irqdel);
  768. if (prot_ver != PROTOCOL_VERSION) {
  769. printk("GDT-ISA: Illegal protocol version\n");
  770. iounmap(ha->brd);
  771. return 0;
  772. }
  773. ha->oem_id = OEM_ID_ICP;
  774. ha->type = GDT_ISA;
  775. ha->ic_all_size = sizeof(dp2_ptr->u);
  776. ha->stype= GDT2_ID;
  777. ha->brd_phys = bios_adr >> 4;
  778. /* special request to controller BIOS */
  779. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  780. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  781. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  782. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  783. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  784. writeb(0, &dp2_ptr->io.event);
  785. retries = INIT_RETRIES;
  786. gdth_delay(20);
  787. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  788. if (--retries == 0) {
  789. printk("GDT-ISA: Initialization error\n");
  790. iounmap(ha->brd);
  791. return 0;
  792. }
  793. gdth_delay(1);
  794. }
  795. writeb(0, &dp2_ptr->u.ic.Status);
  796. writeb(0xff, &dp2_ptr->io.irqdel);
  797. ha->dma64_support = 0;
  798. return 1;
  799. }
  800. #endif /* CONFIG_ISA */
  801. #ifdef CONFIG_PCI
  802. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  803. {
  804. register gdt6_dpram_str __iomem *dp6_ptr;
  805. register gdt6c_dpram_str __iomem *dp6c_ptr;
  806. register gdt6m_dpram_str __iomem *dp6m_ptr;
  807. ulong32 retries;
  808. unchar prot_ver;
  809. ushort command;
  810. int i, found = FALSE;
  811. TRACE(("gdth_init_pci()\n"));
  812. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  813. ha->oem_id = OEM_ID_INTEL;
  814. else
  815. ha->oem_id = OEM_ID_ICP;
  816. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  817. ha->stype = (ulong32)pcistr->pdev->device;
  818. ha->irq = pcistr->irq;
  819. ha->pdev = pcistr->pdev;
  820. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  821. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  822. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  823. if (ha->brd == NULL) {
  824. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  825. return 0;
  826. }
  827. /* check and reset interface area */
  828. dp6_ptr = ha->brd;
  829. writel(DPMEM_MAGIC, &dp6_ptr->u);
  830. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  831. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  832. pcistr->dpmem);
  833. found = FALSE;
  834. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  835. iounmap(ha->brd);
  836. ha->brd = ioremap(i, sizeof(ushort));
  837. if (ha->brd == NULL) {
  838. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  839. return 0;
  840. }
  841. if (readw(ha->brd) != 0xffff) {
  842. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  843. continue;
  844. }
  845. iounmap(ha->brd);
  846. pci_write_config_dword(pcistr->pdev,
  847. PCI_BASE_ADDRESS_0, i);
  848. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  849. if (ha->brd == NULL) {
  850. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  851. return 0;
  852. }
  853. dp6_ptr = ha->brd;
  854. writel(DPMEM_MAGIC, &dp6_ptr->u);
  855. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  856. printk("GDT-PCI: Use free address at 0x%x\n", i);
  857. found = TRUE;
  858. break;
  859. }
  860. }
  861. if (!found) {
  862. printk("GDT-PCI: No free address found!\n");
  863. iounmap(ha->brd);
  864. return 0;
  865. }
  866. }
  867. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  868. if (readl(&dp6_ptr->u) != 0) {
  869. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  870. iounmap(ha->brd);
  871. return 0;
  872. }
  873. /* disable board interrupts, deinit services */
  874. writeb(0xff, &dp6_ptr->io.irqdel);
  875. writeb(0x00, &dp6_ptr->io.irqen);
  876. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  877. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  878. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  879. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  880. writeb(0, &dp6_ptr->io.event);
  881. retries = INIT_RETRIES;
  882. gdth_delay(20);
  883. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  884. if (--retries == 0) {
  885. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  886. iounmap(ha->brd);
  887. return 0;
  888. }
  889. gdth_delay(1);
  890. }
  891. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  892. writeb(0, &dp6_ptr->u.ic.S_Status);
  893. writeb(0xff, &dp6_ptr->io.irqdel);
  894. if (prot_ver != PROTOCOL_VERSION) {
  895. printk("GDT-PCI: Illegal protocol version\n");
  896. iounmap(ha->brd);
  897. return 0;
  898. }
  899. ha->type = GDT_PCI;
  900. ha->ic_all_size = sizeof(dp6_ptr->u);
  901. /* special command to controller BIOS */
  902. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  903. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  904. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  905. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  906. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  907. writeb(0, &dp6_ptr->io.event);
  908. retries = INIT_RETRIES;
  909. gdth_delay(20);
  910. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  911. if (--retries == 0) {
  912. printk("GDT-PCI: Initialization error\n");
  913. iounmap(ha->brd);
  914. return 0;
  915. }
  916. gdth_delay(1);
  917. }
  918. writeb(0, &dp6_ptr->u.ic.S_Status);
  919. writeb(0xff, &dp6_ptr->io.irqdel);
  920. ha->dma64_support = 0;
  921. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  922. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  923. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  924. pcistr->dpmem,ha->irq));
  925. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  926. if (ha->brd == NULL) {
  927. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  928. iounmap(ha->brd);
  929. return 0;
  930. }
  931. /* check and reset interface area */
  932. dp6c_ptr = ha->brd;
  933. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  934. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  935. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  936. pcistr->dpmem);
  937. found = FALSE;
  938. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  939. iounmap(ha->brd);
  940. ha->brd = ioremap(i, sizeof(ushort));
  941. if (ha->brd == NULL) {
  942. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  943. return 0;
  944. }
  945. if (readw(ha->brd) != 0xffff) {
  946. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  947. continue;
  948. }
  949. iounmap(ha->brd);
  950. pci_write_config_dword(pcistr->pdev,
  951. PCI_BASE_ADDRESS_2, i);
  952. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  953. if (ha->brd == NULL) {
  954. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  955. return 0;
  956. }
  957. dp6c_ptr = ha->brd;
  958. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  959. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  960. printk("GDT-PCI: Use free address at 0x%x\n", i);
  961. found = TRUE;
  962. break;
  963. }
  964. }
  965. if (!found) {
  966. printk("GDT-PCI: No free address found!\n");
  967. iounmap(ha->brd);
  968. return 0;
  969. }
  970. }
  971. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  972. if (readl(&dp6c_ptr->u) != 0) {
  973. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  974. iounmap(ha->brd);
  975. return 0;
  976. }
  977. /* disable board interrupts, deinit services */
  978. outb(0x00,PTR2USHORT(&ha->plx->control1));
  979. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  980. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  981. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  982. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  983. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  984. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  985. retries = INIT_RETRIES;
  986. gdth_delay(20);
  987. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  988. if (--retries == 0) {
  989. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  990. iounmap(ha->brd);
  991. return 0;
  992. }
  993. gdth_delay(1);
  994. }
  995. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  996. writeb(0, &dp6c_ptr->u.ic.Status);
  997. if (prot_ver != PROTOCOL_VERSION) {
  998. printk("GDT-PCI: Illegal protocol version\n");
  999. iounmap(ha->brd);
  1000. return 0;
  1001. }
  1002. ha->type = GDT_PCINEW;
  1003. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1004. /* special command to controller BIOS */
  1005. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1006. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1007. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1008. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1009. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1010. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1011. retries = INIT_RETRIES;
  1012. gdth_delay(20);
  1013. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1014. if (--retries == 0) {
  1015. printk("GDT-PCI: Initialization error\n");
  1016. iounmap(ha->brd);
  1017. return 0;
  1018. }
  1019. gdth_delay(1);
  1020. }
  1021. writeb(0, &dp6c_ptr->u.ic.S_Status);
  1022. ha->dma64_support = 0;
  1023. } else { /* MPR */
  1024. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1025. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1026. if (ha->brd == NULL) {
  1027. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1028. return 0;
  1029. }
  1030. /* manipulate config. space to enable DPMEM, start RP controller */
  1031. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1032. command |= 6;
  1033. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1034. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1035. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1036. i = 0xFEFF0001UL;
  1037. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1038. gdth_delay(1);
  1039. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1040. pci_resource_start(pcistr->pdev, 8));
  1041. dp6m_ptr = ha->brd;
  1042. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1043. * Aditional check needed for Xscale based RAID controllers */
  1044. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1045. gdth_delay(1);
  1046. /* check and reset interface area */
  1047. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1048. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1049. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1050. pcistr->dpmem);
  1051. found = FALSE;
  1052. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1053. iounmap(ha->brd);
  1054. ha->brd = ioremap(i, sizeof(ushort));
  1055. if (ha->brd == NULL) {
  1056. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1057. return 0;
  1058. }
  1059. if (readw(ha->brd) != 0xffff) {
  1060. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1061. continue;
  1062. }
  1063. iounmap(ha->brd);
  1064. pci_write_config_dword(pcistr->pdev,
  1065. PCI_BASE_ADDRESS_0, i);
  1066. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1067. if (ha->brd == NULL) {
  1068. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1069. return 0;
  1070. }
  1071. dp6m_ptr = ha->brd;
  1072. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1073. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1074. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1075. found = TRUE;
  1076. break;
  1077. }
  1078. }
  1079. if (!found) {
  1080. printk("GDT-PCI: No free address found!\n");
  1081. iounmap(ha->brd);
  1082. return 0;
  1083. }
  1084. }
  1085. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1086. /* disable board interrupts, deinit services */
  1087. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1088. &dp6m_ptr->i960r.edoor_en_reg);
  1089. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1090. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1091. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1092. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1093. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1094. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1095. retries = INIT_RETRIES;
  1096. gdth_delay(20);
  1097. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1098. if (--retries == 0) {
  1099. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1100. iounmap(ha->brd);
  1101. return 0;
  1102. }
  1103. gdth_delay(1);
  1104. }
  1105. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1106. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1107. if (prot_ver != PROTOCOL_VERSION) {
  1108. printk("GDT-PCI: Illegal protocol version\n");
  1109. iounmap(ha->brd);
  1110. return 0;
  1111. }
  1112. ha->type = GDT_PCIMPR;
  1113. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1114. /* special command to controller BIOS */
  1115. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1116. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1117. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1118. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1119. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1120. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1121. retries = INIT_RETRIES;
  1122. gdth_delay(20);
  1123. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1124. if (--retries == 0) {
  1125. printk("GDT-PCI: Initialization error\n");
  1126. iounmap(ha->brd);
  1127. return 0;
  1128. }
  1129. gdth_delay(1);
  1130. }
  1131. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1132. /* read FW version to detect 64-bit DMA support */
  1133. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1134. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1135. retries = INIT_RETRIES;
  1136. gdth_delay(20);
  1137. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1138. if (--retries == 0) {
  1139. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1140. iounmap(ha->brd);
  1141. return 0;
  1142. }
  1143. gdth_delay(1);
  1144. }
  1145. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1146. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1147. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1148. ha->dma64_support = 0;
  1149. else
  1150. ha->dma64_support = 1;
  1151. }
  1152. return 1;
  1153. }
  1154. #endif /* CONFIG_PCI */
  1155. /* controller protocol functions */
  1156. static void __init gdth_enable_int(gdth_ha_str *ha)
  1157. {
  1158. ulong flags;
  1159. gdt2_dpram_str __iomem *dp2_ptr;
  1160. gdt6_dpram_str __iomem *dp6_ptr;
  1161. gdt6m_dpram_str __iomem *dp6m_ptr;
  1162. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1163. spin_lock_irqsave(&ha->smp_lock, flags);
  1164. if (ha->type == GDT_EISA) {
  1165. outb(0xff, ha->bmic + EDOORREG);
  1166. outb(0xff, ha->bmic + EDENABREG);
  1167. outb(0x01, ha->bmic + EINTENABREG);
  1168. } else if (ha->type == GDT_ISA) {
  1169. dp2_ptr = ha->brd;
  1170. writeb(1, &dp2_ptr->io.irqdel);
  1171. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1172. writeb(1, &dp2_ptr->io.irqen);
  1173. } else if (ha->type == GDT_PCI) {
  1174. dp6_ptr = ha->brd;
  1175. writeb(1, &dp6_ptr->io.irqdel);
  1176. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1177. writeb(1, &dp6_ptr->io.irqen);
  1178. } else if (ha->type == GDT_PCINEW) {
  1179. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1180. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1181. } else if (ha->type == GDT_PCIMPR) {
  1182. dp6m_ptr = ha->brd;
  1183. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1184. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1185. &dp6m_ptr->i960r.edoor_en_reg);
  1186. }
  1187. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1188. }
  1189. /* return IStatus if interrupt was from this card else 0 */
  1190. static unchar gdth_get_status(gdth_ha_str *ha)
  1191. {
  1192. unchar IStatus = 0;
  1193. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1194. if (ha->type == GDT_EISA)
  1195. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1196. else if (ha->type == GDT_ISA)
  1197. IStatus =
  1198. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1199. else if (ha->type == GDT_PCI)
  1200. IStatus =
  1201. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1202. else if (ha->type == GDT_PCINEW)
  1203. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1204. else if (ha->type == GDT_PCIMPR)
  1205. IStatus =
  1206. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1207. return IStatus;
  1208. }
  1209. static int gdth_test_busy(gdth_ha_str *ha)
  1210. {
  1211. register int gdtsema0 = 0;
  1212. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1213. if (ha->type == GDT_EISA)
  1214. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1215. else if (ha->type == GDT_ISA)
  1216. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1217. else if (ha->type == GDT_PCI)
  1218. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1219. else if (ha->type == GDT_PCINEW)
  1220. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1221. else if (ha->type == GDT_PCIMPR)
  1222. gdtsema0 =
  1223. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1224. return (gdtsema0 & 1);
  1225. }
  1226. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1227. {
  1228. int i;
  1229. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1230. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1231. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1232. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1233. ha->cmd_tab[i].service = ha->pccb->Service;
  1234. ha->pccb->CommandIndex = (ulong32)i+2;
  1235. return (i+2);
  1236. }
  1237. }
  1238. return 0;
  1239. }
  1240. static void gdth_set_sema0(gdth_ha_str *ha)
  1241. {
  1242. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1243. if (ha->type == GDT_EISA) {
  1244. outb(1, ha->bmic + SEMA0REG);
  1245. } else if (ha->type == GDT_ISA) {
  1246. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1247. } else if (ha->type == GDT_PCI) {
  1248. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1249. } else if (ha->type == GDT_PCINEW) {
  1250. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1251. } else if (ha->type == GDT_PCIMPR) {
  1252. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1253. }
  1254. }
  1255. static void gdth_copy_command(gdth_ha_str *ha)
  1256. {
  1257. register gdth_cmd_str *cmd_ptr;
  1258. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1259. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1260. gdt6_dpram_str __iomem *dp6_ptr;
  1261. gdt2_dpram_str __iomem *dp2_ptr;
  1262. ushort cp_count,dp_offset,cmd_no;
  1263. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1264. cp_count = ha->cmd_len;
  1265. dp_offset= ha->cmd_offs_dpmem;
  1266. cmd_no = ha->cmd_cnt;
  1267. cmd_ptr = ha->pccb;
  1268. ++ha->cmd_cnt;
  1269. if (ha->type == GDT_EISA)
  1270. return; /* no DPMEM, no copy */
  1271. /* set cpcount dword aligned */
  1272. if (cp_count & 3)
  1273. cp_count += (4 - (cp_count & 3));
  1274. ha->cmd_offs_dpmem += cp_count;
  1275. /* set offset and service, copy command to DPMEM */
  1276. if (ha->type == GDT_ISA) {
  1277. dp2_ptr = ha->brd;
  1278. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1279. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1280. writew((ushort)cmd_ptr->Service,
  1281. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1282. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1283. } else if (ha->type == GDT_PCI) {
  1284. dp6_ptr = ha->brd;
  1285. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1286. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1287. writew((ushort)cmd_ptr->Service,
  1288. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1289. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1290. } else if (ha->type == GDT_PCINEW) {
  1291. dp6c_ptr = ha->brd;
  1292. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1293. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1294. writew((ushort)cmd_ptr->Service,
  1295. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1296. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1297. } else if (ha->type == GDT_PCIMPR) {
  1298. dp6m_ptr = ha->brd;
  1299. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1300. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1301. writew((ushort)cmd_ptr->Service,
  1302. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1303. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1304. }
  1305. }
  1306. static void gdth_release_event(gdth_ha_str *ha)
  1307. {
  1308. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1309. #ifdef GDTH_STATISTICS
  1310. {
  1311. ulong32 i,j;
  1312. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1313. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1314. ++i;
  1315. }
  1316. if (max_index < i) {
  1317. max_index = i;
  1318. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1319. }
  1320. }
  1321. #endif
  1322. if (ha->pccb->OpCode == GDT_INIT)
  1323. ha->pccb->Service |= 0x80;
  1324. if (ha->type == GDT_EISA) {
  1325. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1326. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1327. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1328. } else if (ha->type == GDT_ISA) {
  1329. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1330. } else if (ha->type == GDT_PCI) {
  1331. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1332. } else if (ha->type == GDT_PCINEW) {
  1333. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1334. } else if (ha->type == GDT_PCIMPR) {
  1335. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1336. }
  1337. }
  1338. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1339. {
  1340. int answer_found = FALSE;
  1341. int wait_index = 0;
  1342. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1343. if (index == 0)
  1344. return 1; /* no wait required */
  1345. do {
  1346. __gdth_interrupt(ha, true, &wait_index);
  1347. if (wait_index == index) {
  1348. answer_found = TRUE;
  1349. break;
  1350. }
  1351. gdth_delay(1);
  1352. } while (--time);
  1353. while (gdth_test_busy(ha))
  1354. gdth_delay(0);
  1355. return (answer_found);
  1356. }
  1357. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1358. ulong32 p1, ulong64 p2, ulong64 p3)
  1359. {
  1360. register gdth_cmd_str *cmd_ptr;
  1361. int retries,index;
  1362. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1363. cmd_ptr = ha->pccb;
  1364. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1365. /* make command */
  1366. for (retries = INIT_RETRIES;;) {
  1367. cmd_ptr->Service = service;
  1368. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1369. if (!(index=gdth_get_cmd_index(ha))) {
  1370. TRACE(("GDT: No free command index found\n"));
  1371. return 0;
  1372. }
  1373. gdth_set_sema0(ha);
  1374. cmd_ptr->OpCode = opcode;
  1375. cmd_ptr->BoardNode = LOCALBOARD;
  1376. if (service == CACHESERVICE) {
  1377. if (opcode == GDT_IOCTL) {
  1378. cmd_ptr->u.ioctl.subfunc = p1;
  1379. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1380. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1381. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1382. } else {
  1383. if (ha->cache_feat & GDT_64BIT) {
  1384. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1385. cmd_ptr->u.cache64.BlockNo = p2;
  1386. } else {
  1387. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1388. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1389. }
  1390. }
  1391. } else if (service == SCSIRAWSERVICE) {
  1392. if (ha->raw_feat & GDT_64BIT) {
  1393. cmd_ptr->u.raw64.direction = p1;
  1394. cmd_ptr->u.raw64.bus = (unchar)p2;
  1395. cmd_ptr->u.raw64.target = (unchar)p3;
  1396. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1397. } else {
  1398. cmd_ptr->u.raw.direction = p1;
  1399. cmd_ptr->u.raw.bus = (unchar)p2;
  1400. cmd_ptr->u.raw.target = (unchar)p3;
  1401. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1402. }
  1403. } else if (service == SCREENSERVICE) {
  1404. if (opcode == GDT_REALTIME) {
  1405. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1406. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1407. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1408. }
  1409. }
  1410. ha->cmd_len = sizeof(gdth_cmd_str);
  1411. ha->cmd_offs_dpmem = 0;
  1412. ha->cmd_cnt = 0;
  1413. gdth_copy_command(ha);
  1414. gdth_release_event(ha);
  1415. gdth_delay(20);
  1416. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1417. printk("GDT: Initialization error (timeout service %d)\n",service);
  1418. return 0;
  1419. }
  1420. if (ha->status != S_BSY || --retries == 0)
  1421. break;
  1422. gdth_delay(1);
  1423. }
  1424. return (ha->status != S_OK ? 0:1);
  1425. }
  1426. /* search for devices */
  1427. static int __init gdth_search_drives(gdth_ha_str *ha)
  1428. {
  1429. ushort cdev_cnt, i;
  1430. int ok;
  1431. ulong32 bus_no, drv_cnt, drv_no, j;
  1432. gdth_getch_str *chn;
  1433. gdth_drlist_str *drl;
  1434. gdth_iochan_str *ioc;
  1435. gdth_raw_iochan_str *iocr;
  1436. gdth_arcdl_str *alst;
  1437. gdth_alist_str *alst2;
  1438. gdth_oem_str_ioctl *oemstr;
  1439. #ifdef INT_COAL
  1440. gdth_perf_modes *pmod;
  1441. #endif
  1442. #ifdef GDTH_RTC
  1443. unchar rtc[12];
  1444. ulong flags;
  1445. #endif
  1446. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1447. ok = 0;
  1448. /* initialize controller services, at first: screen service */
  1449. ha->screen_feat = 0;
  1450. if (!force_dma32) {
  1451. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1452. if (ok)
  1453. ha->screen_feat = GDT_64BIT;
  1454. }
  1455. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1456. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1457. if (!ok) {
  1458. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1459. ha->hanum, ha->status);
  1460. return 0;
  1461. }
  1462. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1463. #ifdef GDTH_RTC
  1464. /* read realtime clock info, send to controller */
  1465. /* 1. wait for the falling edge of update flag */
  1466. spin_lock_irqsave(&rtc_lock, flags);
  1467. for (j = 0; j < 1000000; ++j)
  1468. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1469. break;
  1470. for (j = 0; j < 1000000; ++j)
  1471. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1472. break;
  1473. /* 2. read info */
  1474. do {
  1475. for (j = 0; j < 12; ++j)
  1476. rtc[j] = CMOS_READ(j);
  1477. } while (rtc[0] != CMOS_READ(0));
  1478. spin_unlock_irqrestore(&rtc_lock, flags);
  1479. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1480. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1481. /* 3. send to controller firmware */
  1482. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1483. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1484. #endif
  1485. /* unfreeze all IOs */
  1486. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1487. /* initialize cache service */
  1488. ha->cache_feat = 0;
  1489. if (!force_dma32) {
  1490. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1491. 0, 0);
  1492. if (ok)
  1493. ha->cache_feat = GDT_64BIT;
  1494. }
  1495. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1496. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1497. if (!ok) {
  1498. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1499. ha->hanum, ha->status);
  1500. return 0;
  1501. }
  1502. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1503. cdev_cnt = (ushort)ha->info;
  1504. ha->fw_vers = ha->service;
  1505. #ifdef INT_COAL
  1506. if (ha->type == GDT_PCIMPR) {
  1507. /* set perf. modes */
  1508. pmod = (gdth_perf_modes *)ha->pscratch;
  1509. pmod->version = 1;
  1510. pmod->st_mode = 1; /* enable one status buffer */
  1511. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1512. pmod->st_buff_indx1 = COALINDEX;
  1513. pmod->st_buff_addr2 = 0;
  1514. pmod->st_buff_u_addr2 = 0;
  1515. pmod->st_buff_indx2 = 0;
  1516. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1517. pmod->cmd_mode = 0; // disable all cmd buffers
  1518. pmod->cmd_buff_addr1 = 0;
  1519. pmod->cmd_buff_u_addr1 = 0;
  1520. pmod->cmd_buff_indx1 = 0;
  1521. pmod->cmd_buff_addr2 = 0;
  1522. pmod->cmd_buff_u_addr2 = 0;
  1523. pmod->cmd_buff_indx2 = 0;
  1524. pmod->cmd_buff_size = 0;
  1525. pmod->reserved1 = 0;
  1526. pmod->reserved2 = 0;
  1527. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1528. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1529. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1530. }
  1531. }
  1532. #endif
  1533. /* detect number of buses - try new IOCTL */
  1534. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1535. iocr->hdr.version = 0xffffffff;
  1536. iocr->hdr.list_entries = MAXBUS;
  1537. iocr->hdr.first_chan = 0;
  1538. iocr->hdr.last_chan = MAXBUS-1;
  1539. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1540. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1541. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1542. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1543. ha->bus_cnt = iocr->hdr.chan_count;
  1544. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1545. if (iocr->list[bus_no].proc_id < MAXID)
  1546. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1547. else
  1548. ha->bus_id[bus_no] = 0xff;
  1549. }
  1550. } else {
  1551. /* old method */
  1552. chn = (gdth_getch_str *)ha->pscratch;
  1553. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1554. chn->channel_no = bus_no;
  1555. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1556. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1557. IO_CHANNEL | INVALID_CHANNEL,
  1558. sizeof(gdth_getch_str))) {
  1559. if (bus_no == 0) {
  1560. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1561. ha->hanum, ha->status);
  1562. return 0;
  1563. }
  1564. break;
  1565. }
  1566. if (chn->siop_id < MAXID)
  1567. ha->bus_id[bus_no] = chn->siop_id;
  1568. else
  1569. ha->bus_id[bus_no] = 0xff;
  1570. }
  1571. ha->bus_cnt = (unchar)bus_no;
  1572. }
  1573. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1574. /* read cache configuration */
  1575. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1576. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1577. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1578. ha->hanum, ha->status);
  1579. return 0;
  1580. }
  1581. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1582. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1583. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1584. ha->cpar.write_back,ha->cpar.block_size));
  1585. /* read board info and features */
  1586. ha->more_proc = FALSE;
  1587. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1588. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1589. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1590. sizeof(gdth_binfo_str));
  1591. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1592. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1593. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1594. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1595. ha->more_proc = TRUE;
  1596. }
  1597. } else {
  1598. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1599. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1600. }
  1601. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1602. /* read more informations */
  1603. if (ha->more_proc) {
  1604. /* physical drives, channel addresses */
  1605. ioc = (gdth_iochan_str *)ha->pscratch;
  1606. ioc->hdr.version = 0xffffffff;
  1607. ioc->hdr.list_entries = MAXBUS;
  1608. ioc->hdr.first_chan = 0;
  1609. ioc->hdr.last_chan = MAXBUS-1;
  1610. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1611. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1612. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1613. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1614. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1615. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1616. }
  1617. } else {
  1618. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1619. ha->raw[bus_no].address = IO_CHANNEL;
  1620. ha->raw[bus_no].local_no = bus_no;
  1621. }
  1622. }
  1623. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1624. chn = (gdth_getch_str *)ha->pscratch;
  1625. chn->channel_no = ha->raw[bus_no].local_no;
  1626. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1627. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1628. ha->raw[bus_no].address | INVALID_CHANNEL,
  1629. sizeof(gdth_getch_str))) {
  1630. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1631. TRACE2(("Channel %d: %d phys. drives\n",
  1632. bus_no,chn->drive_cnt));
  1633. }
  1634. if (ha->raw[bus_no].pdev_cnt > 0) {
  1635. drl = (gdth_drlist_str *)ha->pscratch;
  1636. drl->sc_no = ha->raw[bus_no].local_no;
  1637. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1638. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1639. SCSI_DR_LIST | L_CTRL_PATTERN,
  1640. ha->raw[bus_no].address | INVALID_CHANNEL,
  1641. sizeof(gdth_drlist_str))) {
  1642. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1643. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1644. } else {
  1645. ha->raw[bus_no].pdev_cnt = 0;
  1646. }
  1647. }
  1648. }
  1649. /* logical drives */
  1650. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1651. INVALID_CHANNEL,sizeof(ulong32))) {
  1652. drv_cnt = *(ulong32 *)ha->pscratch;
  1653. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1654. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1655. for (j = 0; j < drv_cnt; ++j) {
  1656. drv_no = ((ulong32 *)ha->pscratch)[j];
  1657. if (drv_no < MAX_LDRIVES) {
  1658. ha->hdr[drv_no].is_logdrv = TRUE;
  1659. TRACE2(("Drive %d is log. drive\n",drv_no));
  1660. }
  1661. }
  1662. }
  1663. alst = (gdth_arcdl_str *)ha->pscratch;
  1664. alst->entries_avail = MAX_LDRIVES;
  1665. alst->first_entry = 0;
  1666. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1667. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1668. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1669. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1670. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1671. for (j = 0; j < alst->entries_init; ++j) {
  1672. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1673. ha->hdr[j].is_master = alst->list[j].is_master;
  1674. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1675. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1676. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1677. }
  1678. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1679. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1680. 0, 35 * sizeof(gdth_alist_str))) {
  1681. for (j = 0; j < 35; ++j) {
  1682. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1683. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1684. ha->hdr[j].is_master = alst2->is_master;
  1685. ha->hdr[j].is_parity = alst2->is_parity;
  1686. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1687. ha->hdr[j].master_no = alst2->cd_handle;
  1688. }
  1689. }
  1690. }
  1691. }
  1692. /* initialize raw service */
  1693. ha->raw_feat = 0;
  1694. if (!force_dma32) {
  1695. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1696. if (ok)
  1697. ha->raw_feat = GDT_64BIT;
  1698. }
  1699. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1700. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1701. if (!ok) {
  1702. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1703. ha->hanum, ha->status);
  1704. return 0;
  1705. }
  1706. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1707. /* set/get features raw service (scatter/gather) */
  1708. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1709. 0, 0)) {
  1710. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1711. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1712. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1713. ha->info));
  1714. ha->raw_feat |= (ushort)ha->info;
  1715. }
  1716. }
  1717. /* set/get features cache service (equal to raw service) */
  1718. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1719. SCATTER_GATHER,0)) {
  1720. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1721. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1722. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1723. ha->info));
  1724. ha->cache_feat |= (ushort)ha->info;
  1725. }
  1726. }
  1727. /* reserve drives for raw service */
  1728. if (reserve_mode != 0) {
  1729. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1730. reserve_mode == 1 ? 1 : 3, 0, 0);
  1731. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1732. ha->status));
  1733. }
  1734. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1735. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1736. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1737. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1738. reserve_list[i], reserve_list[i+1],
  1739. reserve_list[i+2], reserve_list[i+3]));
  1740. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1741. reserve_list[i+1], reserve_list[i+2] |
  1742. (reserve_list[i+3] << 8))) {
  1743. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1744. ha->hanum, ha->status);
  1745. }
  1746. }
  1747. }
  1748. /* Determine OEM string using IOCTL */
  1749. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1750. oemstr->params.ctl_version = 0x01;
  1751. oemstr->params.buffer_size = sizeof(oemstr->text);
  1752. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1753. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1754. sizeof(gdth_oem_str_ioctl))) {
  1755. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1756. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1757. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1758. /* Save the Host Drive inquiry data */
  1759. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1760. sizeof(ha->oem_name));
  1761. } else {
  1762. /* Old method, based on PCI ID */
  1763. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1764. printk("GDT-HA %d: Name: %s\n",
  1765. ha->hanum, ha->binfo.type_string);
  1766. if (ha->oem_id == OEM_ID_INTEL)
  1767. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1768. else
  1769. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1770. }
  1771. /* scanning for host drives */
  1772. for (i = 0; i < cdev_cnt; ++i)
  1773. gdth_analyse_hdrive(ha, i);
  1774. TRACE(("gdth_search_drives() OK\n"));
  1775. return 1;
  1776. }
  1777. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1778. {
  1779. ulong32 drv_cyls;
  1780. int drv_hds, drv_secs;
  1781. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1782. if (hdrive >= MAX_HDRIVES)
  1783. return 0;
  1784. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1785. return 0;
  1786. ha->hdr[hdrive].present = TRUE;
  1787. ha->hdr[hdrive].size = ha->info;
  1788. /* evaluate mapping (sectors per head, heads per cylinder) */
  1789. ha->hdr[hdrive].size &= ~SECS32;
  1790. if (ha->info2 == 0) {
  1791. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1792. } else {
  1793. drv_hds = ha->info2 & 0xff;
  1794. drv_secs = (ha->info2 >> 8) & 0xff;
  1795. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1796. }
  1797. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1798. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1799. /* round size */
  1800. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1801. if (ha->cache_feat & GDT_64BIT) {
  1802. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1803. && ha->info2 != 0) {
  1804. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1805. }
  1806. }
  1807. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1808. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1809. /* get informations about device */
  1810. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1811. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1812. hdrive,ha->info));
  1813. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1814. }
  1815. /* cluster info */
  1816. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1817. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1818. hdrive,ha->info));
  1819. if (!shared_access)
  1820. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1821. }
  1822. /* R/W attributes */
  1823. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1824. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1825. hdrive,ha->info));
  1826. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1827. }
  1828. return 1;
  1829. }
  1830. /* command queueing/sending functions */
  1831. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1832. {
  1833. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1834. register Scsi_Cmnd *pscp;
  1835. register Scsi_Cmnd *nscp;
  1836. ulong flags;
  1837. unchar b, t;
  1838. TRACE(("gdth_putq() priority %d\n",priority));
  1839. spin_lock_irqsave(&ha->smp_lock, flags);
  1840. if (!cmndinfo->internal_command) {
  1841. cmndinfo->priority = priority;
  1842. b = scp->device->channel;
  1843. t = scp->device->id;
  1844. if (priority >= DEFAULT_PRI) {
  1845. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1846. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1847. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1848. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1849. }
  1850. }
  1851. }
  1852. if (ha->req_first==NULL) {
  1853. ha->req_first = scp; /* queue was empty */
  1854. scp->SCp.ptr = NULL;
  1855. } else { /* queue not empty */
  1856. pscp = ha->req_first;
  1857. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1858. /* priority: 0-highest,..,0xff-lowest */
  1859. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1860. pscp = nscp;
  1861. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1862. }
  1863. pscp->SCp.ptr = (char *)scp;
  1864. scp->SCp.ptr = (char *)nscp;
  1865. }
  1866. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1867. #ifdef GDTH_STATISTICS
  1868. flags = 0;
  1869. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1870. ++flags;
  1871. if (max_rq < flags) {
  1872. max_rq = flags;
  1873. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1874. }
  1875. #endif
  1876. }
  1877. static void gdth_next(gdth_ha_str *ha)
  1878. {
  1879. register Scsi_Cmnd *pscp;
  1880. register Scsi_Cmnd *nscp;
  1881. unchar b, t, l, firsttime;
  1882. unchar this_cmd, next_cmd;
  1883. ulong flags = 0;
  1884. int cmd_index;
  1885. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1886. if (!gdth_polling)
  1887. spin_lock_irqsave(&ha->smp_lock, flags);
  1888. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1889. this_cmd = firsttime = TRUE;
  1890. next_cmd = gdth_polling ? FALSE:TRUE;
  1891. cmd_index = 0;
  1892. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1893. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1894. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1895. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1896. if (!nscp_cmndinfo->internal_command) {
  1897. b = nscp->device->channel;
  1898. t = nscp->device->id;
  1899. l = nscp->device->lun;
  1900. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1901. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1902. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1903. continue;
  1904. }
  1905. } else
  1906. b = t = l = 0;
  1907. if (firsttime) {
  1908. if (gdth_test_busy(ha)) { /* controller busy ? */
  1909. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1910. if (!gdth_polling) {
  1911. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1912. return;
  1913. }
  1914. while (gdth_test_busy(ha))
  1915. gdth_delay(1);
  1916. }
  1917. firsttime = FALSE;
  1918. }
  1919. if (!nscp_cmndinfo->internal_command) {
  1920. if (nscp_cmndinfo->phase == -1) {
  1921. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1922. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1923. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1924. b, t, l));
  1925. /* TEST_UNIT_READY -> set scan mode */
  1926. if ((ha->scan_mode & 0x0f) == 0) {
  1927. if (b == 0 && t == 0 && l == 0) {
  1928. ha->scan_mode |= 1;
  1929. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1930. }
  1931. } else if ((ha->scan_mode & 0x0f) == 1) {
  1932. if (b == 0 && ((t == 0 && l == 1) ||
  1933. (t == 1 && l == 0))) {
  1934. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1935. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1936. | SCSIRAWSERVICE;
  1937. ha->scan_mode = 0x12;
  1938. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1939. ha->scan_mode));
  1940. } else {
  1941. ha->scan_mode &= 0x10;
  1942. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1943. }
  1944. } else if (ha->scan_mode == 0x12) {
  1945. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1946. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1947. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1948. ha->scan_mode &= 0x10;
  1949. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1950. ha->scan_mode));
  1951. }
  1952. }
  1953. }
  1954. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1955. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1956. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1957. /* always GDT_CLUST_INFO! */
  1958. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1959. }
  1960. }
  1961. }
  1962. if (nscp_cmndinfo->OpCode != -1) {
  1963. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1964. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1965. this_cmd = FALSE;
  1966. next_cmd = FALSE;
  1967. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1968. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1969. this_cmd = FALSE;
  1970. next_cmd = FALSE;
  1971. } else {
  1972. memset((char*)nscp->sense_buffer,0,16);
  1973. nscp->sense_buffer[0] = 0x70;
  1974. nscp->sense_buffer[2] = NOT_READY;
  1975. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1976. if (!nscp_cmndinfo->wait_for_completion)
  1977. nscp_cmndinfo->wait_for_completion++;
  1978. else
  1979. gdth_scsi_done(nscp);
  1980. }
  1981. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1982. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1983. this_cmd = FALSE;
  1984. next_cmd = FALSE;
  1985. } else if (b != ha->virt_bus) {
  1986. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1987. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1988. this_cmd = FALSE;
  1989. else
  1990. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1991. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1992. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1993. nscp->cmnd[0], b, t, l));
  1994. nscp->result = DID_BAD_TARGET << 16;
  1995. if (!nscp_cmndinfo->wait_for_completion)
  1996. nscp_cmndinfo->wait_for_completion++;
  1997. else
  1998. gdth_scsi_done(nscp);
  1999. } else {
  2000. switch (nscp->cmnd[0]) {
  2001. case TEST_UNIT_READY:
  2002. case INQUIRY:
  2003. case REQUEST_SENSE:
  2004. case READ_CAPACITY:
  2005. case VERIFY:
  2006. case START_STOP:
  2007. case MODE_SENSE:
  2008. case SERVICE_ACTION_IN:
  2009. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2010. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2011. nscp->cmnd[4],nscp->cmnd[5]));
  2012. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2013. /* return UNIT_ATTENTION */
  2014. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2015. nscp->cmnd[0], t));
  2016. ha->hdr[t].media_changed = FALSE;
  2017. memset((char*)nscp->sense_buffer,0,16);
  2018. nscp->sense_buffer[0] = 0x70;
  2019. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2020. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2021. if (!nscp_cmndinfo->wait_for_completion)
  2022. nscp_cmndinfo->wait_for_completion++;
  2023. else
  2024. gdth_scsi_done(nscp);
  2025. } else if (gdth_internal_cache_cmd(ha, nscp))
  2026. gdth_scsi_done(nscp);
  2027. break;
  2028. case ALLOW_MEDIUM_REMOVAL:
  2029. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2030. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2031. nscp->cmnd[4],nscp->cmnd[5]));
  2032. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2033. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2034. nscp->result = DID_OK << 16;
  2035. nscp->sense_buffer[0] = 0;
  2036. if (!nscp_cmndinfo->wait_for_completion)
  2037. nscp_cmndinfo->wait_for_completion++;
  2038. else
  2039. gdth_scsi_done(nscp);
  2040. } else {
  2041. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2042. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2043. nscp->cmnd[4],nscp->cmnd[3]));
  2044. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2045. this_cmd = FALSE;
  2046. }
  2047. break;
  2048. case RESERVE:
  2049. case RELEASE:
  2050. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2051. "RESERVE" : "RELEASE"));
  2052. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2053. this_cmd = FALSE;
  2054. break;
  2055. case READ_6:
  2056. case WRITE_6:
  2057. case READ_10:
  2058. case WRITE_10:
  2059. case READ_16:
  2060. case WRITE_16:
  2061. if (ha->hdr[t].media_changed) {
  2062. /* return UNIT_ATTENTION */
  2063. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2064. nscp->cmnd[0], t));
  2065. ha->hdr[t].media_changed = FALSE;
  2066. memset((char*)nscp->sense_buffer,0,16);
  2067. nscp->sense_buffer[0] = 0x70;
  2068. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2069. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2070. if (!nscp_cmndinfo->wait_for_completion)
  2071. nscp_cmndinfo->wait_for_completion++;
  2072. else
  2073. gdth_scsi_done(nscp);
  2074. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2075. this_cmd = FALSE;
  2076. break;
  2077. default:
  2078. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2079. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2080. nscp->cmnd[4],nscp->cmnd[5]));
  2081. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2082. ha->hanum, nscp->cmnd[0]);
  2083. nscp->result = DID_ABORT << 16;
  2084. if (!nscp_cmndinfo->wait_for_completion)
  2085. nscp_cmndinfo->wait_for_completion++;
  2086. else
  2087. gdth_scsi_done(nscp);
  2088. break;
  2089. }
  2090. }
  2091. if (!this_cmd)
  2092. break;
  2093. if (nscp == ha->req_first)
  2094. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2095. else
  2096. pscp->SCp.ptr = nscp->SCp.ptr;
  2097. if (!next_cmd)
  2098. break;
  2099. }
  2100. if (ha->cmd_cnt > 0) {
  2101. gdth_release_event(ha);
  2102. }
  2103. if (!gdth_polling)
  2104. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2105. if (gdth_polling && ha->cmd_cnt > 0) {
  2106. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2107. printk("GDT-HA %d: Command %d timed out !\n",
  2108. ha->hanum, cmd_index);
  2109. }
  2110. }
  2111. /*
  2112. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2113. * buffers, kmap_atomic() as needed.
  2114. */
  2115. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2116. char *buffer, ushort count)
  2117. {
  2118. ushort cpcount,i, max_sg = gdth_sg_count(scp);
  2119. ushort cpsum,cpnow;
  2120. struct scatterlist *sl;
  2121. char *address;
  2122. cpcount = min_t(ushort, count, gdth_bufflen(scp));
  2123. if (cpcount) {
  2124. cpsum=0;
  2125. scsi_for_each_sg(scp, sl, max_sg, i) {
  2126. unsigned long flags;
  2127. cpnow = (ushort)sl->length;
  2128. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2129. cpnow, cpsum, cpcount, gdth_bufflen(scp)));
  2130. if (cpsum+cpnow > cpcount)
  2131. cpnow = cpcount - cpsum;
  2132. cpsum += cpnow;
  2133. if (!sg_page(sl)) {
  2134. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2135. ha->hanum);
  2136. return;
  2137. }
  2138. local_irq_save(flags);
  2139. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2140. memcpy(address, buffer, cpnow);
  2141. flush_dcache_page(sg_page(sl));
  2142. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2143. local_irq_restore(flags);
  2144. if (cpsum == cpcount)
  2145. break;
  2146. buffer += cpnow;
  2147. }
  2148. } else if (count) {
  2149. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2150. ha->hanum);
  2151. WARN_ON(1);
  2152. }
  2153. }
  2154. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2155. {
  2156. unchar t;
  2157. gdth_inq_data inq;
  2158. gdth_rdcap_data rdc;
  2159. gdth_sense_data sd;
  2160. gdth_modep_data mpd;
  2161. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2162. t = scp->device->id;
  2163. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2164. scp->cmnd[0],t));
  2165. scp->result = DID_OK << 16;
  2166. scp->sense_buffer[0] = 0;
  2167. switch (scp->cmnd[0]) {
  2168. case TEST_UNIT_READY:
  2169. case VERIFY:
  2170. case START_STOP:
  2171. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2172. break;
  2173. case INQUIRY:
  2174. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2175. t,ha->hdr[t].devtype));
  2176. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2177. /* you can here set all disks to removable, if you want to do
  2178. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2179. inq.modif_rmb = 0x00;
  2180. if ((ha->hdr[t].devtype & 1) ||
  2181. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2182. inq.modif_rmb = 0x80;
  2183. inq.version = 2;
  2184. inq.resp_aenc = 2;
  2185. inq.add_length= 32;
  2186. strcpy(inq.vendor,ha->oem_name);
  2187. sprintf(inq.product,"Host Drive #%02d",t);
  2188. strcpy(inq.revision," ");
  2189. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2190. break;
  2191. case REQUEST_SENSE:
  2192. TRACE2(("Request sense hdrive %d\n",t));
  2193. sd.errorcode = 0x70;
  2194. sd.segno = 0x00;
  2195. sd.key = NO_SENSE;
  2196. sd.info = 0;
  2197. sd.add_length= 0;
  2198. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2199. break;
  2200. case MODE_SENSE:
  2201. TRACE2(("Mode sense hdrive %d\n",t));
  2202. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2203. mpd.hd.data_length = sizeof(gdth_modep_data);
  2204. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2205. mpd.hd.bd_length = sizeof(mpd.bd);
  2206. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2207. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2208. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2209. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2210. break;
  2211. case READ_CAPACITY:
  2212. TRACE2(("Read capacity hdrive %d\n",t));
  2213. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2214. rdc.last_block_no = 0xffffffff;
  2215. else
  2216. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2217. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2218. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2219. break;
  2220. case SERVICE_ACTION_IN:
  2221. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2222. (ha->cache_feat & GDT_64BIT)) {
  2223. gdth_rdcap16_data rdc16;
  2224. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2225. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2226. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2227. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2228. sizeof(gdth_rdcap16_data));
  2229. } else {
  2230. scp->result = DID_ABORT << 16;
  2231. }
  2232. break;
  2233. default:
  2234. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2235. break;
  2236. }
  2237. if (!cmndinfo->wait_for_completion)
  2238. cmndinfo->wait_for_completion++;
  2239. else
  2240. return 1;
  2241. return 0;
  2242. }
  2243. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2244. {
  2245. register gdth_cmd_str *cmdp;
  2246. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2247. ulong32 cnt, blockcnt;
  2248. ulong64 no, blockno;
  2249. int i, cmd_index, read_write, sgcnt, mode64;
  2250. cmdp = ha->pccb;
  2251. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2252. scp->cmnd[0],scp->cmd_len,hdrive));
  2253. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2254. return 0;
  2255. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2256. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2257. not required, should not occur due to error return on
  2258. READ_CAPACITY_16 */
  2259. cmdp->Service = CACHESERVICE;
  2260. cmdp->RequestBuffer = scp;
  2261. /* search free command index */
  2262. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2263. TRACE(("GDT: No free command index found\n"));
  2264. return 0;
  2265. }
  2266. /* if it's the first command, set command semaphore */
  2267. if (ha->cmd_cnt == 0)
  2268. gdth_set_sema0(ha);
  2269. /* fill command */
  2270. read_write = 0;
  2271. if (cmndinfo->OpCode != -1)
  2272. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2273. else if (scp->cmnd[0] == RESERVE)
  2274. cmdp->OpCode = GDT_RESERVE_DRV;
  2275. else if (scp->cmnd[0] == RELEASE)
  2276. cmdp->OpCode = GDT_RELEASE_DRV;
  2277. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2278. if (scp->cmnd[4] & 1) /* prevent ? */
  2279. cmdp->OpCode = GDT_MOUNT;
  2280. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2281. cmdp->OpCode = GDT_UNMOUNT;
  2282. else
  2283. cmdp->OpCode = GDT_FLUSH;
  2284. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2285. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2286. ) {
  2287. read_write = 1;
  2288. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2289. (ha->cache_feat & GDT_WR_THROUGH)))
  2290. cmdp->OpCode = GDT_WRITE_THR;
  2291. else
  2292. cmdp->OpCode = GDT_WRITE;
  2293. } else {
  2294. read_write = 2;
  2295. cmdp->OpCode = GDT_READ;
  2296. }
  2297. cmdp->BoardNode = LOCALBOARD;
  2298. if (mode64) {
  2299. cmdp->u.cache64.DeviceNo = hdrive;
  2300. cmdp->u.cache64.BlockNo = 1;
  2301. cmdp->u.cache64.sg_canz = 0;
  2302. } else {
  2303. cmdp->u.cache.DeviceNo = hdrive;
  2304. cmdp->u.cache.BlockNo = 1;
  2305. cmdp->u.cache.sg_canz = 0;
  2306. }
  2307. if (read_write) {
  2308. if (scp->cmd_len == 16) {
  2309. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2310. blockno = be64_to_cpu(no);
  2311. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2312. blockcnt = be32_to_cpu(cnt);
  2313. } else if (scp->cmd_len == 10) {
  2314. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2315. blockno = be32_to_cpu(no);
  2316. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2317. blockcnt = be16_to_cpu(cnt);
  2318. } else {
  2319. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2320. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2321. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2322. }
  2323. if (mode64) {
  2324. cmdp->u.cache64.BlockNo = blockno;
  2325. cmdp->u.cache64.BlockCnt = blockcnt;
  2326. } else {
  2327. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2328. cmdp->u.cache.BlockCnt = blockcnt;
  2329. }
  2330. if (gdth_bufflen(scp)) {
  2331. cmndinfo->dma_dir = (read_write == 1 ?
  2332. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2333. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2334. cmndinfo->dma_dir);
  2335. if (mode64) {
  2336. struct scatterlist *sl;
  2337. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2338. cmdp->u.cache64.sg_canz = sgcnt;
  2339. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2340. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2341. #ifdef GDTH_DMA_STATISTICS
  2342. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2343. ha->dma64_cnt++;
  2344. else
  2345. ha->dma32_cnt++;
  2346. #endif
  2347. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2348. }
  2349. } else {
  2350. struct scatterlist *sl;
  2351. cmdp->u.cache.DestAddr= 0xffffffff;
  2352. cmdp->u.cache.sg_canz = sgcnt;
  2353. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2354. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2355. #ifdef GDTH_DMA_STATISTICS
  2356. ha->dma32_cnt++;
  2357. #endif
  2358. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2359. }
  2360. }
  2361. #ifdef GDTH_STATISTICS
  2362. if (max_sg < (ulong32)sgcnt) {
  2363. max_sg = (ulong32)sgcnt;
  2364. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2365. }
  2366. #endif
  2367. }
  2368. }
  2369. /* evaluate command size, check space */
  2370. if (mode64) {
  2371. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2372. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2373. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2374. cmdp->u.cache64.sg_lst[0].sg_len));
  2375. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2376. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2377. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2378. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2379. } else {
  2380. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2381. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2382. cmdp->u.cache.sg_lst[0].sg_ptr,
  2383. cmdp->u.cache.sg_lst[0].sg_len));
  2384. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2385. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2386. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2387. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2388. }
  2389. if (ha->cmd_len & 3)
  2390. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2391. if (ha->cmd_cnt > 0) {
  2392. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2393. ha->ic_all_size) {
  2394. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2395. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2396. return 0;
  2397. }
  2398. }
  2399. /* copy command */
  2400. gdth_copy_command(ha);
  2401. return cmd_index;
  2402. }
  2403. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2404. {
  2405. register gdth_cmd_str *cmdp;
  2406. ushort i;
  2407. dma_addr_t sense_paddr;
  2408. int cmd_index, sgcnt, mode64;
  2409. unchar t,l;
  2410. struct page *page;
  2411. ulong offset;
  2412. struct gdth_cmndinfo *cmndinfo;
  2413. t = scp->device->id;
  2414. l = scp->device->lun;
  2415. cmdp = ha->pccb;
  2416. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2417. scp->cmnd[0],b,t,l));
  2418. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2419. return 0;
  2420. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2421. cmdp->Service = SCSIRAWSERVICE;
  2422. cmdp->RequestBuffer = scp;
  2423. /* search free command index */
  2424. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2425. TRACE(("GDT: No free command index found\n"));
  2426. return 0;
  2427. }
  2428. /* if it's the first command, set command semaphore */
  2429. if (ha->cmd_cnt == 0)
  2430. gdth_set_sema0(ha);
  2431. cmndinfo = gdth_cmnd_priv(scp);
  2432. /* fill command */
  2433. if (cmndinfo->OpCode != -1) {
  2434. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2435. cmdp->BoardNode = LOCALBOARD;
  2436. if (mode64) {
  2437. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2438. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2439. cmdp->OpCode, cmdp->u.raw64.direction));
  2440. /* evaluate command size */
  2441. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2442. } else {
  2443. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2444. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2445. cmdp->OpCode, cmdp->u.raw.direction));
  2446. /* evaluate command size */
  2447. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2448. }
  2449. } else {
  2450. page = virt_to_page(scp->sense_buffer);
  2451. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2452. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2453. 16,PCI_DMA_FROMDEVICE);
  2454. cmndinfo->sense_paddr = sense_paddr;
  2455. cmdp->OpCode = GDT_WRITE; /* always */
  2456. cmdp->BoardNode = LOCALBOARD;
  2457. if (mode64) {
  2458. cmdp->u.raw64.reserved = 0;
  2459. cmdp->u.raw64.mdisc_time = 0;
  2460. cmdp->u.raw64.mcon_time = 0;
  2461. cmdp->u.raw64.clen = scp->cmd_len;
  2462. cmdp->u.raw64.target = t;
  2463. cmdp->u.raw64.lun = l;
  2464. cmdp->u.raw64.bus = b;
  2465. cmdp->u.raw64.priority = 0;
  2466. cmdp->u.raw64.sdlen = gdth_bufflen(scp);
  2467. cmdp->u.raw64.sense_len = 16;
  2468. cmdp->u.raw64.sense_data = sense_paddr;
  2469. cmdp->u.raw64.direction =
  2470. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2471. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2472. cmdp->u.raw64.sg_ranz = 0;
  2473. } else {
  2474. cmdp->u.raw.reserved = 0;
  2475. cmdp->u.raw.mdisc_time = 0;
  2476. cmdp->u.raw.mcon_time = 0;
  2477. cmdp->u.raw.clen = scp->cmd_len;
  2478. cmdp->u.raw.target = t;
  2479. cmdp->u.raw.lun = l;
  2480. cmdp->u.raw.bus = b;
  2481. cmdp->u.raw.priority = 0;
  2482. cmdp->u.raw.link_p = 0;
  2483. cmdp->u.raw.sdlen = gdth_bufflen(scp);
  2484. cmdp->u.raw.sense_len = 16;
  2485. cmdp->u.raw.sense_data = sense_paddr;
  2486. cmdp->u.raw.direction =
  2487. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2488. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2489. cmdp->u.raw.sg_ranz = 0;
  2490. }
  2491. if (gdth_bufflen(scp)) {
  2492. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2493. sgcnt = pci_map_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  2494. cmndinfo->dma_dir);
  2495. if (mode64) {
  2496. struct scatterlist *sl;
  2497. cmdp->u.raw64.sdata = (ulong64)-1;
  2498. cmdp->u.raw64.sg_ranz = sgcnt;
  2499. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2500. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2501. #ifdef GDTH_DMA_STATISTICS
  2502. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2503. ha->dma64_cnt++;
  2504. else
  2505. ha->dma32_cnt++;
  2506. #endif
  2507. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2508. }
  2509. } else {
  2510. struct scatterlist *sl;
  2511. cmdp->u.raw.sdata = 0xffffffff;
  2512. cmdp->u.raw.sg_ranz = sgcnt;
  2513. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2514. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2515. #ifdef GDTH_DMA_STATISTICS
  2516. ha->dma32_cnt++;
  2517. #endif
  2518. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2519. }
  2520. }
  2521. #ifdef GDTH_STATISTICS
  2522. if (max_sg < sgcnt) {
  2523. max_sg = sgcnt;
  2524. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2525. }
  2526. #endif
  2527. }
  2528. if (mode64) {
  2529. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2530. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2531. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2532. cmdp->u.raw64.sg_lst[0].sg_len));
  2533. /* evaluate command size */
  2534. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2535. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2536. } else {
  2537. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2538. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2539. cmdp->u.raw.sg_lst[0].sg_ptr,
  2540. cmdp->u.raw.sg_lst[0].sg_len));
  2541. /* evaluate command size */
  2542. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2543. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2544. }
  2545. }
  2546. /* check space */
  2547. if (ha->cmd_len & 3)
  2548. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2549. if (ha->cmd_cnt > 0) {
  2550. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2551. ha->ic_all_size) {
  2552. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2553. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2554. return 0;
  2555. }
  2556. }
  2557. /* copy command */
  2558. gdth_copy_command(ha);
  2559. return cmd_index;
  2560. }
  2561. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2562. {
  2563. register gdth_cmd_str *cmdp;
  2564. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2565. int cmd_index;
  2566. cmdp= ha->pccb;
  2567. TRACE2(("gdth_special_cmd(): "));
  2568. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2569. return 0;
  2570. *cmdp = *cmndinfo->internal_cmd_str;
  2571. cmdp->RequestBuffer = scp;
  2572. /* search free command index */
  2573. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2574. TRACE(("GDT: No free command index found\n"));
  2575. return 0;
  2576. }
  2577. /* if it's the first command, set command semaphore */
  2578. if (ha->cmd_cnt == 0)
  2579. gdth_set_sema0(ha);
  2580. /* evaluate command size, check space */
  2581. if (cmdp->OpCode == GDT_IOCTL) {
  2582. TRACE2(("IOCTL\n"));
  2583. ha->cmd_len =
  2584. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2585. } else if (cmdp->Service == CACHESERVICE) {
  2586. TRACE2(("cache command %d\n",cmdp->OpCode));
  2587. if (ha->cache_feat & GDT_64BIT)
  2588. ha->cmd_len =
  2589. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2590. else
  2591. ha->cmd_len =
  2592. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2593. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2594. TRACE2(("raw command %d\n",cmdp->OpCode));
  2595. if (ha->raw_feat & GDT_64BIT)
  2596. ha->cmd_len =
  2597. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2598. else
  2599. ha->cmd_len =
  2600. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2601. }
  2602. if (ha->cmd_len & 3)
  2603. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2604. if (ha->cmd_cnt > 0) {
  2605. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2606. ha->ic_all_size) {
  2607. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2608. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2609. return 0;
  2610. }
  2611. }
  2612. /* copy command */
  2613. gdth_copy_command(ha);
  2614. return cmd_index;
  2615. }
  2616. /* Controller event handling functions */
  2617. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2618. ushort idx, gdth_evt_data *evt)
  2619. {
  2620. gdth_evt_str *e;
  2621. struct timeval tv;
  2622. /* no GDTH_LOCK_HA() ! */
  2623. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2624. if (source == 0) /* no source -> no event */
  2625. return NULL;
  2626. if (ebuffer[elastidx].event_source == source &&
  2627. ebuffer[elastidx].event_idx == idx &&
  2628. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2629. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2630. (char *)&evt->eu, evt->size)) ||
  2631. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2632. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2633. (char *)&evt->event_string)))) {
  2634. e = &ebuffer[elastidx];
  2635. do_gettimeofday(&tv);
  2636. e->last_stamp = tv.tv_sec;
  2637. ++e->same_count;
  2638. } else {
  2639. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2640. ++elastidx;
  2641. if (elastidx == MAX_EVENTS)
  2642. elastidx = 0;
  2643. if (elastidx == eoldidx) { /* reached mark ? */
  2644. ++eoldidx;
  2645. if (eoldidx == MAX_EVENTS)
  2646. eoldidx = 0;
  2647. }
  2648. }
  2649. e = &ebuffer[elastidx];
  2650. e->event_source = source;
  2651. e->event_idx = idx;
  2652. do_gettimeofday(&tv);
  2653. e->first_stamp = e->last_stamp = tv.tv_sec;
  2654. e->same_count = 1;
  2655. e->event_data = *evt;
  2656. e->application = 0;
  2657. }
  2658. return e;
  2659. }
  2660. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2661. {
  2662. gdth_evt_str *e;
  2663. int eindex;
  2664. ulong flags;
  2665. TRACE2(("gdth_read_event() handle %d\n", handle));
  2666. spin_lock_irqsave(&ha->smp_lock, flags);
  2667. if (handle == -1)
  2668. eindex = eoldidx;
  2669. else
  2670. eindex = handle;
  2671. estr->event_source = 0;
  2672. if (eindex >= MAX_EVENTS) {
  2673. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2674. return eindex;
  2675. }
  2676. e = &ebuffer[eindex];
  2677. if (e->event_source != 0) {
  2678. if (eindex != elastidx) {
  2679. if (++eindex == MAX_EVENTS)
  2680. eindex = 0;
  2681. } else {
  2682. eindex = -1;
  2683. }
  2684. memcpy(estr, e, sizeof(gdth_evt_str));
  2685. }
  2686. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2687. return eindex;
  2688. }
  2689. static void gdth_readapp_event(gdth_ha_str *ha,
  2690. unchar application, gdth_evt_str *estr)
  2691. {
  2692. gdth_evt_str *e;
  2693. int eindex;
  2694. ulong flags;
  2695. unchar found = FALSE;
  2696. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2697. spin_lock_irqsave(&ha->smp_lock, flags);
  2698. eindex = eoldidx;
  2699. for (;;) {
  2700. e = &ebuffer[eindex];
  2701. if (e->event_source == 0)
  2702. break;
  2703. if ((e->application & application) == 0) {
  2704. e->application |= application;
  2705. found = TRUE;
  2706. break;
  2707. }
  2708. if (eindex == elastidx)
  2709. break;
  2710. if (++eindex == MAX_EVENTS)
  2711. eindex = 0;
  2712. }
  2713. if (found)
  2714. memcpy(estr, e, sizeof(gdth_evt_str));
  2715. else
  2716. estr->event_source = 0;
  2717. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2718. }
  2719. static void gdth_clear_events(void)
  2720. {
  2721. TRACE(("gdth_clear_events()"));
  2722. eoldidx = elastidx = 0;
  2723. ebuffer[0].event_source = 0;
  2724. }
  2725. /* SCSI interface functions */
  2726. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2727. int gdth_from_wait, int* pIndex)
  2728. {
  2729. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2730. gdt6_dpram_str __iomem *dp6_ptr;
  2731. gdt2_dpram_str __iomem *dp2_ptr;
  2732. Scsi_Cmnd *scp;
  2733. int rval, i;
  2734. unchar IStatus;
  2735. ushort Service;
  2736. ulong flags = 0;
  2737. #ifdef INT_COAL
  2738. int coalesced = FALSE;
  2739. int next = FALSE;
  2740. gdth_coal_status *pcs = NULL;
  2741. int act_int_coal = 0;
  2742. #endif
  2743. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2744. /* if polling and not from gdth_wait() -> return */
  2745. if (gdth_polling) {
  2746. if (!gdth_from_wait) {
  2747. return IRQ_HANDLED;
  2748. }
  2749. }
  2750. if (!gdth_polling)
  2751. spin_lock_irqsave(&ha->smp_lock, flags);
  2752. /* search controller */
  2753. IStatus = gdth_get_status(ha);
  2754. if (IStatus == 0) {
  2755. /* spurious interrupt */
  2756. if (!gdth_polling)
  2757. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2758. return IRQ_HANDLED;
  2759. }
  2760. #ifdef GDTH_STATISTICS
  2761. ++act_ints;
  2762. #endif
  2763. #ifdef INT_COAL
  2764. /* See if the fw is returning coalesced status */
  2765. if (IStatus == COALINDEX) {
  2766. /* Coalesced status. Setup the initial status
  2767. buffer pointer and flags */
  2768. pcs = ha->coal_stat;
  2769. coalesced = TRUE;
  2770. next = TRUE;
  2771. }
  2772. do {
  2773. if (coalesced) {
  2774. /* For coalesced requests all status
  2775. information is found in the status buffer */
  2776. IStatus = (unchar)(pcs->status & 0xff);
  2777. }
  2778. #endif
  2779. if (ha->type == GDT_EISA) {
  2780. if (IStatus & 0x80) { /* error flag */
  2781. IStatus &= ~0x80;
  2782. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2783. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2784. } else /* no error */
  2785. ha->status = S_OK;
  2786. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2787. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2788. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2789. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2790. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2791. } else if (ha->type == GDT_ISA) {
  2792. dp2_ptr = ha->brd;
  2793. if (IStatus & 0x80) { /* error flag */
  2794. IStatus &= ~0x80;
  2795. ha->status = readw(&dp2_ptr->u.ic.Status);
  2796. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2797. } else /* no error */
  2798. ha->status = S_OK;
  2799. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2800. ha->service = readw(&dp2_ptr->u.ic.Service);
  2801. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2802. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2803. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2804. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2805. } else if (ha->type == GDT_PCI) {
  2806. dp6_ptr = ha->brd;
  2807. if (IStatus & 0x80) { /* error flag */
  2808. IStatus &= ~0x80;
  2809. ha->status = readw(&dp6_ptr->u.ic.Status);
  2810. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2811. } else /* no error */
  2812. ha->status = S_OK;
  2813. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2814. ha->service = readw(&dp6_ptr->u.ic.Service);
  2815. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2816. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2817. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2818. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2819. } else if (ha->type == GDT_PCINEW) {
  2820. if (IStatus & 0x80) { /* error flag */
  2821. IStatus &= ~0x80;
  2822. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2823. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2824. } else
  2825. ha->status = S_OK;
  2826. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2827. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2828. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2829. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2830. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2831. } else if (ha->type == GDT_PCIMPR) {
  2832. dp6m_ptr = ha->brd;
  2833. if (IStatus & 0x80) { /* error flag */
  2834. IStatus &= ~0x80;
  2835. #ifdef INT_COAL
  2836. if (coalesced)
  2837. ha->status = pcs->ext_status & 0xffff;
  2838. else
  2839. #endif
  2840. ha->status = readw(&dp6m_ptr->i960r.status);
  2841. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2842. } else /* no error */
  2843. ha->status = S_OK;
  2844. #ifdef INT_COAL
  2845. /* get information */
  2846. if (coalesced) {
  2847. ha->info = pcs->info0;
  2848. ha->info2 = pcs->info1;
  2849. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2850. } else
  2851. #endif
  2852. {
  2853. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2854. ha->service = readw(&dp6m_ptr->i960r.service);
  2855. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2856. }
  2857. /* event string */
  2858. if (IStatus == ASYNCINDEX) {
  2859. if (ha->service != SCREENSERVICE &&
  2860. (ha->fw_vers & 0xff) >= 0x1a) {
  2861. ha->dvr.severity = readb
  2862. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2863. for (i = 0; i < 256; ++i) {
  2864. ha->dvr.event_string[i] = readb
  2865. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2866. if (ha->dvr.event_string[i] == 0)
  2867. break;
  2868. }
  2869. }
  2870. }
  2871. #ifdef INT_COAL
  2872. /* Make sure that non coalesced interrupts get cleared
  2873. before being handled by gdth_async_event/gdth_sync_event */
  2874. if (!coalesced)
  2875. #endif
  2876. {
  2877. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2878. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2879. }
  2880. } else {
  2881. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2882. if (!gdth_polling)
  2883. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2884. return IRQ_HANDLED;
  2885. }
  2886. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2887. IStatus,ha->status,ha->info));
  2888. if (gdth_from_wait) {
  2889. *pIndex = (int)IStatus;
  2890. }
  2891. if (IStatus == ASYNCINDEX) {
  2892. TRACE2(("gdth_interrupt() async. event\n"));
  2893. gdth_async_event(ha);
  2894. if (!gdth_polling)
  2895. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2896. gdth_next(ha);
  2897. return IRQ_HANDLED;
  2898. }
  2899. if (IStatus == SPEZINDEX) {
  2900. TRACE2(("Service unknown or not initialized !\n"));
  2901. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2902. ha->dvr.eu.driver.ionode = ha->hanum;
  2903. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2904. if (!gdth_polling)
  2905. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2906. return IRQ_HANDLED;
  2907. }
  2908. scp = ha->cmd_tab[IStatus-2].cmnd;
  2909. Service = ha->cmd_tab[IStatus-2].service;
  2910. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2911. if (scp == UNUSED_CMND) {
  2912. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2913. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2914. ha->dvr.eu.driver.ionode = ha->hanum;
  2915. ha->dvr.eu.driver.index = IStatus;
  2916. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2917. if (!gdth_polling)
  2918. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2919. return IRQ_HANDLED;
  2920. }
  2921. if (scp == INTERNAL_CMND) {
  2922. TRACE(("gdth_interrupt() answer to internal command\n"));
  2923. if (!gdth_polling)
  2924. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2925. return IRQ_HANDLED;
  2926. }
  2927. TRACE(("gdth_interrupt() sync. status\n"));
  2928. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2929. if (!gdth_polling)
  2930. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2931. if (rval == 2) {
  2932. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2933. } else if (rval == 1) {
  2934. gdth_scsi_done(scp);
  2935. }
  2936. #ifdef INT_COAL
  2937. if (coalesced) {
  2938. /* go to the next status in the status buffer */
  2939. ++pcs;
  2940. #ifdef GDTH_STATISTICS
  2941. ++act_int_coal;
  2942. if (act_int_coal > max_int_coal) {
  2943. max_int_coal = act_int_coal;
  2944. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2945. }
  2946. #endif
  2947. /* see if there is another status */
  2948. if (pcs->status == 0)
  2949. /* Stop the coalesce loop */
  2950. next = FALSE;
  2951. }
  2952. } while (next);
  2953. /* coalescing only for new GDT_PCIMPR controllers available */
  2954. if (ha->type == GDT_PCIMPR && coalesced) {
  2955. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2956. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2957. }
  2958. #endif
  2959. gdth_next(ha);
  2960. return IRQ_HANDLED;
  2961. }
  2962. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2963. {
  2964. gdth_ha_str *ha = dev_id;
  2965. return __gdth_interrupt(ha, false, NULL);
  2966. }
  2967. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2968. Scsi_Cmnd *scp)
  2969. {
  2970. gdth_msg_str *msg;
  2971. gdth_cmd_str *cmdp;
  2972. unchar b, t;
  2973. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2974. cmdp = ha->pccb;
  2975. TRACE(("gdth_sync_event() serv %d status %d\n",
  2976. service,ha->status));
  2977. if (service == SCREENSERVICE) {
  2978. msg = ha->pmsg;
  2979. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2980. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2981. if (msg->msg_len > MSGLEN+1)
  2982. msg->msg_len = MSGLEN+1;
  2983. if (msg->msg_len)
  2984. if (!(msg->msg_answer && msg->msg_ext)) {
  2985. msg->msg_text[msg->msg_len] = '\0';
  2986. printk("%s",msg->msg_text);
  2987. }
  2988. if (msg->msg_ext && !msg->msg_answer) {
  2989. while (gdth_test_busy(ha))
  2990. gdth_delay(0);
  2991. cmdp->Service = SCREENSERVICE;
  2992. cmdp->RequestBuffer = SCREEN_CMND;
  2993. gdth_get_cmd_index(ha);
  2994. gdth_set_sema0(ha);
  2995. cmdp->OpCode = GDT_READ;
  2996. cmdp->BoardNode = LOCALBOARD;
  2997. cmdp->u.screen.reserved = 0;
  2998. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2999. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3000. ha->cmd_offs_dpmem = 0;
  3001. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3002. + sizeof(ulong64);
  3003. ha->cmd_cnt = 0;
  3004. gdth_copy_command(ha);
  3005. gdth_release_event(ha);
  3006. return 0;
  3007. }
  3008. if (msg->msg_answer && msg->msg_alen) {
  3009. /* default answers (getchar() not possible) */
  3010. if (msg->msg_alen == 1) {
  3011. msg->msg_alen = 0;
  3012. msg->msg_len = 1;
  3013. msg->msg_text[0] = 0;
  3014. } else {
  3015. msg->msg_alen -= 2;
  3016. msg->msg_len = 2;
  3017. msg->msg_text[0] = 1;
  3018. msg->msg_text[1] = 0;
  3019. }
  3020. msg->msg_ext = 0;
  3021. msg->msg_answer = 0;
  3022. while (gdth_test_busy(ha))
  3023. gdth_delay(0);
  3024. cmdp->Service = SCREENSERVICE;
  3025. cmdp->RequestBuffer = SCREEN_CMND;
  3026. gdth_get_cmd_index(ha);
  3027. gdth_set_sema0(ha);
  3028. cmdp->OpCode = GDT_WRITE;
  3029. cmdp->BoardNode = LOCALBOARD;
  3030. cmdp->u.screen.reserved = 0;
  3031. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3032. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3033. ha->cmd_offs_dpmem = 0;
  3034. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3035. + sizeof(ulong64);
  3036. ha->cmd_cnt = 0;
  3037. gdth_copy_command(ha);
  3038. gdth_release_event(ha);
  3039. return 0;
  3040. }
  3041. printk("\n");
  3042. } else {
  3043. b = scp->device->channel;
  3044. t = scp->device->id;
  3045. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  3046. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3047. }
  3048. /* cache or raw service */
  3049. if (ha->status == S_BSY) {
  3050. TRACE2(("Controller busy -> retry !\n"));
  3051. if (cmndinfo->OpCode == GDT_MOUNT)
  3052. cmndinfo->OpCode = GDT_CLUST_INFO;
  3053. /* retry */
  3054. return 2;
  3055. }
  3056. if (gdth_bufflen(scp))
  3057. pci_unmap_sg(ha->pdev, gdth_sglist(scp), gdth_sg_count(scp),
  3058. cmndinfo->dma_dir);
  3059. if (cmndinfo->sense_paddr)
  3060. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3061. PCI_DMA_FROMDEVICE);
  3062. if (ha->status == S_OK) {
  3063. cmndinfo->status = S_OK;
  3064. cmndinfo->info = ha->info;
  3065. if (cmndinfo->OpCode != -1) {
  3066. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3067. cmndinfo->OpCode));
  3068. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3069. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3070. ha->hdr[t].cluster_type = (unchar)ha->info;
  3071. if (!(ha->hdr[t].cluster_type &
  3072. CLUSTER_MOUNTED)) {
  3073. /* NOT MOUNTED -> MOUNT */
  3074. cmndinfo->OpCode = GDT_MOUNT;
  3075. if (ha->hdr[t].cluster_type &
  3076. CLUSTER_RESERVED) {
  3077. /* cluster drive RESERVED (on the other node) */
  3078. cmndinfo->phase = -2; /* reservation conflict */
  3079. }
  3080. } else {
  3081. cmndinfo->OpCode = -1;
  3082. }
  3083. } else {
  3084. if (cmndinfo->OpCode == GDT_MOUNT) {
  3085. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3086. ha->hdr[t].media_changed = TRUE;
  3087. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3088. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3089. ha->hdr[t].media_changed = TRUE;
  3090. }
  3091. cmndinfo->OpCode = -1;
  3092. }
  3093. /* retry */
  3094. cmndinfo->priority = HIGH_PRI;
  3095. return 2;
  3096. } else {
  3097. /* RESERVE/RELEASE ? */
  3098. if (scp->cmnd[0] == RESERVE) {
  3099. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3100. } else if (scp->cmnd[0] == RELEASE) {
  3101. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3102. }
  3103. scp->result = DID_OK << 16;
  3104. scp->sense_buffer[0] = 0;
  3105. }
  3106. } else {
  3107. cmndinfo->status = ha->status;
  3108. cmndinfo->info = ha->info;
  3109. if (cmndinfo->OpCode != -1) {
  3110. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3111. cmndinfo->OpCode, ha->status));
  3112. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3113. cmndinfo->OpCode == GDT_SCAN_END) {
  3114. cmndinfo->OpCode = -1;
  3115. /* retry */
  3116. cmndinfo->priority = HIGH_PRI;
  3117. return 2;
  3118. }
  3119. memset((char*)scp->sense_buffer,0,16);
  3120. scp->sense_buffer[0] = 0x70;
  3121. scp->sense_buffer[2] = NOT_READY;
  3122. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3123. } else if (service == CACHESERVICE) {
  3124. if (ha->status == S_CACHE_UNKNOWN &&
  3125. (ha->hdr[t].cluster_type &
  3126. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3127. /* bus reset -> force GDT_CLUST_INFO */
  3128. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3129. }
  3130. memset((char*)scp->sense_buffer,0,16);
  3131. if (ha->status == (ushort)S_CACHE_RESERV) {
  3132. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3133. } else {
  3134. scp->sense_buffer[0] = 0x70;
  3135. scp->sense_buffer[2] = NOT_READY;
  3136. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3137. }
  3138. if (!cmndinfo->internal_command) {
  3139. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3140. ha->dvr.eu.sync.ionode = ha->hanum;
  3141. ha->dvr.eu.sync.service = service;
  3142. ha->dvr.eu.sync.status = ha->status;
  3143. ha->dvr.eu.sync.info = ha->info;
  3144. ha->dvr.eu.sync.hostdrive = t;
  3145. if (ha->status >= 0x8000)
  3146. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3147. else
  3148. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3149. }
  3150. } else {
  3151. /* sense buffer filled from controller firmware (DMA) */
  3152. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3153. scp->result = DID_BAD_TARGET << 16;
  3154. } else {
  3155. scp->result = (DID_OK << 16) | ha->info;
  3156. }
  3157. }
  3158. }
  3159. if (!cmndinfo->wait_for_completion)
  3160. cmndinfo->wait_for_completion++;
  3161. else
  3162. return 1;
  3163. }
  3164. return 0;
  3165. }
  3166. static char *async_cache_tab[] = {
  3167. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3168. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3169. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3170. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3171. /* 2*/ "\005\000\002\006\004"
  3172. "GDT HA %u, Host Drive %lu not ready",
  3173. /* 3*/ "\005\000\002\006\004"
  3174. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3175. /* 4*/ "\005\000\002\006\004"
  3176. "GDT HA %u, mirror update on Host Drive %lu failed",
  3177. /* 5*/ "\005\000\002\006\004"
  3178. "GDT HA %u, Mirror Drive %lu failed",
  3179. /* 6*/ "\005\000\002\006\004"
  3180. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3181. /* 7*/ "\005\000\002\006\004"
  3182. "GDT HA %u, Host Drive %lu write protected",
  3183. /* 8*/ "\005\000\002\006\004"
  3184. "GDT HA %u, media changed in Host Drive %lu",
  3185. /* 9*/ "\005\000\002\006\004"
  3186. "GDT HA %u, Host Drive %lu is offline",
  3187. /*10*/ "\005\000\002\006\004"
  3188. "GDT HA %u, media change of Mirror Drive %lu",
  3189. /*11*/ "\005\000\002\006\004"
  3190. "GDT HA %u, Mirror Drive %lu is write protected",
  3191. /*12*/ "\005\000\002\006\004"
  3192. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3193. /*13*/ "\007\000\002\006\002\010\002"
  3194. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3195. /*14*/ "\005\000\002\006\002"
  3196. "GDT HA %u, Array Drive %u: FAIL state entered",
  3197. /*15*/ "\005\000\002\006\002"
  3198. "GDT HA %u, Array Drive %u: error",
  3199. /*16*/ "\007\000\002\006\002\010\002"
  3200. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3201. /*17*/ "\005\000\002\006\002"
  3202. "GDT HA %u, Array Drive %u: parity build failed",
  3203. /*18*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3205. /*19*/ "\005\000\002\010\002"
  3206. "GDT HA %u, Test of Hot Fix %u failed",
  3207. /*20*/ "\005\000\002\006\002"
  3208. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3209. /*21*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3211. /*22*/ "\007\000\002\006\002\010\002"
  3212. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3213. /*23*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3215. /*24*/ "\005\000\002\010\002"
  3216. "GDT HA %u, mirror update on Cache Drive %u completed",
  3217. /*25*/ "\005\000\002\010\002"
  3218. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3219. /*26*/ "\005\000\002\006\002"
  3220. "GDT HA %u, Array Drive %u: drive rebuild started",
  3221. /*27*/ "\005\000\002\012\001"
  3222. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3223. /*28*/ "\005\000\002\012\001"
  3224. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3225. /*29*/ "\007\000\002\012\001\013\001"
  3226. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3227. /*30*/ "\007\000\002\012\001\013\001"
  3228. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3229. /*31*/ "\007\000\002\012\001\013\001"
  3230. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3231. /*32*/ "\007\000\002\012\001\013\001"
  3232. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3233. /*33*/ "\007\000\002\012\001\013\001"
  3234. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3235. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3236. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3237. /*35*/ "\007\000\002\012\001\013\001"
  3238. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3239. /*36*/ "\007\000\002\012\001\013\001"
  3240. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3241. /*37*/ "\007\000\002\012\001\006\004"
  3242. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3243. /*38*/ "\007\000\002\012\001\013\001"
  3244. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3245. /*39*/ "\007\000\002\012\001\013\001"
  3246. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3247. /*40*/ "\007\000\002\012\001\013\001"
  3248. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3249. /*41*/ "\007\000\002\012\001\013\001"
  3250. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3251. /*42*/ "\005\000\002\006\002"
  3252. "GDT HA %u, Array Drive %u: drive build started",
  3253. /*43*/ "\003\000\002"
  3254. "GDT HA %u, DRAM parity error detected",
  3255. /*44*/ "\005\000\002\006\002"
  3256. "GDT HA %u, Mirror Drive %u: update started",
  3257. /*45*/ "\007\000\002\006\002\010\002"
  3258. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3259. /*46*/ "\005\000\002\006\002"
  3260. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3261. /*47*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3263. /*48*/ "\005\000\002\006\002"
  3264. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3265. /*49*/ "\005\000\002\006\002"
  3266. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3267. /*50*/ "\007\000\002\012\001\013\001"
  3268. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3269. /*51*/ "\005\000\002\006\002"
  3270. "GDT HA %u, Array Drive %u: expand started",
  3271. /*52*/ "\005\000\002\006\002"
  3272. "GDT HA %u, Array Drive %u: expand finished successfully",
  3273. /*53*/ "\005\000\002\006\002"
  3274. "GDT HA %u, Array Drive %u: expand failed",
  3275. /*54*/ "\003\000\002"
  3276. "GDT HA %u, CPU temperature critical",
  3277. /*55*/ "\003\000\002"
  3278. "GDT HA %u, CPU temperature OK",
  3279. /*56*/ "\005\000\002\006\004"
  3280. "GDT HA %u, Host drive %lu created",
  3281. /*57*/ "\005\000\002\006\002"
  3282. "GDT HA %u, Array Drive %u: expand restarted",
  3283. /*58*/ "\005\000\002\006\002"
  3284. "GDT HA %u, Array Drive %u: expand stopped",
  3285. /*59*/ "\005\000\002\010\002"
  3286. "GDT HA %u, Mirror Drive %u: drive build quited",
  3287. /*60*/ "\005\000\002\006\002"
  3288. "GDT HA %u, Array Drive %u: parity build quited",
  3289. /*61*/ "\005\000\002\006\002"
  3290. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3291. /*62*/ "\005\000\002\006\002"
  3292. "GDT HA %u, Array Drive %u: parity verify started",
  3293. /*63*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: parity verify done",
  3295. /*64*/ "\005\000\002\006\002"
  3296. "GDT HA %u, Array Drive %u: parity verify failed",
  3297. /*65*/ "\005\000\002\006\002"
  3298. "GDT HA %u, Array Drive %u: parity error detected",
  3299. /*66*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: parity verify quited",
  3301. /*67*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Host Drive %u reserved",
  3303. /*68*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Host Drive %u mounted and released",
  3305. /*69*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Host Drive %u released",
  3307. /*70*/ "\003\000\002"
  3308. "GDT HA %u, DRAM error detected and corrected with ECC",
  3309. /*71*/ "\003\000\002"
  3310. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3311. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3312. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3313. /*73*/ "\005\000\002\006\002"
  3314. "GDT HA %u, Host drive %u resetted locally",
  3315. /*74*/ "\005\000\002\006\002"
  3316. "GDT HA %u, Host drive %u resetted remotely",
  3317. /*75*/ "\003\000\002"
  3318. "GDT HA %u, async. status 75 unknown",
  3319. };
  3320. static int gdth_async_event(gdth_ha_str *ha)
  3321. {
  3322. gdth_cmd_str *cmdp;
  3323. int cmd_index;
  3324. cmdp= ha->pccb;
  3325. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3326. ha->hanum, ha->service));
  3327. if (ha->service == SCREENSERVICE) {
  3328. if (ha->status == MSG_REQUEST) {
  3329. while (gdth_test_busy(ha))
  3330. gdth_delay(0);
  3331. cmdp->Service = SCREENSERVICE;
  3332. cmdp->RequestBuffer = SCREEN_CMND;
  3333. cmd_index = gdth_get_cmd_index(ha);
  3334. gdth_set_sema0(ha);
  3335. cmdp->OpCode = GDT_READ;
  3336. cmdp->BoardNode = LOCALBOARD;
  3337. cmdp->u.screen.reserved = 0;
  3338. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3339. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3340. ha->cmd_offs_dpmem = 0;
  3341. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3342. + sizeof(ulong64);
  3343. ha->cmd_cnt = 0;
  3344. gdth_copy_command(ha);
  3345. if (ha->type == GDT_EISA)
  3346. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3347. else if (ha->type == GDT_ISA)
  3348. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3349. else
  3350. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3351. (ushort)((ha->brd_phys>>3)&0x1f));
  3352. gdth_release_event(ha);
  3353. }
  3354. } else {
  3355. if (ha->type == GDT_PCIMPR &&
  3356. (ha->fw_vers & 0xff) >= 0x1a) {
  3357. ha->dvr.size = 0;
  3358. ha->dvr.eu.async.ionode = ha->hanum;
  3359. ha->dvr.eu.async.status = ha->status;
  3360. /* severity and event_string already set! */
  3361. } else {
  3362. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3363. ha->dvr.eu.async.ionode = ha->hanum;
  3364. ha->dvr.eu.async.service = ha->service;
  3365. ha->dvr.eu.async.status = ha->status;
  3366. ha->dvr.eu.async.info = ha->info;
  3367. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3368. }
  3369. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3370. gdth_log_event( &ha->dvr, NULL );
  3371. /* new host drive from expand? */
  3372. if (ha->service == CACHESERVICE && ha->status == 56) {
  3373. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3374. (ushort)ha->info));
  3375. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3376. }
  3377. }
  3378. return 1;
  3379. }
  3380. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3381. {
  3382. gdth_stackframe stack;
  3383. char *f = NULL;
  3384. int i,j;
  3385. TRACE2(("gdth_log_event()\n"));
  3386. if (dvr->size == 0) {
  3387. if (buffer == NULL) {
  3388. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3389. } else {
  3390. sprintf(buffer,"Adapter %d: %s\n",
  3391. dvr->eu.async.ionode,dvr->event_string);
  3392. }
  3393. } else if (dvr->eu.async.service == CACHESERVICE &&
  3394. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3395. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3396. dvr->eu.async.status));
  3397. f = async_cache_tab[dvr->eu.async.status];
  3398. /* i: parameter to push, j: stack element to fill */
  3399. for (j=0,i=1; i < f[0]; i+=2) {
  3400. switch (f[i+1]) {
  3401. case 4:
  3402. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3403. break;
  3404. case 2:
  3405. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3406. break;
  3407. case 1:
  3408. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3409. break;
  3410. default:
  3411. break;
  3412. }
  3413. }
  3414. if (buffer == NULL) {
  3415. printk(&f[(int)f[0]],stack);
  3416. printk("\n");
  3417. } else {
  3418. sprintf(buffer,&f[(int)f[0]],stack);
  3419. }
  3420. } else {
  3421. if (buffer == NULL) {
  3422. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3423. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3424. } else {
  3425. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3426. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3427. }
  3428. }
  3429. }
  3430. #ifdef GDTH_STATISTICS
  3431. static void gdth_timeout(ulong data)
  3432. {
  3433. ulong32 i;
  3434. Scsi_Cmnd *nscp;
  3435. gdth_ha_str *ha;
  3436. ulong flags;
  3437. BUG_ON(list_empty(&gdth_instances));
  3438. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3439. spin_lock_irqsave(&ha->smp_lock, flags);
  3440. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3441. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3442. ++act_stats;
  3443. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3444. ++act_rq;
  3445. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3446. act_ints, act_ios, act_stats, act_rq));
  3447. act_ints = act_ios = 0;
  3448. gdth_timer.expires = jiffies + 30 * HZ;
  3449. add_timer(&gdth_timer);
  3450. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3451. }
  3452. #endif
  3453. static void __init internal_setup(char *str,int *ints)
  3454. {
  3455. int i, argc;
  3456. char *cur_str, *argv;
  3457. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3458. str ? str:"NULL", ints ? ints[0]:0));
  3459. /* read irq[] from ints[] */
  3460. if (ints) {
  3461. argc = ints[0];
  3462. if (argc > 0) {
  3463. if (argc > MAXHA)
  3464. argc = MAXHA;
  3465. for (i = 0; i < argc; ++i)
  3466. irq[i] = ints[i+1];
  3467. }
  3468. }
  3469. /* analyse string */
  3470. argv = str;
  3471. while (argv && (cur_str = strchr(argv, ':'))) {
  3472. int val = 0, c = *++cur_str;
  3473. if (c == 'n' || c == 'N')
  3474. val = 0;
  3475. else if (c == 'y' || c == 'Y')
  3476. val = 1;
  3477. else
  3478. val = (int)simple_strtoul(cur_str, NULL, 0);
  3479. if (!strncmp(argv, "disable:", 8))
  3480. disable = val;
  3481. else if (!strncmp(argv, "reserve_mode:", 13))
  3482. reserve_mode = val;
  3483. else if (!strncmp(argv, "reverse_scan:", 13))
  3484. reverse_scan = val;
  3485. else if (!strncmp(argv, "hdr_channel:", 12))
  3486. hdr_channel = val;
  3487. else if (!strncmp(argv, "max_ids:", 8))
  3488. max_ids = val;
  3489. else if (!strncmp(argv, "rescan:", 7))
  3490. rescan = val;
  3491. else if (!strncmp(argv, "shared_access:", 14))
  3492. shared_access = val;
  3493. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3494. probe_eisa_isa = val;
  3495. else if (!strncmp(argv, "reserve_list:", 13)) {
  3496. reserve_list[0] = val;
  3497. for (i = 1; i < MAX_RES_ARGS; i++) {
  3498. cur_str = strchr(cur_str, ',');
  3499. if (!cur_str)
  3500. break;
  3501. if (!isdigit((int)*++cur_str)) {
  3502. --cur_str;
  3503. break;
  3504. }
  3505. reserve_list[i] =
  3506. (int)simple_strtoul(cur_str, NULL, 0);
  3507. }
  3508. if (!cur_str)
  3509. break;
  3510. argv = ++cur_str;
  3511. continue;
  3512. }
  3513. if ((argv = strchr(argv, ',')))
  3514. ++argv;
  3515. }
  3516. }
  3517. int __init option_setup(char *str)
  3518. {
  3519. int ints[MAXHA];
  3520. char *cur = str;
  3521. int i = 1;
  3522. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3523. while (cur && isdigit(*cur) && i <= MAXHA) {
  3524. ints[i++] = simple_strtoul(cur, NULL, 0);
  3525. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3526. }
  3527. ints[0] = i - 1;
  3528. internal_setup(cur, ints);
  3529. return 1;
  3530. }
  3531. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3532. {
  3533. TRACE2(("gdth_ctr_name()\n"));
  3534. if (ha->type == GDT_EISA) {
  3535. switch (ha->stype) {
  3536. case GDT3_ID:
  3537. return("GDT3000/3020");
  3538. case GDT3A_ID:
  3539. return("GDT3000A/3020A/3050A");
  3540. case GDT3B_ID:
  3541. return("GDT3000B/3010A");
  3542. }
  3543. } else if (ha->type == GDT_ISA) {
  3544. return("GDT2000/2020");
  3545. } else if (ha->type == GDT_PCI) {
  3546. switch (ha->pdev->device) {
  3547. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3548. return("GDT6000/6020/6050");
  3549. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3550. return("GDT6000B/6010");
  3551. }
  3552. }
  3553. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3554. return("");
  3555. }
  3556. static const char *gdth_info(struct Scsi_Host *shp)
  3557. {
  3558. gdth_ha_str *ha = shost_priv(shp);
  3559. TRACE2(("gdth_info()\n"));
  3560. return ((const char *)ha->binfo.type_string);
  3561. }
  3562. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3563. {
  3564. gdth_ha_str *ha = shost_priv(scp->device->host);
  3565. int i;
  3566. ulong flags;
  3567. Scsi_Cmnd *cmnd;
  3568. unchar b;
  3569. TRACE2(("gdth_eh_bus_reset()\n"));
  3570. b = scp->device->channel;
  3571. /* clear command tab */
  3572. spin_lock_irqsave(&ha->smp_lock, flags);
  3573. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3574. cmnd = ha->cmd_tab[i].cmnd;
  3575. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3576. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3577. }
  3578. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3579. if (b == ha->virt_bus) {
  3580. /* host drives */
  3581. for (i = 0; i < MAX_HDRIVES; ++i) {
  3582. if (ha->hdr[i].present) {
  3583. spin_lock_irqsave(&ha->smp_lock, flags);
  3584. gdth_polling = TRUE;
  3585. while (gdth_test_busy(ha))
  3586. gdth_delay(0);
  3587. if (gdth_internal_cmd(ha, CACHESERVICE,
  3588. GDT_CLUST_RESET, i, 0, 0))
  3589. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3590. gdth_polling = FALSE;
  3591. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3592. }
  3593. }
  3594. } else {
  3595. /* raw devices */
  3596. spin_lock_irqsave(&ha->smp_lock, flags);
  3597. for (i = 0; i < MAXID; ++i)
  3598. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3599. gdth_polling = TRUE;
  3600. while (gdth_test_busy(ha))
  3601. gdth_delay(0);
  3602. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3603. BUS_L2P(ha,b), 0, 0);
  3604. gdth_polling = FALSE;
  3605. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3606. }
  3607. return SUCCESS;
  3608. }
  3609. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3610. {
  3611. unchar b, t;
  3612. gdth_ha_str *ha = shost_priv(sdev->host);
  3613. struct scsi_device *sd;
  3614. unsigned capacity;
  3615. sd = sdev;
  3616. capacity = cap;
  3617. b = sd->channel;
  3618. t = sd->id;
  3619. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3620. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3621. /* raw device or host drive without mapping information */
  3622. TRACE2(("Evaluate mapping\n"));
  3623. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3624. } else {
  3625. ip[0] = ha->hdr[t].heads;
  3626. ip[1] = ha->hdr[t].secs;
  3627. ip[2] = capacity / ip[0] / ip[1];
  3628. }
  3629. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3630. ip[0],ip[1],ip[2]));
  3631. return 0;
  3632. }
  3633. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3634. void (*done)(struct scsi_cmnd *))
  3635. {
  3636. gdth_ha_str *ha = shost_priv(scp->device->host);
  3637. struct gdth_cmndinfo *cmndinfo;
  3638. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3639. cmndinfo = gdth_get_cmndinfo(ha);
  3640. BUG_ON(!cmndinfo);
  3641. scp->scsi_done = done;
  3642. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3643. cmndinfo->priority = DEFAULT_PRI;
  3644. gdth_set_bufflen(scp, scsi_bufflen(scp));
  3645. gdth_set_sg_count(scp, scsi_sg_count(scp));
  3646. gdth_set_sglist(scp, scsi_sglist(scp));
  3647. return __gdth_queuecommand(ha, scp, cmndinfo);
  3648. }
  3649. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3650. struct gdth_cmndinfo *cmndinfo)
  3651. {
  3652. scp->host_scribble = (unsigned char *)cmndinfo;
  3653. cmndinfo->wait_for_completion = 1;
  3654. cmndinfo->phase = -1;
  3655. cmndinfo->OpCode = -1;
  3656. #ifdef GDTH_STATISTICS
  3657. ++act_ios;
  3658. #endif
  3659. gdth_putq(ha, scp, cmndinfo->priority);
  3660. gdth_next(ha);
  3661. return 0;
  3662. }
  3663. static int gdth_open(struct inode *inode, struct file *filep)
  3664. {
  3665. gdth_ha_str *ha;
  3666. list_for_each_entry(ha, &gdth_instances, list) {
  3667. if (!ha->sdev)
  3668. ha->sdev = scsi_get_host_dev(ha->shost);
  3669. }
  3670. TRACE(("gdth_open()\n"));
  3671. return 0;
  3672. }
  3673. static int gdth_close(struct inode *inode, struct file *filep)
  3674. {
  3675. TRACE(("gdth_close()\n"));
  3676. return 0;
  3677. }
  3678. static int ioc_event(void __user *arg)
  3679. {
  3680. gdth_ioctl_event evt;
  3681. gdth_ha_str *ha;
  3682. ulong flags;
  3683. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3684. return -EFAULT;
  3685. ha = gdth_find_ha(evt.ionode);
  3686. if (!ha)
  3687. return -EFAULT;
  3688. if (evt.erase == 0xff) {
  3689. if (evt.event.event_source == ES_TEST)
  3690. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3691. else if (evt.event.event_source == ES_DRIVER)
  3692. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3693. else if (evt.event.event_source == ES_SYNC)
  3694. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3695. else
  3696. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3697. spin_lock_irqsave(&ha->smp_lock, flags);
  3698. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3699. &evt.event.event_data);
  3700. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3701. } else if (evt.erase == 0xfe) {
  3702. gdth_clear_events();
  3703. } else if (evt.erase == 0) {
  3704. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3705. } else {
  3706. gdth_readapp_event(ha, evt.erase, &evt.event);
  3707. }
  3708. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3709. return -EFAULT;
  3710. return 0;
  3711. }
  3712. static int ioc_lockdrv(void __user *arg)
  3713. {
  3714. gdth_ioctl_lockdrv ldrv;
  3715. unchar i, j;
  3716. ulong flags;
  3717. gdth_ha_str *ha;
  3718. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3719. return -EFAULT;
  3720. ha = gdth_find_ha(ldrv.ionode);
  3721. if (!ha)
  3722. return -EFAULT;
  3723. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3724. j = ldrv.drives[i];
  3725. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3726. continue;
  3727. if (ldrv.lock) {
  3728. spin_lock_irqsave(&ha->smp_lock, flags);
  3729. ha->hdr[j].lock = 1;
  3730. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3731. gdth_wait_completion(ha, ha->bus_cnt, j);
  3732. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3733. } else {
  3734. spin_lock_irqsave(&ha->smp_lock, flags);
  3735. ha->hdr[j].lock = 0;
  3736. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3737. gdth_start_timeout(ha, ha->bus_cnt, j);
  3738. gdth_next(ha);
  3739. }
  3740. }
  3741. return 0;
  3742. }
  3743. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3744. {
  3745. gdth_ioctl_reset res;
  3746. gdth_cmd_str cmd;
  3747. gdth_ha_str *ha;
  3748. int rval;
  3749. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3750. res.number >= MAX_HDRIVES)
  3751. return -EFAULT;
  3752. ha = gdth_find_ha(res.ionode);
  3753. if (!ha)
  3754. return -EFAULT;
  3755. if (!ha->hdr[res.number].present)
  3756. return 0;
  3757. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3758. cmd.Service = CACHESERVICE;
  3759. cmd.OpCode = GDT_CLUST_RESET;
  3760. if (ha->cache_feat & GDT_64BIT)
  3761. cmd.u.cache64.DeviceNo = res.number;
  3762. else
  3763. cmd.u.cache.DeviceNo = res.number;
  3764. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3765. if (rval < 0)
  3766. return rval;
  3767. res.status = rval;
  3768. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3769. return -EFAULT;
  3770. return 0;
  3771. }
  3772. static int ioc_general(void __user *arg, char *cmnd)
  3773. {
  3774. gdth_ioctl_general gen;
  3775. char *buf = NULL;
  3776. ulong64 paddr;
  3777. gdth_ha_str *ha;
  3778. int rval;
  3779. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3780. return -EFAULT;
  3781. ha = gdth_find_ha(gen.ionode);
  3782. if (!ha)
  3783. return -EFAULT;
  3784. if (gen.data_len + gen.sense_len != 0) {
  3785. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3786. FALSE, &paddr)))
  3787. return -EFAULT;
  3788. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3789. gen.data_len + gen.sense_len)) {
  3790. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3791. return -EFAULT;
  3792. }
  3793. if (gen.command.OpCode == GDT_IOCTL) {
  3794. gen.command.u.ioctl.p_param = paddr;
  3795. } else if (gen.command.Service == CACHESERVICE) {
  3796. if (ha->cache_feat & GDT_64BIT) {
  3797. /* copy elements from 32-bit IOCTL structure */
  3798. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3799. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3800. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3801. /* addresses */
  3802. if (ha->cache_feat & SCATTER_GATHER) {
  3803. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3804. gen.command.u.cache64.sg_canz = 1;
  3805. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3806. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3807. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3808. } else {
  3809. gen.command.u.cache64.DestAddr = paddr;
  3810. gen.command.u.cache64.sg_canz = 0;
  3811. }
  3812. } else {
  3813. if (ha->cache_feat & SCATTER_GATHER) {
  3814. gen.command.u.cache.DestAddr = 0xffffffff;
  3815. gen.command.u.cache.sg_canz = 1;
  3816. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3817. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3818. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3819. } else {
  3820. gen.command.u.cache.DestAddr = paddr;
  3821. gen.command.u.cache.sg_canz = 0;
  3822. }
  3823. }
  3824. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3825. if (ha->raw_feat & GDT_64BIT) {
  3826. /* copy elements from 32-bit IOCTL structure */
  3827. char cmd[16];
  3828. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3829. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3830. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3831. gen.command.u.raw64.target = gen.command.u.raw.target;
  3832. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3833. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3834. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3835. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3836. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3837. /* addresses */
  3838. if (ha->raw_feat & SCATTER_GATHER) {
  3839. gen.command.u.raw64.sdata = (ulong64)-1;
  3840. gen.command.u.raw64.sg_ranz = 1;
  3841. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3842. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3843. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3844. } else {
  3845. gen.command.u.raw64.sdata = paddr;
  3846. gen.command.u.raw64.sg_ranz = 0;
  3847. }
  3848. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3849. } else {
  3850. if (ha->raw_feat & SCATTER_GATHER) {
  3851. gen.command.u.raw.sdata = 0xffffffff;
  3852. gen.command.u.raw.sg_ranz = 1;
  3853. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3854. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3855. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3856. } else {
  3857. gen.command.u.raw.sdata = paddr;
  3858. gen.command.u.raw.sg_ranz = 0;
  3859. }
  3860. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3861. }
  3862. } else {
  3863. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3864. return -EFAULT;
  3865. }
  3866. }
  3867. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3868. if (rval < 0)
  3869. return rval;
  3870. gen.status = rval;
  3871. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3872. gen.data_len + gen.sense_len)) {
  3873. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3874. return -EFAULT;
  3875. }
  3876. if (copy_to_user(arg, &gen,
  3877. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3878. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3879. return -EFAULT;
  3880. }
  3881. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3882. return 0;
  3883. }
  3884. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3885. {
  3886. gdth_ioctl_rescan *rsc;
  3887. gdth_cmd_str *cmd;
  3888. gdth_ha_str *ha;
  3889. unchar i;
  3890. int rc = -ENOMEM;
  3891. u32 cluster_type = 0;
  3892. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3893. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3894. if (!rsc || !cmd)
  3895. goto free_fail;
  3896. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3897. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3898. rc = -EFAULT;
  3899. goto free_fail;
  3900. }
  3901. memset(cmd, 0, sizeof(gdth_cmd_str));
  3902. for (i = 0; i < MAX_HDRIVES; ++i) {
  3903. if (!ha->hdr[i].present) {
  3904. rsc->hdr_list[i].bus = 0xff;
  3905. continue;
  3906. }
  3907. rsc->hdr_list[i].bus = ha->virt_bus;
  3908. rsc->hdr_list[i].target = i;
  3909. rsc->hdr_list[i].lun = 0;
  3910. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3911. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3912. cmd->Service = CACHESERVICE;
  3913. cmd->OpCode = GDT_CLUST_INFO;
  3914. if (ha->cache_feat & GDT_64BIT)
  3915. cmd->u.cache64.DeviceNo = i;
  3916. else
  3917. cmd->u.cache.DeviceNo = i;
  3918. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3919. rsc->hdr_list[i].cluster_type = cluster_type;
  3920. }
  3921. }
  3922. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3923. rc = -EFAULT;
  3924. else
  3925. rc = 0;
  3926. free_fail:
  3927. kfree(rsc);
  3928. kfree(cmd);
  3929. return rc;
  3930. }
  3931. static int ioc_rescan(void __user *arg, char *cmnd)
  3932. {
  3933. gdth_ioctl_rescan *rsc;
  3934. gdth_cmd_str *cmd;
  3935. ushort i, status, hdr_cnt;
  3936. ulong32 info;
  3937. int cyls, hds, secs;
  3938. int rc = -ENOMEM;
  3939. ulong flags;
  3940. gdth_ha_str *ha;
  3941. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3942. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3943. if (!cmd || !rsc)
  3944. goto free_fail;
  3945. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3946. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3947. rc = -EFAULT;
  3948. goto free_fail;
  3949. }
  3950. memset(cmd, 0, sizeof(gdth_cmd_str));
  3951. if (rsc->flag == 0) {
  3952. /* old method: re-init. cache service */
  3953. cmd->Service = CACHESERVICE;
  3954. if (ha->cache_feat & GDT_64BIT) {
  3955. cmd->OpCode = GDT_X_INIT_HOST;
  3956. cmd->u.cache64.DeviceNo = LINUX_OS;
  3957. } else {
  3958. cmd->OpCode = GDT_INIT;
  3959. cmd->u.cache.DeviceNo = LINUX_OS;
  3960. }
  3961. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3962. i = 0;
  3963. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3964. } else {
  3965. i = rsc->hdr_no;
  3966. hdr_cnt = i + 1;
  3967. }
  3968. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3969. cmd->Service = CACHESERVICE;
  3970. cmd->OpCode = GDT_INFO;
  3971. if (ha->cache_feat & GDT_64BIT)
  3972. cmd->u.cache64.DeviceNo = i;
  3973. else
  3974. cmd->u.cache.DeviceNo = i;
  3975. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3976. spin_lock_irqsave(&ha->smp_lock, flags);
  3977. rsc->hdr_list[i].bus = ha->virt_bus;
  3978. rsc->hdr_list[i].target = i;
  3979. rsc->hdr_list[i].lun = 0;
  3980. if (status != S_OK) {
  3981. ha->hdr[i].present = FALSE;
  3982. } else {
  3983. ha->hdr[i].present = TRUE;
  3984. ha->hdr[i].size = info;
  3985. /* evaluate mapping */
  3986. ha->hdr[i].size &= ~SECS32;
  3987. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3988. ha->hdr[i].heads = hds;
  3989. ha->hdr[i].secs = secs;
  3990. /* round size */
  3991. ha->hdr[i].size = cyls * hds * secs;
  3992. }
  3993. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3994. if (status != S_OK)
  3995. continue;
  3996. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3997. /* but we need ha->info2, not yet stored in scp->SCp */
  3998. /* devtype, cluster info, R/W attribs */
  3999. cmd->Service = CACHESERVICE;
  4000. cmd->OpCode = GDT_DEVTYPE;
  4001. if (ha->cache_feat & GDT_64BIT)
  4002. cmd->u.cache64.DeviceNo = i;
  4003. else
  4004. cmd->u.cache.DeviceNo = i;
  4005. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4006. spin_lock_irqsave(&ha->smp_lock, flags);
  4007. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4008. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4009. cmd->Service = CACHESERVICE;
  4010. cmd->OpCode = GDT_CLUST_INFO;
  4011. if (ha->cache_feat & GDT_64BIT)
  4012. cmd->u.cache64.DeviceNo = i;
  4013. else
  4014. cmd->u.cache.DeviceNo = i;
  4015. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4016. spin_lock_irqsave(&ha->smp_lock, flags);
  4017. ha->hdr[i].cluster_type =
  4018. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4019. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4020. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4021. cmd->Service = CACHESERVICE;
  4022. cmd->OpCode = GDT_RW_ATTRIBS;
  4023. if (ha->cache_feat & GDT_64BIT)
  4024. cmd->u.cache64.DeviceNo = i;
  4025. else
  4026. cmd->u.cache.DeviceNo = i;
  4027. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4028. spin_lock_irqsave(&ha->smp_lock, flags);
  4029. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4030. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4031. }
  4032. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4033. rc = -EFAULT;
  4034. else
  4035. rc = 0;
  4036. free_fail:
  4037. kfree(rsc);
  4038. kfree(cmd);
  4039. return rc;
  4040. }
  4041. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4042. unsigned int cmd, unsigned long arg)
  4043. {
  4044. gdth_ha_str *ha;
  4045. Scsi_Cmnd *scp;
  4046. ulong flags;
  4047. char cmnd[MAX_COMMAND_SIZE];
  4048. void __user *argp = (void __user *)arg;
  4049. memset(cmnd, 0xff, 12);
  4050. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4051. switch (cmd) {
  4052. case GDTIOCTL_CTRCNT:
  4053. {
  4054. int cnt = gdth_ctr_count;
  4055. if (put_user(cnt, (int __user *)argp))
  4056. return -EFAULT;
  4057. break;
  4058. }
  4059. case GDTIOCTL_DRVERS:
  4060. {
  4061. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4062. if (put_user(ver, (int __user *)argp))
  4063. return -EFAULT;
  4064. break;
  4065. }
  4066. case GDTIOCTL_OSVERS:
  4067. {
  4068. gdth_ioctl_osvers osv;
  4069. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4070. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4071. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4072. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4073. return -EFAULT;
  4074. break;
  4075. }
  4076. case GDTIOCTL_CTRTYPE:
  4077. {
  4078. gdth_ioctl_ctrtype ctrt;
  4079. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4080. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4081. return -EFAULT;
  4082. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4083. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4084. } else {
  4085. if (ha->type != GDT_PCIMPR) {
  4086. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4087. } else {
  4088. ctrt.type =
  4089. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4090. if (ha->stype >= 0x300)
  4091. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4092. else
  4093. ctrt.ext_type = 0x6000 | ha->stype;
  4094. }
  4095. ctrt.device_id = ha->pdev->device;
  4096. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4097. }
  4098. ctrt.info = ha->brd_phys;
  4099. ctrt.oem_id = ha->oem_id;
  4100. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4101. return -EFAULT;
  4102. break;
  4103. }
  4104. case GDTIOCTL_GENERAL:
  4105. return ioc_general(argp, cmnd);
  4106. case GDTIOCTL_EVENT:
  4107. return ioc_event(argp);
  4108. case GDTIOCTL_LOCKDRV:
  4109. return ioc_lockdrv(argp);
  4110. case GDTIOCTL_LOCKCHN:
  4111. {
  4112. gdth_ioctl_lockchn lchn;
  4113. unchar i, j;
  4114. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4115. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4116. return -EFAULT;
  4117. i = lchn.channel;
  4118. if (i < ha->bus_cnt) {
  4119. if (lchn.lock) {
  4120. spin_lock_irqsave(&ha->smp_lock, flags);
  4121. ha->raw[i].lock = 1;
  4122. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4123. for (j = 0; j < ha->tid_cnt; ++j) {
  4124. gdth_wait_completion(ha, i, j);
  4125. gdth_stop_timeout(ha, i, j);
  4126. }
  4127. } else {
  4128. spin_lock_irqsave(&ha->smp_lock, flags);
  4129. ha->raw[i].lock = 0;
  4130. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4131. for (j = 0; j < ha->tid_cnt; ++j) {
  4132. gdth_start_timeout(ha, i, j);
  4133. gdth_next(ha);
  4134. }
  4135. }
  4136. }
  4137. break;
  4138. }
  4139. case GDTIOCTL_RESCAN:
  4140. return ioc_rescan(argp, cmnd);
  4141. case GDTIOCTL_HDRLIST:
  4142. return ioc_hdrlist(argp, cmnd);
  4143. case GDTIOCTL_RESET_BUS:
  4144. {
  4145. gdth_ioctl_reset res;
  4146. int rval;
  4147. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4148. (NULL == (ha = gdth_find_ha(res.ionode))))
  4149. return -EFAULT;
  4150. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4151. if (!scp)
  4152. return -ENOMEM;
  4153. scp->device = ha->sdev;
  4154. scp->cmd_len = 12;
  4155. scp->device->channel = res.number;
  4156. rval = gdth_eh_bus_reset(scp);
  4157. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4158. kfree(scp);
  4159. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4160. return -EFAULT;
  4161. break;
  4162. }
  4163. case GDTIOCTL_RESET_DRV:
  4164. return ioc_resetdrv(argp, cmnd);
  4165. default:
  4166. break;
  4167. }
  4168. return 0;
  4169. }
  4170. /* flush routine */
  4171. static void gdth_flush(gdth_ha_str *ha)
  4172. {
  4173. int i;
  4174. gdth_cmd_str gdtcmd;
  4175. char cmnd[MAX_COMMAND_SIZE];
  4176. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4177. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4178. for (i = 0; i < MAX_HDRIVES; ++i) {
  4179. if (ha->hdr[i].present) {
  4180. gdtcmd.BoardNode = LOCALBOARD;
  4181. gdtcmd.Service = CACHESERVICE;
  4182. gdtcmd.OpCode = GDT_FLUSH;
  4183. if (ha->cache_feat & GDT_64BIT) {
  4184. gdtcmd.u.cache64.DeviceNo = i;
  4185. gdtcmd.u.cache64.BlockNo = 1;
  4186. gdtcmd.u.cache64.sg_canz = 0;
  4187. } else {
  4188. gdtcmd.u.cache.DeviceNo = i;
  4189. gdtcmd.u.cache.BlockNo = 1;
  4190. gdtcmd.u.cache.sg_canz = 0;
  4191. }
  4192. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4193. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4194. }
  4195. }
  4196. }
  4197. /* configure lun */
  4198. static int gdth_slave_configure(struct scsi_device *sdev)
  4199. {
  4200. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4201. sdev->skip_ms_page_3f = 1;
  4202. sdev->skip_ms_page_8 = 1;
  4203. return 0;
  4204. }
  4205. static struct scsi_host_template gdth_template = {
  4206. .name = "GDT SCSI Disk Array Controller",
  4207. .info = gdth_info,
  4208. .queuecommand = gdth_queuecommand,
  4209. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4210. .slave_configure = gdth_slave_configure,
  4211. .bios_param = gdth_bios_param,
  4212. .proc_info = gdth_proc_info,
  4213. .proc_name = "gdth",
  4214. .can_queue = GDTH_MAXCMDS,
  4215. .this_id = -1,
  4216. .sg_tablesize = GDTH_MAXSG,
  4217. .cmd_per_lun = GDTH_MAXC_P_L,
  4218. .unchecked_isa_dma = 1,
  4219. .use_clustering = ENABLE_CLUSTERING,
  4220. };
  4221. #ifdef CONFIG_ISA
  4222. static int __init gdth_isa_probe_one(ulong32 isa_bios)
  4223. {
  4224. struct Scsi_Host *shp;
  4225. gdth_ha_str *ha;
  4226. dma_addr_t scratch_dma_handle = 0;
  4227. int error, i;
  4228. if (!gdth_search_isa(isa_bios))
  4229. return -ENXIO;
  4230. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4231. if (!shp)
  4232. return -ENOMEM;
  4233. ha = shost_priv(shp);
  4234. error = -ENODEV;
  4235. if (!gdth_init_isa(isa_bios,ha))
  4236. goto out_host_put;
  4237. /* controller found and initialized */
  4238. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4239. isa_bios, ha->irq, ha->drq);
  4240. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4241. if (error) {
  4242. printk("GDT-ISA: Unable to allocate IRQ\n");
  4243. goto out_host_put;
  4244. }
  4245. error = request_dma(ha->drq, "gdth");
  4246. if (error) {
  4247. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4248. goto out_free_irq;
  4249. }
  4250. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4251. enable_dma(ha->drq);
  4252. shp->unchecked_isa_dma = 1;
  4253. shp->irq = ha->irq;
  4254. shp->dma_channel = ha->drq;
  4255. ha->hanum = gdth_ctr_count++;
  4256. ha->shost = shp;
  4257. ha->pccb = &ha->cmdext;
  4258. ha->ccb_phys = 0L;
  4259. ha->pdev = NULL;
  4260. error = -ENOMEM;
  4261. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4262. &scratch_dma_handle);
  4263. if (!ha->pscratch)
  4264. goto out_dec_counters;
  4265. ha->scratch_phys = scratch_dma_handle;
  4266. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4267. &scratch_dma_handle);
  4268. if (!ha->pmsg)
  4269. goto out_free_pscratch;
  4270. ha->msg_phys = scratch_dma_handle;
  4271. #ifdef INT_COAL
  4272. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4273. sizeof(gdth_coal_status) * MAXOFFSETS,
  4274. &scratch_dma_handle);
  4275. if (!ha->coal_stat)
  4276. goto out_free_pmsg;
  4277. ha->coal_stat_phys = scratch_dma_handle;
  4278. #endif
  4279. ha->scratch_busy = FALSE;
  4280. ha->req_first = NULL;
  4281. ha->tid_cnt = MAX_HDRIVES;
  4282. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4283. ha->tid_cnt = max_ids;
  4284. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4285. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4286. ha->scan_mode = rescan ? 0x10 : 0;
  4287. error = -ENODEV;
  4288. if (!gdth_search_drives(ha)) {
  4289. printk("GDT-ISA: Error during device scan\n");
  4290. goto out_free_coal_stat;
  4291. }
  4292. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4293. hdr_channel = ha->bus_cnt;
  4294. ha->virt_bus = hdr_channel;
  4295. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4296. shp->max_cmd_len = 16;
  4297. shp->max_id = ha->tid_cnt;
  4298. shp->max_lun = MAXLUN;
  4299. shp->max_channel = ha->bus_cnt;
  4300. spin_lock_init(&ha->smp_lock);
  4301. gdth_enable_int(ha);
  4302. error = scsi_add_host(shp, NULL);
  4303. if (error)
  4304. goto out_free_coal_stat;
  4305. list_add_tail(&ha->list, &gdth_instances);
  4306. scsi_scan_host(shp);
  4307. return 0;
  4308. out_free_coal_stat:
  4309. #ifdef INT_COAL
  4310. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4311. ha->coal_stat, ha->coal_stat_phys);
  4312. out_free_pmsg:
  4313. #endif
  4314. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4315. ha->pmsg, ha->msg_phys);
  4316. out_free_pscratch:
  4317. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4318. ha->pscratch, ha->scratch_phys);
  4319. out_dec_counters:
  4320. gdth_ctr_count--;
  4321. out_free_irq:
  4322. free_irq(ha->irq, ha);
  4323. out_host_put:
  4324. scsi_host_put(shp);
  4325. return error;
  4326. }
  4327. #endif /* CONFIG_ISA */
  4328. #ifdef CONFIG_EISA
  4329. static int __init gdth_eisa_probe_one(ushort eisa_slot)
  4330. {
  4331. struct Scsi_Host *shp;
  4332. gdth_ha_str *ha;
  4333. dma_addr_t scratch_dma_handle = 0;
  4334. int error, i;
  4335. if (!gdth_search_eisa(eisa_slot))
  4336. return -ENXIO;
  4337. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4338. if (!shp)
  4339. return -ENOMEM;
  4340. ha = shost_priv(shp);
  4341. error = -ENODEV;
  4342. if (!gdth_init_eisa(eisa_slot,ha))
  4343. goto out_host_put;
  4344. /* controller found and initialized */
  4345. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4346. eisa_slot >> 12, ha->irq);
  4347. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4348. if (error) {
  4349. printk("GDT-EISA: Unable to allocate IRQ\n");
  4350. goto out_host_put;
  4351. }
  4352. shp->unchecked_isa_dma = 0;
  4353. shp->irq = ha->irq;
  4354. shp->dma_channel = 0xff;
  4355. ha->hanum = gdth_ctr_count++;
  4356. ha->shost = shp;
  4357. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4358. ha->pccb = &ha->cmdext;
  4359. ha->ccb_phys = 0L;
  4360. error = -ENOMEM;
  4361. ha->pdev = NULL;
  4362. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4363. &scratch_dma_handle);
  4364. if (!ha->pscratch)
  4365. goto out_free_irq;
  4366. ha->scratch_phys = scratch_dma_handle;
  4367. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4368. &scratch_dma_handle);
  4369. if (!ha->pmsg)
  4370. goto out_free_pscratch;
  4371. ha->msg_phys = scratch_dma_handle;
  4372. #ifdef INT_COAL
  4373. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4374. sizeof(gdth_coal_status) * MAXOFFSETS,
  4375. &scratch_dma_handle);
  4376. if (!ha->coal_stat)
  4377. goto out_free_pmsg;
  4378. ha->coal_stat_phys = scratch_dma_handle;
  4379. #endif
  4380. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4381. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4382. if (!ha->ccb_phys)
  4383. goto out_free_coal_stat;
  4384. ha->scratch_busy = FALSE;
  4385. ha->req_first = NULL;
  4386. ha->tid_cnt = MAX_HDRIVES;
  4387. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4388. ha->tid_cnt = max_ids;
  4389. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4390. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4391. ha->scan_mode = rescan ? 0x10 : 0;
  4392. if (!gdth_search_drives(ha)) {
  4393. printk("GDT-EISA: Error during device scan\n");
  4394. error = -ENODEV;
  4395. goto out_free_ccb_phys;
  4396. }
  4397. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4398. hdr_channel = ha->bus_cnt;
  4399. ha->virt_bus = hdr_channel;
  4400. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4401. shp->max_cmd_len = 16;
  4402. shp->max_id = ha->tid_cnt;
  4403. shp->max_lun = MAXLUN;
  4404. shp->max_channel = ha->bus_cnt;
  4405. spin_lock_init(&ha->smp_lock);
  4406. gdth_enable_int(ha);
  4407. error = scsi_add_host(shp, NULL);
  4408. if (error)
  4409. goto out_free_coal_stat;
  4410. list_add_tail(&ha->list, &gdth_instances);
  4411. scsi_scan_host(shp);
  4412. return 0;
  4413. out_free_ccb_phys:
  4414. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4415. PCI_DMA_BIDIRECTIONAL);
  4416. out_free_coal_stat:
  4417. #ifdef INT_COAL
  4418. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4419. ha->coal_stat, ha->coal_stat_phys);
  4420. out_free_pmsg:
  4421. #endif
  4422. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4423. ha->pmsg, ha->msg_phys);
  4424. out_free_pscratch:
  4425. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4426. ha->pscratch, ha->scratch_phys);
  4427. out_free_irq:
  4428. free_irq(ha->irq, ha);
  4429. gdth_ctr_count--;
  4430. out_host_put:
  4431. scsi_host_put(shp);
  4432. return error;
  4433. }
  4434. #endif /* CONFIG_EISA */
  4435. #ifdef CONFIG_PCI
  4436. static int __init gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4437. {
  4438. struct Scsi_Host *shp;
  4439. gdth_ha_str *ha;
  4440. dma_addr_t scratch_dma_handle = 0;
  4441. int error, i;
  4442. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4443. if (!shp)
  4444. return -ENOMEM;
  4445. ha = shost_priv(shp);
  4446. error = -ENODEV;
  4447. if (!gdth_init_pci(&pcistr[ctr],ha))
  4448. goto out_host_put;
  4449. /* controller found and initialized */
  4450. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4451. pcistr[ctr].pdev->bus->number,
  4452. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4453. ha->irq);
  4454. error = request_irq(ha->irq, gdth_interrupt,
  4455. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4456. if (error) {
  4457. printk("GDT-PCI: Unable to allocate IRQ\n");
  4458. goto out_host_put;
  4459. }
  4460. shp->unchecked_isa_dma = 0;
  4461. shp->irq = ha->irq;
  4462. shp->dma_channel = 0xff;
  4463. ha->hanum = gdth_ctr_count++;
  4464. ha->shost = shp;
  4465. ha->pccb = &ha->cmdext;
  4466. ha->ccb_phys = 0L;
  4467. error = -ENOMEM;
  4468. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4469. &scratch_dma_handle);
  4470. if (!ha->pscratch)
  4471. goto out_free_irq;
  4472. ha->scratch_phys = scratch_dma_handle;
  4473. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4474. &scratch_dma_handle);
  4475. if (!ha->pmsg)
  4476. goto out_free_pscratch;
  4477. ha->msg_phys = scratch_dma_handle;
  4478. #ifdef INT_COAL
  4479. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4480. sizeof(gdth_coal_status) * MAXOFFSETS,
  4481. &scratch_dma_handle);
  4482. if (!ha->coal_stat)
  4483. goto out_free_pmsg;
  4484. ha->coal_stat_phys = scratch_dma_handle;
  4485. #endif
  4486. ha->scratch_busy = FALSE;
  4487. ha->req_first = NULL;
  4488. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4489. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4490. ha->tid_cnt = max_ids;
  4491. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4492. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4493. ha->scan_mode = rescan ? 0x10 : 0;
  4494. error = -ENODEV;
  4495. if (!gdth_search_drives(ha)) {
  4496. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4497. goto out_free_coal_stat;
  4498. }
  4499. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4500. hdr_channel = ha->bus_cnt;
  4501. ha->virt_bus = hdr_channel;
  4502. /* 64-bit DMA only supported from FW >= x.43 */
  4503. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4504. !ha->dma64_support) {
  4505. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4506. printk(KERN_WARNING "GDT-PCI %d: "
  4507. "Unable to set 32-bit DMA\n", ha->hanum);
  4508. goto out_free_coal_stat;
  4509. }
  4510. } else {
  4511. shp->max_cmd_len = 16;
  4512. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4513. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4514. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4515. printk(KERN_WARNING "GDT-PCI %d: "
  4516. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4517. goto out_free_coal_stat;
  4518. }
  4519. }
  4520. shp->max_id = ha->tid_cnt;
  4521. shp->max_lun = MAXLUN;
  4522. shp->max_channel = ha->bus_cnt;
  4523. spin_lock_init(&ha->smp_lock);
  4524. gdth_enable_int(ha);
  4525. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4526. if (error)
  4527. goto out_free_coal_stat;
  4528. list_add_tail(&ha->list, &gdth_instances);
  4529. scsi_scan_host(shp);
  4530. return 0;
  4531. out_free_coal_stat:
  4532. #ifdef INT_COAL
  4533. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4534. ha->coal_stat, ha->coal_stat_phys);
  4535. out_free_pmsg:
  4536. #endif
  4537. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4538. ha->pmsg, ha->msg_phys);
  4539. out_free_pscratch:
  4540. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4541. ha->pscratch, ha->scratch_phys);
  4542. out_free_irq:
  4543. free_irq(ha->irq, ha);
  4544. gdth_ctr_count--;
  4545. out_host_put:
  4546. scsi_host_put(shp);
  4547. return error;
  4548. }
  4549. #endif /* CONFIG_PCI */
  4550. static void gdth_remove_one(gdth_ha_str *ha)
  4551. {
  4552. struct Scsi_Host *shp = ha->shost;
  4553. TRACE2(("gdth_remove_one()\n"));
  4554. scsi_remove_host(shp);
  4555. gdth_flush(ha);
  4556. if (ha->sdev) {
  4557. scsi_free_host_dev(ha->sdev);
  4558. ha->sdev = NULL;
  4559. }
  4560. if (shp->irq)
  4561. free_irq(shp->irq,ha);
  4562. #ifdef CONFIG_ISA
  4563. if (shp->dma_channel != 0xff)
  4564. free_dma(shp->dma_channel);
  4565. #endif
  4566. #ifdef INT_COAL
  4567. if (ha->coal_stat)
  4568. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4569. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4570. #endif
  4571. if (ha->pscratch)
  4572. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4573. ha->pscratch, ha->scratch_phys);
  4574. if (ha->pmsg)
  4575. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4576. ha->pmsg, ha->msg_phys);
  4577. if (ha->ccb_phys)
  4578. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4579. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4580. scsi_host_put(shp);
  4581. }
  4582. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4583. {
  4584. gdth_ha_str *ha;
  4585. TRACE2(("gdth_halt() event %d\n", (int)event));
  4586. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4587. return NOTIFY_DONE;
  4588. list_for_each_entry(ha, &gdth_instances, list)
  4589. gdth_flush(ha);
  4590. return NOTIFY_OK;
  4591. }
  4592. static struct notifier_block gdth_notifier = {
  4593. gdth_halt, NULL, 0
  4594. };
  4595. static int __init gdth_init(void)
  4596. {
  4597. if (disable) {
  4598. printk("GDT-HA: Controller driver disabled from"
  4599. " command line !\n");
  4600. return 0;
  4601. }
  4602. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4603. GDTH_VERSION_STR);
  4604. /* initializations */
  4605. gdth_polling = TRUE;
  4606. gdth_clear_events();
  4607. /* As default we do not probe for EISA or ISA controllers */
  4608. if (probe_eisa_isa) {
  4609. /* scanning for controllers, at first: ISA controller */
  4610. #ifdef CONFIG_ISA
  4611. ulong32 isa_bios;
  4612. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4613. isa_bios += 0x8000UL)
  4614. gdth_isa_probe_one(isa_bios);
  4615. #endif
  4616. #ifdef CONFIG_EISA
  4617. {
  4618. ushort eisa_slot;
  4619. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4620. eisa_slot += 0x1000)
  4621. gdth_eisa_probe_one(eisa_slot);
  4622. }
  4623. #endif
  4624. }
  4625. #ifdef CONFIG_PCI
  4626. /* scanning for PCI controllers */
  4627. {
  4628. gdth_pci_str pcistr[MAXHA];
  4629. int cnt,ctr;
  4630. cnt = gdth_search_pci(pcistr);
  4631. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4632. gdth_sort_pci(pcistr,cnt);
  4633. for (ctr = 0; ctr < cnt; ++ctr)
  4634. gdth_pci_probe_one(pcistr, ctr);
  4635. }
  4636. #endif /* CONFIG_PCI */
  4637. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4638. if (list_empty(&gdth_instances))
  4639. return -ENODEV;
  4640. #ifdef GDTH_STATISTICS
  4641. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4642. init_timer(&gdth_timer);
  4643. gdth_timer.expires = jiffies + HZ;
  4644. gdth_timer.data = 0L;
  4645. gdth_timer.function = gdth_timeout;
  4646. add_timer(&gdth_timer);
  4647. #endif
  4648. major = register_chrdev(0,"gdth", &gdth_fops);
  4649. register_reboot_notifier(&gdth_notifier);
  4650. gdth_polling = FALSE;
  4651. return 0;
  4652. }
  4653. static void __exit gdth_exit(void)
  4654. {
  4655. gdth_ha_str *ha;
  4656. unregister_chrdev(major, "gdth");
  4657. unregister_reboot_notifier(&gdth_notifier);
  4658. #ifdef GDTH_STATISTICS
  4659. del_timer_sync(&gdth_timer);
  4660. #endif
  4661. list_for_each_entry(ha, &gdth_instances, list)
  4662. gdth_remove_one(ha);
  4663. }
  4664. module_init(gdth_init);
  4665. module_exit(gdth_exit);
  4666. #ifndef MODULE
  4667. __setup("gdth=", option_setup);
  4668. #endif