Kconfig 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282
  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. def_bool n
  8. config FPU
  9. def_bool n
  10. config RWSEM_GENERIC_SPINLOCK
  11. def_bool y
  12. config RWSEM_XCHGADD_ALGORITHM
  13. def_bool n
  14. config BLACKFIN
  15. def_bool y
  16. select HAVE_FUNCTION_GRAPH_TRACER
  17. select HAVE_FUNCTION_TRACER
  18. select HAVE_IDE
  19. select HAVE_KERNEL_GZIP
  20. select HAVE_KERNEL_BZIP2
  21. select HAVE_KERNEL_LZMA
  22. select HAVE_OPROFILE
  23. select ARCH_WANT_OPTIONAL_GPIOLIB
  24. config GENERIC_BUG
  25. def_bool y
  26. depends on BUG
  27. config ZONE_DMA
  28. def_bool y
  29. config GENERIC_FIND_NEXT_BIT
  30. def_bool y
  31. config GENERIC_HWEIGHT
  32. def_bool y
  33. config GENERIC_HARDIRQS
  34. def_bool y
  35. config GENERIC_IRQ_PROBE
  36. def_bool y
  37. config GENERIC_GPIO
  38. def_bool y
  39. config FORCE_MAX_ZONEORDER
  40. int
  41. default "14"
  42. config GENERIC_CALIBRATE_DELAY
  43. def_bool y
  44. config LOCKDEP_SUPPORT
  45. def_bool y
  46. config STACKTRACE_SUPPORT
  47. def_bool y
  48. config TRACE_IRQFLAGS_SUPPORT
  49. def_bool y
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. source "kernel/Kconfig.freezer"
  53. menu "Blackfin Processor Options"
  54. comment "Processor and Board Settings"
  55. choice
  56. prompt "CPU"
  57. default BF533
  58. config BF512
  59. bool "BF512"
  60. help
  61. BF512 Processor Support.
  62. config BF514
  63. bool "BF514"
  64. help
  65. BF514 Processor Support.
  66. config BF516
  67. bool "BF516"
  68. help
  69. BF516 Processor Support.
  70. config BF518
  71. bool "BF518"
  72. help
  73. BF518 Processor Support.
  74. config BF522
  75. bool "BF522"
  76. help
  77. BF522 Processor Support.
  78. config BF523
  79. bool "BF523"
  80. help
  81. BF523 Processor Support.
  82. config BF524
  83. bool "BF524"
  84. help
  85. BF524 Processor Support.
  86. config BF525
  87. bool "BF525"
  88. help
  89. BF525 Processor Support.
  90. config BF526
  91. bool "BF526"
  92. help
  93. BF526 Processor Support.
  94. config BF527
  95. bool "BF527"
  96. help
  97. BF527 Processor Support.
  98. config BF531
  99. bool "BF531"
  100. help
  101. BF531 Processor Support.
  102. config BF532
  103. bool "BF532"
  104. help
  105. BF532 Processor Support.
  106. config BF533
  107. bool "BF533"
  108. help
  109. BF533 Processor Support.
  110. config BF534
  111. bool "BF534"
  112. help
  113. BF534 Processor Support.
  114. config BF536
  115. bool "BF536"
  116. help
  117. BF536 Processor Support.
  118. config BF537
  119. bool "BF537"
  120. help
  121. BF537 Processor Support.
  122. config BF538
  123. bool "BF538"
  124. help
  125. BF538 Processor Support.
  126. config BF539
  127. bool "BF539"
  128. help
  129. BF539 Processor Support.
  130. config BF542
  131. bool "BF542"
  132. help
  133. BF542 Processor Support.
  134. config BF542M
  135. bool "BF542m"
  136. help
  137. BF542 Processor Support.
  138. config BF544
  139. bool "BF544"
  140. help
  141. BF544 Processor Support.
  142. config BF544M
  143. bool "BF544m"
  144. help
  145. BF544 Processor Support.
  146. config BF547
  147. bool "BF547"
  148. help
  149. BF547 Processor Support.
  150. config BF547M
  151. bool "BF547m"
  152. help
  153. BF547 Processor Support.
  154. config BF548
  155. bool "BF548"
  156. help
  157. BF548 Processor Support.
  158. config BF548M
  159. bool "BF548m"
  160. help
  161. BF548 Processor Support.
  162. config BF549
  163. bool "BF549"
  164. help
  165. BF549 Processor Support.
  166. config BF549M
  167. bool "BF549m"
  168. help
  169. BF549 Processor Support.
  170. config BF561
  171. bool "BF561"
  172. help
  173. BF561 Processor Support.
  174. endchoice
  175. config SMP
  176. depends on BF561
  177. select GENERIC_TIME
  178. bool "Symmetric multi-processing support"
  179. ---help---
  180. This enables support for systems with more than one CPU,
  181. like the dual core BF561. If you have a system with only one
  182. CPU, say N. If you have a system with more than one CPU, say Y.
  183. If you don't know what to do here, say N.
  184. config NR_CPUS
  185. int
  186. depends on SMP
  187. default 2 if BF561
  188. config IRQ_PER_CPU
  189. bool
  190. depends on SMP
  191. default y
  192. config BF_REV_MIN
  193. int
  194. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  195. default 2 if (BF537 || BF536 || BF534)
  196. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  197. default 4 if (BF538 || BF539)
  198. config BF_REV_MAX
  199. int
  200. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  201. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  202. default 5 if (BF561 || BF538 || BF539)
  203. default 6 if (BF533 || BF532 || BF531)
  204. choice
  205. prompt "Silicon Rev"
  206. default BF_REV_0_0 if (BF51x || BF52x)
  207. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  208. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  209. config BF_REV_0_0
  210. bool "0.0"
  211. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  212. config BF_REV_0_1
  213. bool "0.1"
  214. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  215. config BF_REV_0_2
  216. bool "0.2"
  217. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  218. config BF_REV_0_3
  219. bool "0.3"
  220. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  221. config BF_REV_0_4
  222. bool "0.4"
  223. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  224. config BF_REV_0_5
  225. bool "0.5"
  226. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  227. config BF_REV_0_6
  228. bool "0.6"
  229. depends on (BF533 || BF532 || BF531)
  230. config BF_REV_ANY
  231. bool "any"
  232. config BF_REV_NONE
  233. bool "none"
  234. endchoice
  235. config BF51x
  236. bool
  237. depends on (BF512 || BF514 || BF516 || BF518)
  238. default y
  239. config BF52x
  240. bool
  241. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  242. default y
  243. config BF53x
  244. bool
  245. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  246. default y
  247. config BF54xM
  248. bool
  249. depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
  250. default y
  251. config BF54x
  252. bool
  253. depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
  254. default y
  255. config MEM_GENERIC_BOARD
  256. bool
  257. depends on GENERIC_BOARD
  258. default y
  259. config MEM_MT48LC64M4A2FB_7E
  260. bool
  261. depends on (BFIN533_STAMP)
  262. default y
  263. config MEM_MT48LC16M16A2TG_75
  264. bool
  265. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  266. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  267. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  268. default y
  269. config MEM_MT48LC32M8A2_75
  270. bool
  271. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  272. default y
  273. config MEM_MT48LC8M32B2B5_7
  274. bool
  275. depends on (BFIN561_BLUETECHNIX_CM)
  276. default y
  277. config MEM_MT48LC32M16A2TG_75
  278. bool
  279. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
  280. default y
  281. config MEM_MT48LC32M8A2_75
  282. bool
  283. depends on (BFIN518F_EZBRD)
  284. default y
  285. config MEM_MT48H32M16LFCJ_75
  286. bool
  287. depends on (BFIN526_EZBRD)
  288. default y
  289. source "arch/blackfin/mach-bf518/Kconfig"
  290. source "arch/blackfin/mach-bf527/Kconfig"
  291. source "arch/blackfin/mach-bf533/Kconfig"
  292. source "arch/blackfin/mach-bf561/Kconfig"
  293. source "arch/blackfin/mach-bf537/Kconfig"
  294. source "arch/blackfin/mach-bf538/Kconfig"
  295. source "arch/blackfin/mach-bf548/Kconfig"
  296. menu "Board customizations"
  297. config CMDLINE_BOOL
  298. bool "Default bootloader kernel arguments"
  299. config CMDLINE
  300. string "Initial kernel command string"
  301. depends on CMDLINE_BOOL
  302. default "console=ttyBF0,57600"
  303. help
  304. If you don't have a boot loader capable of passing a command line string
  305. to the kernel, you may specify one here. As a minimum, you should specify
  306. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  307. config BOOT_LOAD
  308. hex "Kernel load address for booting"
  309. default "0x1000"
  310. range 0x1000 0x20000000
  311. help
  312. This option allows you to set the load address of the kernel.
  313. This can be useful if you are on a board which has a small amount
  314. of memory or you wish to reserve some memory at the beginning of
  315. the address space.
  316. Note that you need to keep this value above 4k (0x1000) as this
  317. memory region is used to capture NULL pointer references as well
  318. as some core kernel functions.
  319. config ROM_BASE
  320. hex "Kernel ROM Base"
  321. depends on ROMKERNEL
  322. default "0x20040000"
  323. range 0x20000000 0x20400000 if !(BF54x || BF561)
  324. range 0x20000000 0x30000000 if (BF54x || BF561)
  325. help
  326. comment "Clock/PLL Setup"
  327. config CLKIN_HZ
  328. int "Frequency of the crystal on the board in Hz"
  329. default "10000000" if BFIN532_IP0X
  330. default "11059200" if BFIN533_STAMP
  331. default "24576000" if PNAV10
  332. default "25000000" # most people use this
  333. default "27000000" if BFIN533_EZKIT
  334. default "30000000" if BFIN561_EZKIT
  335. help
  336. The frequency of CLKIN crystal oscillator on the board in Hz.
  337. Warning: This value should match the crystal on the board. Otherwise,
  338. peripherals won't work properly.
  339. config BFIN_KERNEL_CLOCK
  340. bool "Re-program Clocks while Kernel boots?"
  341. default n
  342. help
  343. This option decides if kernel clocks are re-programed from the
  344. bootloader settings. If the clocks are not set, the SDRAM settings
  345. are also not changed, and the Bootloader does 100% of the hardware
  346. configuration.
  347. config PLL_BYPASS
  348. bool "Bypass PLL"
  349. depends on BFIN_KERNEL_CLOCK
  350. default n
  351. config CLKIN_HALF
  352. bool "Half Clock In"
  353. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  354. default n
  355. help
  356. If this is set the clock will be divided by 2, before it goes to the PLL.
  357. config VCO_MULT
  358. int "VCO Multiplier"
  359. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  360. range 1 64
  361. default "22" if BFIN533_EZKIT
  362. default "45" if BFIN533_STAMP
  363. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  364. default "22" if BFIN533_BLUETECHNIX_CM
  365. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  366. default "20" if BFIN561_EZKIT
  367. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  368. help
  369. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  370. PLL Frequency = (Crystal Frequency) * (this setting)
  371. choice
  372. prompt "Core Clock Divider"
  373. depends on BFIN_KERNEL_CLOCK
  374. default CCLK_DIV_1
  375. help
  376. This sets the frequency of the core. It can be 1, 2, 4 or 8
  377. Core Frequency = (PLL frequency) / (this setting)
  378. config CCLK_DIV_1
  379. bool "1"
  380. config CCLK_DIV_2
  381. bool "2"
  382. config CCLK_DIV_4
  383. bool "4"
  384. config CCLK_DIV_8
  385. bool "8"
  386. endchoice
  387. config SCLK_DIV
  388. int "System Clock Divider"
  389. depends on BFIN_KERNEL_CLOCK
  390. range 1 15
  391. default 5
  392. help
  393. This sets the frequency of the system clock (including SDRAM or DDR).
  394. This can be between 1 and 15
  395. System Clock = (PLL frequency) / (this setting)
  396. choice
  397. prompt "DDR SDRAM Chip Type"
  398. depends on BFIN_KERNEL_CLOCK
  399. depends on BF54x
  400. default MEM_MT46V32M16_5B
  401. config MEM_MT46V32M16_6T
  402. bool "MT46V32M16_6T"
  403. config MEM_MT46V32M16_5B
  404. bool "MT46V32M16_5B"
  405. endchoice
  406. choice
  407. prompt "DDR/SDRAM Timing"
  408. depends on BFIN_KERNEL_CLOCK
  409. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  410. help
  411. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  412. The calculated SDRAM timing parameters may not be 100%
  413. accurate - This option is therefore marked experimental.
  414. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  415. bool "Calculate Timings (EXPERIMENTAL)"
  416. depends on EXPERIMENTAL
  417. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  418. bool "Provide accurate Timings based on target SCLK"
  419. help
  420. Please consult the Blackfin Hardware Reference Manuals as well
  421. as the memory device datasheet.
  422. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  423. endchoice
  424. menu "Memory Init Control"
  425. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  426. config MEM_DDRCTL0
  427. depends on BF54x
  428. hex "DDRCTL0"
  429. default 0x0
  430. config MEM_DDRCTL1
  431. depends on BF54x
  432. hex "DDRCTL1"
  433. default 0x0
  434. config MEM_DDRCTL2
  435. depends on BF54x
  436. hex "DDRCTL2"
  437. default 0x0
  438. config MEM_EBIU_DDRQUE
  439. depends on BF54x
  440. hex "DDRQUE"
  441. default 0x0
  442. config MEM_SDRRC
  443. depends on !BF54x
  444. hex "SDRRC"
  445. default 0x0
  446. config MEM_SDGCTL
  447. depends on !BF54x
  448. hex "SDGCTL"
  449. default 0x0
  450. endmenu
  451. #
  452. # Max & Min Speeds for various Chips
  453. #
  454. config MAX_VCO_HZ
  455. int
  456. default 400000000 if BF512
  457. default 400000000 if BF514
  458. default 400000000 if BF516
  459. default 400000000 if BF518
  460. default 600000000 if BF522
  461. default 400000000 if BF523
  462. default 400000000 if BF524
  463. default 600000000 if BF525
  464. default 400000000 if BF526
  465. default 600000000 if BF527
  466. default 400000000 if BF531
  467. default 400000000 if BF532
  468. default 750000000 if BF533
  469. default 500000000 if BF534
  470. default 400000000 if BF536
  471. default 600000000 if BF537
  472. default 533333333 if BF538
  473. default 533333333 if BF539
  474. default 600000000 if BF542
  475. default 533333333 if BF544
  476. default 600000000 if BF547
  477. default 600000000 if BF548
  478. default 533333333 if BF549
  479. default 600000000 if BF561
  480. config MIN_VCO_HZ
  481. int
  482. default 50000000
  483. config MAX_SCLK_HZ
  484. int
  485. default 133333333
  486. config MIN_SCLK_HZ
  487. int
  488. default 27000000
  489. comment "Kernel Timer/Scheduler"
  490. source kernel/Kconfig.hz
  491. config GENERIC_TIME
  492. bool "Generic time"
  493. default y
  494. config GENERIC_CLOCKEVENTS
  495. bool "Generic clock events"
  496. depends on GENERIC_TIME
  497. default y
  498. choice
  499. prompt "Kernel Tick Source"
  500. depends on GENERIC_CLOCKEVENTS
  501. default TICKSOURCE_CORETMR
  502. config TICKSOURCE_GPTMR0
  503. bool "Gptimer0 (SCLK domain)"
  504. select BFIN_GPTIMERS
  505. config TICKSOURCE_CORETMR
  506. bool "Core timer (CCLK domain)"
  507. endchoice
  508. config CYCLES_CLOCKSOURCE
  509. bool "Use 'CYCLES' as a clocksource"
  510. depends on GENERIC_CLOCKEVENTS
  511. depends on !BFIN_SCRATCH_REG_CYCLES
  512. depends on !SMP
  513. help
  514. If you say Y here, you will enable support for using the 'cycles'
  515. registers as a clock source. Doing so means you will be unable to
  516. safely write to the 'cycles' register during runtime. You will
  517. still be able to read it (such as for performance monitoring), but
  518. writing the registers will most likely crash the kernel.
  519. config GPTMR0_CLOCKSOURCE
  520. bool "Use GPTimer0 as a clocksource (higher rating)"
  521. depends on GENERIC_CLOCKEVENTS
  522. depends on !TICKSOURCE_GPTMR0
  523. source kernel/time/Kconfig
  524. comment "Misc"
  525. choice
  526. prompt "Blackfin Exception Scratch Register"
  527. default BFIN_SCRATCH_REG_RETN
  528. help
  529. Select the resource to reserve for the Exception handler:
  530. - RETN: Non-Maskable Interrupt (NMI)
  531. - RETE: Exception Return (JTAG/ICE)
  532. - CYCLES: Performance counter
  533. If you are unsure, please select "RETN".
  534. config BFIN_SCRATCH_REG_RETN
  535. bool "RETN"
  536. help
  537. Use the RETN register in the Blackfin exception handler
  538. as a stack scratch register. This means you cannot
  539. safely use NMI on the Blackfin while running Linux, but
  540. you can debug the system with a JTAG ICE and use the
  541. CYCLES performance registers.
  542. If you are unsure, please select "RETN".
  543. config BFIN_SCRATCH_REG_RETE
  544. bool "RETE"
  545. help
  546. Use the RETE register in the Blackfin exception handler
  547. as a stack scratch register. This means you cannot
  548. safely use a JTAG ICE while debugging a Blackfin board,
  549. but you can safely use the CYCLES performance registers
  550. and the NMI.
  551. If you are unsure, please select "RETN".
  552. config BFIN_SCRATCH_REG_CYCLES
  553. bool "CYCLES"
  554. help
  555. Use the CYCLES register in the Blackfin exception handler
  556. as a stack scratch register. This means you cannot
  557. safely use the CYCLES performance registers on a Blackfin
  558. board at anytime, but you can debug the system with a JTAG
  559. ICE and use the NMI.
  560. If you are unsure, please select "RETN".
  561. endchoice
  562. endmenu
  563. menu "Blackfin Kernel Optimizations"
  564. depends on !SMP
  565. comment "Memory Optimizations"
  566. config I_ENTRY_L1
  567. bool "Locate interrupt entry code in L1 Memory"
  568. default y
  569. help
  570. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  571. into L1 instruction memory. (less latency)
  572. config EXCPT_IRQ_SYSC_L1
  573. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  574. default y
  575. help
  576. If enabled, the entire ASM lowlevel exception and interrupt entry code
  577. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  578. (less latency)
  579. config DO_IRQ_L1
  580. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  581. default y
  582. help
  583. If enabled, the frequently called do_irq dispatcher function is linked
  584. into L1 instruction memory. (less latency)
  585. config CORE_TIMER_IRQ_L1
  586. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  587. default y
  588. help
  589. If enabled, the frequently called timer_interrupt() function is linked
  590. into L1 instruction memory. (less latency)
  591. config IDLE_L1
  592. bool "Locate frequently idle function in L1 Memory"
  593. default y
  594. help
  595. If enabled, the frequently called idle function is linked
  596. into L1 instruction memory. (less latency)
  597. config SCHEDULE_L1
  598. bool "Locate kernel schedule function in L1 Memory"
  599. default y
  600. help
  601. If enabled, the frequently called kernel schedule is linked
  602. into L1 instruction memory. (less latency)
  603. config ARITHMETIC_OPS_L1
  604. bool "Locate kernel owned arithmetic functions in L1 Memory"
  605. default y
  606. help
  607. If enabled, arithmetic functions are linked
  608. into L1 instruction memory. (less latency)
  609. config ACCESS_OK_L1
  610. bool "Locate access_ok function in L1 Memory"
  611. default y
  612. help
  613. If enabled, the access_ok function is linked
  614. into L1 instruction memory. (less latency)
  615. config MEMSET_L1
  616. bool "Locate memset function in L1 Memory"
  617. default y
  618. help
  619. If enabled, the memset function is linked
  620. into L1 instruction memory. (less latency)
  621. config MEMCPY_L1
  622. bool "Locate memcpy function in L1 Memory"
  623. default y
  624. help
  625. If enabled, the memcpy function is linked
  626. into L1 instruction memory. (less latency)
  627. config SYS_BFIN_SPINLOCK_L1
  628. bool "Locate sys_bfin_spinlock function in L1 Memory"
  629. default y
  630. help
  631. If enabled, sys_bfin_spinlock function is linked
  632. into L1 instruction memory. (less latency)
  633. config IP_CHECKSUM_L1
  634. bool "Locate IP Checksum function in L1 Memory"
  635. default n
  636. help
  637. If enabled, the IP Checksum function is linked
  638. into L1 instruction memory. (less latency)
  639. config CACHELINE_ALIGNED_L1
  640. bool "Locate cacheline_aligned data to L1 Data Memory"
  641. default y if !BF54x
  642. default n if BF54x
  643. depends on !BF531
  644. help
  645. If enabled, cacheline_aligned data is linked
  646. into L1 data memory. (less latency)
  647. config SYSCALL_TAB_L1
  648. bool "Locate Syscall Table L1 Data Memory"
  649. default n
  650. depends on !BF531
  651. help
  652. If enabled, the Syscall LUT is linked
  653. into L1 data memory. (less latency)
  654. config CPLB_SWITCH_TAB_L1
  655. bool "Locate CPLB Switch Tables L1 Data Memory"
  656. default n
  657. depends on !BF531
  658. help
  659. If enabled, the CPLB Switch Tables are linked
  660. into L1 data memory. (less latency)
  661. config APP_STACK_L1
  662. bool "Support locating application stack in L1 Scratch Memory"
  663. default y
  664. help
  665. If enabled the application stack can be located in L1
  666. scratch memory (less latency).
  667. Currently only works with FLAT binaries.
  668. config EXCEPTION_L1_SCRATCH
  669. bool "Locate exception stack in L1 Scratch Memory"
  670. default n
  671. depends on !APP_STACK_L1
  672. help
  673. Whenever an exception occurs, use the L1 Scratch memory for
  674. stack storage. You cannot place the stacks of FLAT binaries
  675. in L1 when using this option.
  676. If you don't use L1 Scratch, then you should say Y here.
  677. comment "Speed Optimizations"
  678. config BFIN_INS_LOWOVERHEAD
  679. bool "ins[bwl] low overhead, higher interrupt latency"
  680. default y
  681. help
  682. Reads on the Blackfin are speculative. In Blackfin terms, this means
  683. they can be interrupted at any time (even after they have been issued
  684. on to the external bus), and re-issued after the interrupt occurs.
  685. For memory - this is not a big deal, since memory does not change if
  686. it sees a read.
  687. If a FIFO is sitting on the end of the read, it will see two reads,
  688. when the core only sees one since the FIFO receives both the read
  689. which is cancelled (and not delivered to the core) and the one which
  690. is re-issued (which is delivered to the core).
  691. To solve this, interrupts are turned off before reads occur to
  692. I/O space. This option controls which the overhead/latency of
  693. controlling interrupts during this time
  694. "n" turns interrupts off every read
  695. (higher overhead, but lower interrupt latency)
  696. "y" turns interrupts off every loop
  697. (low overhead, but longer interrupt latency)
  698. default behavior is to leave this set to on (type "Y"). If you are experiencing
  699. interrupt latency issues, it is safe and OK to turn this off.
  700. endmenu
  701. choice
  702. prompt "Kernel executes from"
  703. help
  704. Choose the memory type that the kernel will be running in.
  705. config RAMKERNEL
  706. bool "RAM"
  707. help
  708. The kernel will be resident in RAM when running.
  709. config ROMKERNEL
  710. bool "ROM"
  711. help
  712. The kernel will be resident in FLASH/ROM when running.
  713. endchoice
  714. source "mm/Kconfig"
  715. config BFIN_GPTIMERS
  716. tristate "Enable Blackfin General Purpose Timers API"
  717. default n
  718. help
  719. Enable support for the General Purpose Timers API. If you
  720. are unsure, say N.
  721. To compile this driver as a module, choose M here: the module
  722. will be called gptimers.
  723. choice
  724. prompt "Uncached DMA region"
  725. default DMA_UNCACHED_1M
  726. config DMA_UNCACHED_4M
  727. bool "Enable 4M DMA region"
  728. config DMA_UNCACHED_2M
  729. bool "Enable 2M DMA region"
  730. config DMA_UNCACHED_1M
  731. bool "Enable 1M DMA region"
  732. config DMA_UNCACHED_NONE
  733. bool "Disable DMA region"
  734. endchoice
  735. comment "Cache Support"
  736. config BFIN_ICACHE
  737. bool "Enable ICACHE"
  738. default y
  739. config BFIN_ICACHE_LOCK
  740. bool "Enable Instruction Cache Locking"
  741. depends on BFIN_ICACHE
  742. default n
  743. config BFIN_EXTMEM_ICACHEABLE
  744. bool "Enable ICACHE for external memory"
  745. depends on BFIN_ICACHE
  746. default y
  747. config BFIN_L2_ICACHEABLE
  748. bool "Enable ICACHE for L2 SRAM"
  749. depends on BFIN_ICACHE
  750. depends on BF54x || BF561
  751. default n
  752. config BFIN_DCACHE
  753. bool "Enable DCACHE"
  754. default y
  755. config BFIN_DCACHE_BANKA
  756. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  757. depends on BFIN_DCACHE && !BF531
  758. default n
  759. config BFIN_EXTMEM_DCACHEABLE
  760. bool "Enable DCACHE for external memory"
  761. depends on BFIN_DCACHE
  762. default y
  763. choice
  764. prompt "External memory DCACHE policy"
  765. depends on BFIN_EXTMEM_DCACHEABLE
  766. default BFIN_EXTMEM_WRITEBACK if !SMP
  767. default BFIN_EXTMEM_WRITETHROUGH if SMP
  768. config BFIN_EXTMEM_WRITEBACK
  769. bool "Write back"
  770. depends on !SMP
  771. help
  772. Write Back Policy:
  773. Cached data will be written back to SDRAM only when needed.
  774. This can give a nice increase in performance, but beware of
  775. broken drivers that do not properly invalidate/flush their
  776. cache.
  777. Write Through Policy:
  778. Cached data will always be written back to SDRAM when the
  779. cache is updated. This is a completely safe setting, but
  780. performance is worse than Write Back.
  781. If you are unsure of the options and you want to be safe,
  782. then go with Write Through.
  783. config BFIN_EXTMEM_WRITETHROUGH
  784. bool "Write through"
  785. help
  786. Write Back Policy:
  787. Cached data will be written back to SDRAM only when needed.
  788. This can give a nice increase in performance, but beware of
  789. broken drivers that do not properly invalidate/flush their
  790. cache.
  791. Write Through Policy:
  792. Cached data will always be written back to SDRAM when the
  793. cache is updated. This is a completely safe setting, but
  794. performance is worse than Write Back.
  795. If you are unsure of the options and you want to be safe,
  796. then go with Write Through.
  797. endchoice
  798. config BFIN_L2_DCACHEABLE
  799. bool "Enable DCACHE for L2 SRAM"
  800. depends on BFIN_DCACHE
  801. depends on BF54x || BF561
  802. default n
  803. choice
  804. prompt "L2 SRAM DCACHE policy"
  805. depends on BFIN_L2_DCACHEABLE
  806. default BFIN_L2_WRITEBACK
  807. config BFIN_L2_WRITEBACK
  808. bool "Write back"
  809. depends on !SMP
  810. config BFIN_L2_WRITETHROUGH
  811. bool "Write through"
  812. depends on !SMP
  813. endchoice
  814. comment "Memory Protection Unit"
  815. config MPU
  816. bool "Enable the memory protection unit (EXPERIMENTAL)"
  817. default n
  818. help
  819. Use the processor's MPU to protect applications from accessing
  820. memory they do not own. This comes at a performance penalty
  821. and is recommended only for debugging.
  822. comment "Asynchronous Memory Configuration"
  823. menu "EBIU_AMGCTL Global Control"
  824. config C_AMCKEN
  825. bool "Enable CLKOUT"
  826. default y
  827. config C_CDPRIO
  828. bool "DMA has priority over core for ext. accesses"
  829. default n
  830. config C_B0PEN
  831. depends on BF561
  832. bool "Bank 0 16 bit packing enable"
  833. default y
  834. config C_B1PEN
  835. depends on BF561
  836. bool "Bank 1 16 bit packing enable"
  837. default y
  838. config C_B2PEN
  839. depends on BF561
  840. bool "Bank 2 16 bit packing enable"
  841. default y
  842. config C_B3PEN
  843. depends on BF561
  844. bool "Bank 3 16 bit packing enable"
  845. default n
  846. choice
  847. prompt "Enable Asynchronous Memory Banks"
  848. default C_AMBEN_ALL
  849. config C_AMBEN
  850. bool "Disable All Banks"
  851. config C_AMBEN_B0
  852. bool "Enable Bank 0"
  853. config C_AMBEN_B0_B1
  854. bool "Enable Bank 0 & 1"
  855. config C_AMBEN_B0_B1_B2
  856. bool "Enable Bank 0 & 1 & 2"
  857. config C_AMBEN_ALL
  858. bool "Enable All Banks"
  859. endchoice
  860. endmenu
  861. menu "EBIU_AMBCTL Control"
  862. config BANK_0
  863. hex "Bank 0 (AMBCTL0.L)"
  864. default 0x7BB0
  865. help
  866. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  867. used to control the Asynchronous Memory Bank 0 settings.
  868. config BANK_1
  869. hex "Bank 1 (AMBCTL0.H)"
  870. default 0x7BB0
  871. default 0x5558 if BF54x
  872. help
  873. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  874. used to control the Asynchronous Memory Bank 1 settings.
  875. config BANK_2
  876. hex "Bank 2 (AMBCTL1.L)"
  877. default 0x7BB0
  878. help
  879. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  880. used to control the Asynchronous Memory Bank 2 settings.
  881. config BANK_3
  882. hex "Bank 3 (AMBCTL1.H)"
  883. default 0x99B3
  884. help
  885. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  886. used to control the Asynchronous Memory Bank 3 settings.
  887. endmenu
  888. config EBIU_MBSCTLVAL
  889. hex "EBIU Bank Select Control Register"
  890. depends on BF54x
  891. default 0
  892. config EBIU_MODEVAL
  893. hex "Flash Memory Mode Control Register"
  894. depends on BF54x
  895. default 1
  896. config EBIU_FCTLVAL
  897. hex "Flash Memory Bank Control Register"
  898. depends on BF54x
  899. default 6
  900. endmenu
  901. #############################################################################
  902. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  903. config PCI
  904. bool "PCI support"
  905. depends on BROKEN
  906. help
  907. Support for PCI bus.
  908. source "drivers/pci/Kconfig"
  909. config HOTPLUG
  910. bool "Support for hot-pluggable device"
  911. help
  912. Say Y here if you want to plug devices into your computer while
  913. the system is running, and be able to use them quickly. In many
  914. cases, the devices can likewise be unplugged at any time too.
  915. One well known example of this is PCMCIA- or PC-cards, credit-card
  916. size devices such as network cards, modems or hard drives which are
  917. plugged into slots found on all modern laptop computers. Another
  918. example, used on modern desktops as well as laptops, is USB.
  919. Enable HOTPLUG and build a modular kernel. Get agent software
  920. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  921. Then your kernel will automatically call out to a user mode "policy
  922. agent" (/sbin/hotplug) to load modules and set up software needed
  923. to use devices as you hotplug them.
  924. source "drivers/pcmcia/Kconfig"
  925. source "drivers/pci/hotplug/Kconfig"
  926. endmenu
  927. menu "Executable file formats"
  928. source "fs/Kconfig.binfmt"
  929. endmenu
  930. menu "Power management options"
  931. source "kernel/power/Kconfig"
  932. config ARCH_SUSPEND_POSSIBLE
  933. def_bool y
  934. depends on !SMP
  935. choice
  936. prompt "Standby Power Saving Mode"
  937. depends on PM
  938. default PM_BFIN_SLEEP_DEEPER
  939. config PM_BFIN_SLEEP_DEEPER
  940. bool "Sleep Deeper"
  941. help
  942. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  943. power dissipation by disabling the clock to the processor core (CCLK).
  944. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  945. to 0.85 V to provide the greatest power savings, while preserving the
  946. processor state.
  947. The PLL and system clock (SCLK) continue to operate at a very low
  948. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  949. the SDRAM is put into Self Refresh Mode. Typically an external event
  950. such as GPIO interrupt or RTC activity wakes up the processor.
  951. Various Peripherals such as UART, SPORT, PPI may not function as
  952. normal during Sleep Deeper, due to the reduced SCLK frequency.
  953. When in the sleep mode, system DMA access to L1 memory is not supported.
  954. If unsure, select "Sleep Deeper".
  955. config PM_BFIN_SLEEP
  956. bool "Sleep"
  957. help
  958. Sleep Mode (High Power Savings) - The sleep mode reduces power
  959. dissipation by disabling the clock to the processor core (CCLK).
  960. The PLL and system clock (SCLK), however, continue to operate in
  961. this mode. Typically an external event or RTC activity will wake
  962. up the processor. When in the sleep mode, system DMA access to L1
  963. memory is not supported.
  964. If unsure, select "Sleep Deeper".
  965. endchoice
  966. config PM_WAKEUP_BY_GPIO
  967. bool "Allow Wakeup from Standby by GPIO"
  968. depends on PM && !BF54x
  969. config PM_WAKEUP_GPIO_NUMBER
  970. int "GPIO number"
  971. range 0 47
  972. depends on PM_WAKEUP_BY_GPIO
  973. default 2
  974. choice
  975. prompt "GPIO Polarity"
  976. depends on PM_WAKEUP_BY_GPIO
  977. default PM_WAKEUP_GPIO_POLAR_H
  978. config PM_WAKEUP_GPIO_POLAR_H
  979. bool "Active High"
  980. config PM_WAKEUP_GPIO_POLAR_L
  981. bool "Active Low"
  982. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  983. bool "Falling EDGE"
  984. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  985. bool "Rising EDGE"
  986. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  987. bool "Both EDGE"
  988. endchoice
  989. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  990. depends on PM
  991. config PM_BFIN_WAKE_PH6
  992. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  993. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  994. default n
  995. help
  996. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  997. config PM_BFIN_WAKE_GP
  998. bool "Allow Wake-Up from GPIOs"
  999. depends on PM && BF54x
  1000. default n
  1001. help
  1002. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  1003. (all processors, except ADSP-BF549). This option sets
  1004. the general-purpose wake-up enable (GPWE) control bit to enable
  1005. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  1006. On ADSP-BF549 this option enables the the same functionality on the
  1007. /MRXON pin also PH7.
  1008. endmenu
  1009. menu "CPU Frequency scaling"
  1010. source "drivers/cpufreq/Kconfig"
  1011. config BFIN_CPU_FREQ
  1012. bool
  1013. depends on CPU_FREQ
  1014. select CPU_FREQ_TABLE
  1015. default y
  1016. config CPU_VOLTAGE
  1017. bool "CPU Voltage scaling"
  1018. depends on EXPERIMENTAL
  1019. depends on CPU_FREQ
  1020. default n
  1021. help
  1022. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1023. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1024. manuals. There is a theoretical risk that during VDDINT transitions
  1025. the PLL may unlock.
  1026. endmenu
  1027. source "net/Kconfig"
  1028. source "drivers/Kconfig"
  1029. source "fs/Kconfig"
  1030. source "arch/blackfin/Kconfig.debug"
  1031. source "security/Kconfig"
  1032. source "crypto/Kconfig"
  1033. source "lib/Kconfig"